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| hcs12 microcontrollers freescale.com mc9s12e256 data sheet mc9s12e256 rev. 1.08 01/2006
mc9s12e256 data sheet mc9s12e256 rev. 1.08 01/2006 mc9s12e256 data sheet, rev. 1.08 4 freescale semiconductor to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summ arizes changes contained in this document. revision history date revision level description november 10, 2005 1.07 new data sheet january 18, 2005 1.08 table a-4. operating conditions ? updated minimum value for i/o, regulator and analog supply voltage table a-9. voltage regulator electrical parameters ? updated minimum value for low voltage interrupt for both assert level and deassrt level. freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2006. all rights reserved. mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 5 list of chapters chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) . . . . . . . 21 chapter 2 256 kbyte flash module (fts256k2v 1) . . . . . . . . . . . . . . . . . . 81 chapter 3 port integration mo dule (pim9e256v1). . . . . . . . . . . . . . . . . . 119 chapter 4 clocks and reset generator (crgv4 ) . . . . . . . . . . . . . . . . . . 165 chapter 5 oscillator (oscv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 chapter 6 analog-to-digital converter (a td10b16cv4) . . . . . . . . . . . . 205 chapter 7 digital-to-analog converter (dac8 b1cv1) . . . . . . . . . . . . . . 235 chapter 8 serial communication interface (sciv4) . . . . . . . . . . . . . . . . 243 chapter 9 serial peripheral in terface (spiv3) . . . . . . . . . . . . . . . . . . . . . 275 chapter 10 inter-integrated circuit (iicv2) . . . . . . . . . . . . . . . . . . . . . . . . 297 chapter 11 pulse width modula tor with fault protection (pmf15b6cv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 chapter 12 pulse-width modulator (pwm8b6cv1 ). . . . . . . . . . . . . . . . . . 377 chapter 13 timer module (tim16b4cv1) . . . . . . . . . . . . . . . . . . . . . . . . . . 411 chapter 14 dual output volt age regulator (vreg3v3v2). . . . . . . . . . . . 437 chapter 15 background debug module (bdmv4). . . . . . . . . . . . . . . . . . . 445 chapter 16 debug module (dbgv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 chapter 17 interrupt (intv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 chapter 18 multiplexed external bus interf ace (mebiv3) . . . . . . . . . . . . 509 chapter 19 module mapping control (mmcv4) . . . . . . . . . . . . . . . . . . . . . 541 appendix a electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 appendix b ordering information and mech anical drawings. . . . . . . . . . 594 list of chapters mc9s12e256 data sheet, rev. 1.08 6 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 7 contents section number title page chapter 1 mc9s12e256 device over view (mc9s12e256dgv1) 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2.1 detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2.2 part id assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1.3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1.3.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1.3.2 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 1.4 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4.1 extal, xtal ? oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4.2 reset ? external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4.3 test ? test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4.4 xfc ? pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4.5 bkgd / taghi / modc ? background debug, tag high & mode pin . . . . . . . . . . . 61 1.4.6 pa[7:0] / addr[15:8] / data[15:8] ? port a i/o pi ns . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4.7 pb[7:0] / addr[7:0] / data[7:0] ? port b i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4.8 pe7 / noacc / xclks ? port e i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.4.9 pe6 / modb / ipipe1 ? port e i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.4.10 pe5 / moda / ipipe0 ? port e i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.4.11 pe4 / eclk? port e i/o pin 4 / e- clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.4.12 pe3 / lstrb / taglo ? port e i/o pin 3 / low-byte strobe (lstrb) . . . . . . . . . . 63 1.4.13 pe2 / r/w ? port e i/o pin 2 / read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.4.14 pe1 / irq ? port e input pin 1 / maskable interrupt pin . . . . . . . . . . . . . . . . . . . . . . . 63 1.4.15 pe0 / xirq ? port e input pin 0 / non maskable interrupt pin . . . . . . . . . . . . . . . . . . 64 1.4.16 pk7 / ecs / romctl ? port k i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.4.17 pk6 / xcs ? port k i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.4.18 pk[5:0] / xaddr[19:14] ? port k i/o pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.4.19 pad[15:0] / an[15:0] / kwad[15:0] ? port ad i/o pins [15:0] . . . . . . . . . . . . . . . . 65 1.4.20 pm7 / scl ? port m i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.4.21 pm6 / sda ? port m i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.4.22 pm5 / txd2 ? port m i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.4.23 pm4 / rxd2 ? port m i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.4.24 pm3 ? port m i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.4.25 pm1 / dao1 ? port m i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 contents mc9s12e256 data sheet, rev. 1.08 8 freescale semiconductor section number title page 1.4.26 pm0 / dao2 ? port m i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.4.27 pp[5:0] / pw0[5:0] ? port p i/o pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.4.28 pq[6:4] / is[2:0] ? port q i/o pins [6:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.4.29 pq[3:0] / fault[3:0] ? port q i/o pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.4.30 ps7 / ss ? port s i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.4.31 ps6 / sck ? port s i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.32 ps5 / mosi ? port s i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.33 ps4 / miso ? port s i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.34 ps3 / txd1 ? port s i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.35 ps2 / rxd1 ? port s i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.36 ps1 / txd0 ? port s i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.37 ps0 / rxd0 ? port s i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.4.38 pt[7:4] / ioc1[7:4]? port t i/o pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.4.39 pt[3:0] / ioc0[7:4]? port t i/o pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.4.40 pu[7:6] ? port u i/o pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.4.41 pu[5:4] / pw1[5:4] ? port u i/o pins [5:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.4.42 pu[3:0] / ioc2[7:4]/pw1[3:0] ? port u i/o pins [3:0 ] . . . . . . . . . . . . . . . . . . . . . . . . 68 1.4.43 vddx,vssx ? power & ground pins for i/o drivers . . . . . . . . . . . . . . . . . . . . . . . . 69 1.4.44 vddr, vssr ? power supply pins for i/o dr ivers & for internal voltage regulator 69 1.4.45 vdd1, vdd2, vss1, vss2 ? power supply pins for internal logic . . . . . . . . . . . . . 69 1.4.46 vdda, vssa ? power supply pins for atd and vreg . . . . . . . . . . . . . . . . . . . . . . 69 1.4.47 vrh, vrl ? atd reference voltage i nput pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.4.48 vddpll, vsspll ? power supply pins for pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.5 system clock description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.6.2 chip configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.7 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1.7.1 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 1.7.2 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1.7.3 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1.8 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8.2 pseudo stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8.3 wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8.4 run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.9 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.9.1 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.9.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.10 recommended printed circuit board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 contents mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 9 section number title page chapter 2 256 kbyte flash module (fts256k2v1) 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 2.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.4.1 flash command operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.5.3 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.6 flash module security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.6.1 unsecuring the mcu using backdoor ke y access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.6.2 unsecuring the flash module in special single-ch ip mode using bdm . . . . . . . . . . . 117 2.7 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.7.1 flash reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.7.2 reset while flash command active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.8.1 description of flash interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 chapter 3 port integration module (pim9e256v1) 3.1 lntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.3.1 port ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.3.2 port m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.3.3 port p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.3.4 port q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 3.3.5 port s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 3.3.6 port t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.3.7 port u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 contents mc9s12e256 data sheet, rev. 1.08 10 freescale semiconductor section number title page 3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.4.1 i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.4.2 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.4.3 data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.4.4 reduced drive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 59 3.4.5 pull device enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 3.4.6 polarity select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.4.7 pin configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.5.1 reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 3.6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 3.6.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 3.6.3 operation in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 63 chapter 4 clocks and reset generator (crgv4) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 4.2.1 v ddpll , v sspll ? pll operating voltage, pll ground . . . . . . . . . . . . . . . . . . . . . . 167 4.2.2 xfc ? pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 4.2.3 reset ? reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.4.1 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.4.2 system clocks generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 4.4.3 clock monitor (cm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 4.4.4 clock quality checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 4.4.5 computer operating properly watchdog (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 4.4.6 real-time interrupt (rti) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 87 4.4.7 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.4.8 low-power operation in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.4.9 low-power operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.4.10 low-power operation in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 contents mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 11 section number title page 4.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.5.1 clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.5.2 computer operating properly watchdog (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.5.3 power-on reset, low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 4.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.6.1 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.6.2 pll lock interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.6.3 self-clock mode interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 0 chapter 5 oscillator (oscv2) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 5.2.1 v ddpll and v sspll ? pll operating voltage, pll ground . . . . . . . . . . . . . . . . . . . 202 5.2.2 extal and xtal ? clock/crystal source pi ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 5.2.3 xclks ? colpitts/pierce oscillator selection signal . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 5.4.1 amplitude limitation control (alc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 5.4.2 clock monitor (cm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 5.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 chapter 6 analog-to-digital con verter (atd10b16cv4) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.2.1 anx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) ? analog input channel x pins 207 6.2.2 etrig3, etrig2, etrig1, etrig0 ? ex ternal trigger pins . . . . . . . . . . . . . . . . . 207 6.2.3 v rh , v rl ? high reference voltage pin, low reference voltage pin . . . . . . . . . . . 207 6.2.4 v dda , v ssa ? analog circuitry power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 contents mc9s12e256 data sheet, rev. 1.08 12 freescale semiconductor section number title page 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.4.1 analog sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.4.2 digital sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 6.4.3 operation in low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 6.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 6.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 chapter 7 digital-to-analog converter (dac8b1cv1) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 7.2.1 dao ? dac channel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.2.2 v dda ? dac power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.2.3 v ssa ? dac ground supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.2.4 v ref ? dac reference supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.2.5 v rl ? dac reference ground supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.4.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 7.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 chapter 8 serial communication interface (sciv4) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 8.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 8.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.2.1 txd ? sci transmit pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.2.2 rxd ? sci receive pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 contents mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 13 section number title page 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 8.4.1 infrared interface submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 8.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 8.4.3 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 8.4.4 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 8.4.5 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.4.6 single-wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 8.4.7 loop operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 8.5.1 description of interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 8.5.2 recovery from wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 chapter 9 serial peripheral interface (spiv3) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 9.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 9.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 9.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2.1 mosi ? master out/slave in pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2.2 miso ? master in/slave out pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.2.3 ss ? slave select pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.2.4 sck ? serial clock pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 9.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.4.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 9.4.3 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 9.4.4 spi baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 9.4.5 special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 9.4.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 9.4.7 operation in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 9.4.8 operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 94 9.4.9 operation in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 94 9.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.6.1 modf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.6.2 spif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.6.3 sptef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 contents mc9s12e256 data sheet, rev. 1.08 14 freescale semiconductor section number title page chapter 10 inter-integrated circuit (iicv2) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 10.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 10.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 10.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 10.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 10.2.1 iic_scl ? serial clock line pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 10.2.2 iic_sda ? serial data line pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 10.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 10.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 10.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 10.4.1 i-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 10.4.2 operation in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 13 10.4.3 operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 10.4.4 operation in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 10.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 10.7 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 10.7.1 iic programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 11.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 11.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 11.1.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 11.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.2.1 pwm0?pwm5 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.2.2 fault0?fault3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.2.3 is0?is2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 11.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3 11.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 11.4.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 11.4.2 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 11.4.3 pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 11.4.4 independent or complementary ch annel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 11.4.5 deadtime generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 11.4.6 software output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 contents mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 15 section number title page 11.4.7 pwm generator loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 11.4.8 fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 11.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 11.6 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 11.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 chapter 12 pulse-width modulator (pwm8b6cv1) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 12.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 12.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 12.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.2.1 pwm5 ? pulse width modulator channel 5 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.2.2 pwm4 ? pulse width modulator channel 4 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.2.3 pwm3 ? pulse width modulator channel 3 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.2.4 pwm2 ? pulse width modulator channel 2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 12.2.5 pwm1 ? pulse width modulator channel 1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 12.2.6 pwm0 ? pulse width modulator channel 0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 12.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 12.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 12.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 12.4.1 pwm clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 12.4.2 pwm channel timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2 12.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 12.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 chapter 13 timer module (tim16b4cv1) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 13.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 13.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 13.1.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 13.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.2.1 ioc7 ? input capture and output compare channel 7 pin . . . . . . . . . . . . . . . . . . . . 414 13.2.2 ioc6 ? input capture and output compare channel 6 pin . . . . . . . . . . . . . . . . . . . . 414 13.2.3 ioc5 ? input capture and output compare channel 5 pin . . . . . . . . . . . . . . . . . . . . 414 13.2.4 ioc4 ? input capture and output compare channel 4 pin . . . . . . . . . . . . . . . . . . . . 414 13.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 13.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 contents mc9s12e256 data sheet, rev. 1.08 16 freescale semiconductor section number title page 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 13.4.1 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 13.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 13.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 13.4.4 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 13.4.5 event counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 13.4.6 gated time accumulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 13.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 13.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 13.6.1 channel [7:4] interrupt (c[7:4]f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 13.6.2 pulse accumulator input interrupt (paovi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 13.6.3 pulse accumulator overflow interrupt (paovf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 13.6.4 timer overflow interrupt (tof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 chapter 14 dual output voltage regulator (vreg3v3v2) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 14.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 14.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 14.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 14.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.2.1 v ddr ? regulator power input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.2.2 v dda , v ssa ? regulator reference supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.2.3 v dd , v ss ? regulator output1 (core logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 14.2.4 v ddpll , v sspll ? regulator output2 (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 14.2.5 v regen ? optional regulator enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 14.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 14.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 0 14.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 14.4.1 reg ? regulator core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1 14.4.2 full-performance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 42 14.4.3 reduced-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 42 14.4.4 lvd ? low-voltage detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 14.4.5 por ? power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 14.4.6 lvr ? low-voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 14.4.7 ctrl ? regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 14.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 14.5.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 14.5.2 low-voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 14.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 14.6.1 lvi ? low-voltage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 contents mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 17 section number title page chapter 15 background debug module (bdmv4) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 15.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 15.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 15.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 15.2.1 bkgd ? background interface pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 15.2.2 taghi ? high byte instruction tagging pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 15.2.3 taglo ? low byte instruction tagging pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 15.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 15.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 15.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 15.4.1 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 15.4.2 enabling and activating bdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 15.4.3 bdm hardware commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 15.4.4 standard bdm firmware commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 15.4.5 bdm command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 15.4.6 bdm serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 15.4.7 serial interface hardware handshake protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 15.4.8 hardware handshake abort procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 15.4.9 sync ? request timed reference pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 15.4.10instruction tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 15.4.11instruction tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 15.4.12serial communication time -out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 15.4.13operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 15.4.14operation in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 chapter 16 debug module (dbgv1) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 16.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 16.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 16.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 16.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4 16.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 16.4.1 dbg operating in bkp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 16.4.2 dbg operating in dbg mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 16.4.3 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 contents mc9s12e256 data sheet, rev. 1.08 18 freescale semiconductor section number title page 16.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 16.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 chapter 17 interrupt (intv1) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 17.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 17.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 17.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3 17.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.6.1 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.6.2 highest priority i-bit maskable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.6.3 interrupt priority decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.7 exception priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 chapter 18 multiplexed external bus interface (mebiv3) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 18.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 18.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 18.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 18.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4 18.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 18.4.1 detecting access type from external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 18.4.2 stretched bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 18.4.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 18.4.4 internal visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 18.4.5 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 contents mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 19 section number title page chapter 19 module mapping control (mmcv4) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 19.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 19.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 19.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 19.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 19.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3 19.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 19.4.1 bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 19.4.2 address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 19.4.3 memory expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 appendix a electrical characteristics a.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 a.1.4 current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 a.2 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 a.2.1 chip power-up and lvi/lvr graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . . 570 a.2.2 output loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 a.3 startup, oscillator, and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 a.3.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 a.3.2 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 a.3.3 phase locked loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 a.4 flash nvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 a.4.1 nvm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 a.4.2 nvm reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 a.5 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 a.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 a.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 contents mc9s12e256 data sheet, rev. 1.08 20 freescale semiconductor section number title page a.6 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 a.6.1 atd operating characteristics ? 5v range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 a.6.2 atd operating characteristics ? 3.3v range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 a.6.3 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 a.6.4 atd accuracy ? 5v range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 a.6.5 atd accuracy ? 3.3v range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 a.7 dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 a.7.1 dac operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 a.8 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 appendix b ordering information an d mechanical drawings mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 21 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) 1.1 introduction the mc9s12e256 is a 112/80 pin low cost general purpose mcu comprised of standard on-chip peripherals including a 16- bit central processing unit (hcs12 cpu) , 256k bytes of flash eeprom, 16k bytes of ram, three asynchronous se rial communications interface modul es (sci), a serial peripheral interface (spi), an inter-ic bus (iic), three 4-channel 16-bit timer modules (tim), a 6-channel 15-bit pulse modulator with fault protect ion module (pmf), a 6- channel 8-bit pulse width modulator (pwm), a 16-channel 10-bit analog-to-digit al converter (adc), and two 1- channel 8-bit digital-to-analog converters (dac). the mc9s12e256 has full 16-bit data paths throughout. the incl usion of a pll circuit allows power consumption a nd performance to be adjusted to suit operational requirements. in addition to the i/o ports available on each module, 16 dedicated i/ o port bits are available with wake-up capability from stop or wait mode. furthe rmore, an on chip bandgap based vol tage regulator (vreg) generates the internal digital supply voltage of 2.5v (vdd) from a 2.97v to 5.5v external supply range. 1.1.1 features ? 16-bit hcs12 core ? hcs12 cpu ? upward compatible with m68hc11 instruction set ? interrupt stacking and programme r?s model identical to m68hc11 ? instruction queue ? enhanced indexed addressing ? module mapping control (mmc) ? interrupt control (int) ? background debug module (bdm) ? debugger (dbg12) including breakpoints and change-of-flow trace buffer ? multiplexed external bus interface (mebi) ? wake-up interrupt inputs ? up to 16 port bits available for wake up interrupt function with digital filtering ? memory ? 256k byte flash eeprom ? 16k byte ram chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 22 freescale semiconductor ? two 1-channel digital-to -analog converters (dac) ? 8-bit resolution ? analog-to-digital converter (adc) ? 16-channel module with 10-bit resolution ? external conversion trigger capability ? three 4-channel timers (tim) ? programmable input capture or output compare channels ? simple pwm mode ? counter modulo reset ? external event counting ? gated time accumulation ? 6 pwm channels (pwm) ? programmable period and duty cycle ? 8-bit 6-channel or 16-bit 3-channel ? separate control for each pulse width and duty cycle ? center-aligned or left-aligned outputs ? programmable clock select logic wi th a wide range of frequencies ? fast emergency shutdown input ? 6-channel pulse width modulator with fault protection (pmf) ? three independent 15-bit c ounters with synchronous mode ? complementary ch annel operation ? edge and center aligned pwm signals ? programmable dead time insertion ? integral reload rates from 1 to 16 ? four fault protection shut down input pins ? three current sense input pins ? serial interfaces ? three asynchronous serial co mmunication interfaces (sci) ? synchronous serial peripheral interface (spi) ? inter-ic bus (iic) ? clock and reset generator (crg) ? windowed cop watchdog ? real time interrupt ? clock monitor ? pierce or low current colpitts oscillator ? phase-locked loop clock frequency multiplier ? self clock mode in absence of external clock ? low power 0.5 to 16mhz crystal oscillator reference clock chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 23 ? operating frequency ? 50mhz equivalent to 25mhz bus speed ? internal 2.5v regulator ? input voltage range from 2.97v to 5.5v ? low power mode capability ? includes low voltage reset (lvr) circuitry ? includes low voltage interrupt (lvi) circuitry ? 112-pin lqfp or 80-pin qfp package ? up to 90 i/o lines with 5v input and drive capability (112 pin package) ? up to two dedicated 5v input only lines (irq and xirq) ? sixteen 3.3v/5v a/ d converter inputs ? development support. ? single-wire background debug tm mode ? on-chip hardware breakpoints ? enhanced debug features 1.1.2 modes of operation user modes (expanded modes are only available in the 112-pin package version) ? normal modes ? normal single-chip mode ? normal expanded wide mode ? normal expanded narrow mode ? emulation expanded wide mode ? emulation expanded narrow mode ? special operating modes ? special single-chip mode with active background debug mode ? special test mode (freescale use only) ? special peripheral mode (freescale use only) ? low power modes ? stop mode ? pseudo stop mode ? wait mode chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 24 freescale semiconductor 1.1.3 block diagram figure 1-1. mc9s12e256 block diagram 256k byte flash eeprom 16k byte ram reset extal xtal sci0 bkgd r/w modb/ipipe1 xirq noacc/xclks system integration module (sim) vddr cpu12 periodic interrupt cop watchdog clock monitor single-wire background debugger(dbg12) crg xfc multiplexed address/data bus vrh vrl multiplexed wide bus multiplexed vddx vssx narrow bus irq lstrb /taglo eclk moda/ipipe0 pa4 pa3 pa2 pa1 pa0 pa7 pa6 pa5 test addr12 addr11 addr10 addr9 addr8 addr15 addr14 addr13 data12 data11 data10 data9 data8 data15 data14 data13 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 addr4 addr3 addr2 addr1 addr0 addr7 addr6 addr5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 pe3 pe4 pe5 pe6 pe7 pe0 pe1 pe2 ioc06 ioc16 ioc04 ioc17 ioc05 ioc07 ioc14 ioc15 pt3 pt4 pt5 pt6 pt7 pt0 pt1 pt2 adc an2 an6 an0 an7 an1 an3 an4 an5 pad3 pad4 pad5 pad6 pad7 pad0 pad1 pad2 rxd0 txd0 ps3 ps4 ps5 ps0 ps1 ps2 sci1 rxd1 txd1 pq3 pq4 pq5 pq6 pq0 pq1 pq2 ps6 ps7 i/o driver 3.3v/5v vdda vssa ddra ddrb pta ptb ddre pte ptt ddrt ptq pts clock and reset generation voltage regulator vssr debug module vddr vssr voltage regulator 3.3v/5v tim0 pw01 pw00 pad dao0 dao1 pp3 pp4 pp5 pp2 ptp ddrp an10 an11 an8 an9 pad8 pad9 pad10 pad11 pad12 pad13 kwad3 kwad4 kwad5 kwad6 kwad7 kwad0 kwad1 kwad2 kwad8 kwad9 kwad10 kwad11 kwad12 kwad13 tim1 spi miso mosi sck rxd2 txd2 pm7 pm4 pm5 pm6 sda scl ptm ss ddrm ddrs an12 an13 an14 an15 kwad14 kwad15 pad14 pad15 signals shown in bold are not available on the 80 pin package pm0 pm1 pk3 pk4 pk5 pk6 pk0 pk1 pk2 ddrk ptk xaddr14 xaddr15 xaddr16 xaddr17 xaddr18 xaddr19 xcs vddpll vsspll pll 2.5v vdd1,2 vss1,2 internal logic 2.5v iic sci2 pp0 pp1 pu3 pu4 pu5 pu6 pu7 pu0 pu1 pu2 ptu ddru pm3 pmf pw03 pw02 pw05 pw04 fault1 fault0 fault3 fault2 is1 is0 is2 pk7 ecs adc/dac 3.3v/5v voltage reference breakpoints dac0 dac1 ddrq modc/taghi ioc24 ioc25 ioc26 ioc27 tim2 pw12 pw13 pw14 pw15 pwm pw10 pw11 mux ddrad chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 25 1.2 device memory map table 1-1 shows the device register map of the mc9s12e256 after reset. figure 1-2 illustrates the device memory map with flash and ram. table 1-1. device register map overview address module size 0x0000?0x0017 core (ports a, b, e, modes, inits, test) 24 0x0018 reserved 1 0x0019 voltage regulator (vreg) 1 0x001a?0x001b device id register (partid) 2 0x001c?0x001f core (mem siz, irq, hprio) 4 0x0020?0x002f core (dbg) 16 0x0030?0x0033 core (ppage, port k) 4 0x0034?0x003f clock and reset generator (pll, rti, cop) 12 0x0040?0x006f standard timer 16-bit 4 channels (tim0) 48 0x0070?0x007f reserved 16 0x0080?0x00af analog to digital converter 10-bit 16 channels (atd) 48 0x00b0?0x00c7 reserved 24 0x00c8?0x00cf serial communications interface 0 (sci0) 8 0x00d0?0x00d7 serial communications interface 1 (sci1) 8 0x00d8?0x00df serial peripheral interface (spi) 8 0x00e0?0x00e7 inter ic bus 8 0x00e8?0x00ef serial communications interface 2 (sci2) 8 0x00f0?0x00f3 digital to analog converter 8-bit 1-channel (dac0) 4 0x00f4?0x00f7 digital to analog converter 8-bit 1-channel (dac1) 4 0x00f8?0x00ff reserved 8 0x0100- 0x010f flash control register 16 0x0110?0x013f reserved 48 0x0140?0x016f standard timer 16-bit 4 channels (tim1) 48 0x0170?0x017f reserved 16 0x0180?0x01af standard timer 16-bit 4 channels (tim2) 48 0x01b0?0x01df reserved 48 0x01e0?0x01ff pulse width modulator 8-bit 6 channels (pwm) 32 0x0200?0x023f pulse width modulator with fault 15-bit 6 channels (pmf) 64 0x0240?0x027f port integration module (pim) 64 0x0280?0x03ff reserved 384 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 26 freescale semiconductor figure 1-2. mc9s12e256 user configurable memory map vectors 0x0000 0xffff 0xc000 0x8000 0x4000 0x0400 0xff00 ext normal single chip expanded special single chip 0xff00 0xffff bdm (if active) 0xc000 0xffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector 0x8000 0xbfff 16k page window sixteen * 16k flash eeprom pages 0x4000 0x7fff 16k bytes ram mappable to any 16k boundary 0x0000 0x03ff 1k register space mappable to any 2k boundary the figure shows a useful map, which is not the map out of reset. after reset the map is: 0x0000?0x03ff: register space 0x0000?0x3fff: 16k ram (only 15 k ram visible 0x0400?0x3fff) vectors vectors chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 27 1.2.1 detailed register map 0x0000 ? 0x000f mebi map 1 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0000 porta r bit 7654321bit 0 w 0x0001 portb r bit 7654321bit 0 w 0x0002 ddra r bit 7654321bit 0 w 0x0003 ddrb r bit 7654321bit 0 w 0x0004 reserved r00000000 w 0x0005 reserved r00000000 w 0x0006 reserved r00000000 w 0x0007 reserved r00000000 w 0x0008 porte r bit 765432 bit 1 bit 0 w 0x0009 ddre r bit 76543bit 2 00 w 0x000a pear r noacce 0 pipoe neclk lstre rdwe 00 w 0x000b mode r modc modb moda 0 ivis 0 emk eme w 0x000c pucr r pupke 00 pupee 00 pupbe pupae w 0x000d rdriv r rdpk 00 rdpe 00 rdpb rdpa w 0x000e ebictl r0000000 estr w 0x000f reserved r00000000 w chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 28 freescale semiconductor 0x0010 ? 0x0014 mmc map 1 of 4 (h cs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0010 initrm r ram15 ram14 ram13 ram12 ram11 00 ramhal w 0x0011 initrg r0 reg14 reg13 reg12 reg11 000 w 0x0012 initee r ee15 ee14 ee13 ee12 ee11 00 eeon w 0x0013 misc r0000 exstr1 exstr0 romhm romon w 0x0014 mtst0 rbit 7654321bit 0 w 0x0015 ? 0x0016 int map 1 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0015 itcr r0 0 0 wrint adr3 adr2 adr1 adr0 w 0x0016 itest r inte intc inta int8 int6 int4 int2 int0 w 0x0017 ? 0x0017mmc map 2 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0017 mtst1 rbit 7654321bit 0 w 0x0018 ? 0x0018 misce llaneous peripherals (d evice user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0018 reserved r00000000 w 0x0019 ? 0x0019 vreg3v3 (voltage regulator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0019 vregctrl r00000lvds lv i e lv i f w chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 29 0x001a ? 0x001b miscella neous peripherals (device user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001a partidh r id15 id14 id13 id12 id11 id10 id9 id8 w 0x001b partidl r id7 id6 id5 id4 id3 id2 id1 id0 w 0x001c ? 0x001d mmc map 3 of 4 (hcs12 module mapping cont rol, device user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001c memsiz0 r reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 w 0x001d memsiz1 rrom_sw1rom_sw00000pag_sw1 pag_sw0 w 0x001e ? 0x001e mebi map 2 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001e intcr r irqe irqen 000000 w 0x001f ? 0x001f int map 2 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001f hprio r psel7 psel6 psel5 psel4 psel3 psel2 psel1 0 w 0x0020 ? 0x002f dbg (including bkp ) map 1 of 1 (hcs12 debug) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0020 dbgc1 r dbgen arm trgsel begin dbgbrk 0 capmod ?w 0x0021 dbgsc r af bf cf 0 trg ?w 0x0022 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ?w 0x0023 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ?w 0x0024 dbgcnt r tbf 0 cnt ?w 0x0025 dbgccx r pagsel extcmp ?w chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 30 freescale semiconductor 0x0026 dbgcch r bit 15 14 13 12 11 10 9 bit 8 ?w 0x0027 dbgccl r bit 7654321bit 0 ?w 0x0028 dbgc2 r bkaben full bdm tagab bkcen tagc rwcen rwc bkpct0 w 0x0029 dbgc3 r bkambh bkambl bkbmbh bkbmbl rwaen rwa rwben rwb bkpct1 w 0x002a dbgcax r pagsel extcmp bkp0x w 0x002b dbgcah r bit 15 14 13 12 11 10 9 bit 8 bkp0h w 0x002c dbgcal r bit 7654321bit 0 bkp0l w 0x002d dbgcbx r pagsel extcmp bkp1x w 0x002e dbgcbh r bit 15 14 13 12 11 10 9 bit 8 bkp1h w 0x002f dbgcbl r bit 7654321bit 0 bkp1l w 0x0030 ? 0x0031 mmc map 4 of 4 (h cs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0030 ppage r0 0 pix5 pix4 pix3 pix2 pix1 pix0 w 0x0031 reserved r00000000 w 0x0032 ? 0x0033 mebi map 3 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0032 portk r ecs xcs xab19 xab18 xab17 xab16 xab15 xab14 w 0x0033 ddrk r bit 7654321bit 0 w 0x0020 ? 0x002f dbg (includi ng bkp) map 1 of 1 ( hcs12 debug) (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 31 0x0034 ? 0x003f crg (clock and reset generator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0034 synr r0 0 syn5 syn4 syn3 syn2 syn1 syn0 w 0x0035 refdv r0000 refdv3 refdv2 refdv1 refdv0 w 0x0036 ctflg test only r tout7 tout6 tout5 tout4 tout3 tout2 tout1 tout0 w 0x0037 crgflg r rtif prof 0 lockif lock track scmif scm w 0x0038 crgint r rtie 00 lockie 00 scmie 0 w 0x0039 clksel r pllsel pstp syswai roawai pllwai cwai rtiwai copwai w 0x003a pllctl r cme pllon auto acq 0 pre pce scme w 0x003b rtictl r0 rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x003c copctl r wcop rsbck 000 cr2 cr1 cr0 w 0x003d forbyp test only r rtibyp copbyp 0 pllbyp 00 fcm 0 w 0x003e ctctl test only r tctl7 tctl6 tctl5 tctl4 tclt3 tctl2 tctl1 tctl0 w 0x003f armcop r00000000 wbit 7654321bit 0 0x0040 ? 0x006f tim0 (timer 16 bi t 4 channels) (s heet 1 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0040 tios r ios7 ios6 ios5 ios4 0000 w 0x0041 cforc r00000000 wfoc7foc6foc5foc4 0x0042 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 0000 w 0x0043 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 0000 w 0x0044 tcnt (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0045 tcnt (lo) rbit 7654321bit 0 w chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 32 freescale semiconductor 0x0046 tscr1 r ten tswai tsfrz tffca 0000 w 0x0047 ttov r tov7 tov6 tov5 tov4 0000 w 0x0048 tctl1 r om7ol7om6ol6om5ol5om4ol4 w 0x0049 reserved r00000000 w 0x004a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x004b reserved r00000000 w 0x004c tie r c7i c6i c5i c4i 0000 w 0x004d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x004e tflg1 r c7f c6f c5f c4f 0000 w 0x004f tflg2 r tof 0000000 w 0x0050 reserved r00000000 w 0x0051 reserved r00000000 w 0x0052 reserved r00000000 w 0x0053 reserved r00000000 w 0x0054 reserved r00000000 w 0x0055 reserved r00000000 w 0x0056 reserved r00000000 w 0x0057 reserved r00000000 w 0x0058 tc4 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0040 ? 0x006f tim0 (timer 16 bi t 4 channels) (s heet 2 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 33 0x0059 tc4 (lo) r bit 7654321bit 0 w 0x005a tc5 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x005b tc5 (lo) r bit 7654321bit 0 w 0x005c tc6 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x005d tc6 (lo) r bit 7654321bit 0 w 0x005e tc7 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x005f tc7 (lo) r bit 7654321bit 0 w 0x0060 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x0061 paflg r000000 paov f pa i f w 0x0062 pacnt (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0063 pacnt (lo) r bit 7654321bit 0 w 0x0064 reserved r00000000 w 0x0065 reserved r00000000 w 0x0066 reserved r00000000 w 0x0067 reserved r00000000 w 0x0068 reserved r00000000 w 0x0069 reserved r00000000 w 0x006a reserved r00000000 w 0x006b reserved r00000000 w 0x0040 ? 0x006f tim0 (timer 16 bi t 4 channels) (s heet 3 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 34 freescale semiconductor 0x006c reserved r00000000 w 0x006d reserved r00000000 w 0x006e reserved r00000000 w 0x006f reserved r00000000 w 0x0070 ? 0x007f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0070? 0x007f reserved r00000000 w 0x0080 ? 0x00af atd (analog to digital converter 10 bit 16 channel) (sheet 1 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0080 atdctl0 r0000 wrap3 1 wrap2 1 wrap1 1 wrap0 1 w 0x0081 atdctl1 r etrigsel 2 000 etrigch3 2 etrigch2 2 etrigch1 2 etrigch0 2 w 0x0082 atdctl2 r adpu affc awai etrigl e etrigp etrig ascie ascif w 0x0083 atdctl3 r0 s8c s4c s2c s1c fifo frz1 frz0 w 0x0084 atdctl4 r sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 w 0x0085 atdctl5 r djm dsgn scan mult 0 cc cb ca w 0x0086 atdstat0 r scf 0 etorf fifor 0 cc2 cc1 cc0 w 0x0087 reserved r00000000 w 0x0088 atdtest0 r00000000 w 0x0089 atdtest1 r0000000 sc w 0x008a atdstat0 r ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 w 0x0040 ? 0x006f tim0 (timer 16 bi t 4 channels) (s heet 4 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 35 0x008b atdstat1 r ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 w 0x008c atddien0 r ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 w 0x008d atddien1 r ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 w 0x008e portad0 r ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 w 0x008f portad1 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w 0x0090 atddr0h r bit15 14 13 12 11 10 9 bit8 w 0x0091 atddr0l rbit7bit6000000 w 0x0092 atddr1h r bit15 14 13 12 11 10 9 bit8 w 0x0093 atddr1l rbit7bit6000000 w 0x0094 atddr2h r bit15 14 13 12 11 10 9 bit8 w 0x0095 atddr2l rbit7bit6000000 w 0x0096 atddr3h r bit15 14 13 12 11 10 9 bit8 w 0x0097 atddr3l rbit7bit6000000 w 0x0098 atddr4h r bit15 14 13 12 11 10 9 bit8 w 0x0099 atddr4l rbit7bit6000000 w 0x009a atddr5h r bit15 14 13 12 11 10 9 bit8 w 0x009b atddr5l rbit7bit6000000 w 0x009c atddr6h r bit15 14 13 12 11 10 9 bit8 w 0x009d atddr6l rbit7bit6000000 w 0x0080 ? 0x00af atd (analog to digital converter 10 bit 16 channel) (sheet 2 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 36 freescale semiconductor 0x009e atddr7h r bit15 14 13 12 11 10 9 bit8 w 0x009f atddr7l rbit7bit6000000 w 0x00a0 atddr8h r bit15 14 13 12 11 10 9 bit8 w 0x00a1 atddr8l rbit7bit6000000 w 0x00a2 atddr9h r bit15 14 13 12 11 10 9 bit8 w 0x00a3 atddr9l rbit7bit6000000 w 0x00a4 atddr10h r bit15 14 13 12 11 10 9 bit8 w 0x00a5 atddr10l rbit7bit6000000 w 0x00a6 atddr11h r bit15 14 13 12 11 10 9 bit8 w 0x00a7 atddr11l rbit7bit6000000 w 0x00a8 atddr12h r bit15 14 13 12 11 10 9 bit8 w 0x00a9 atddr12l rbit7bit6000000 w 0x00aa atddr13h r bit15 14 13 12 11 10 9 bit8 w 0x00ab atddr13l rbit7bit6000000 w 0x00ac atddr14h r bit15 14 13 12 11 10 9 bit8 w 0x00ad atddr14l rbit7bit6000000 w 0x00ae atddr15h r bit15 14 13 12 11 10 9 bit8 w 0x00af atddr15l rbit7bit6000000 w 1 wrap0?3 bits are available in version v04 of atd10b16c 2 etrigsel and etrigch0?3 bits are available in version v04 of atd10b16c 0x0080 ? 0x00af atd (analog to digital converter 10 bit 16 channel) (sheet 3 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 37 0x00b0 ? 0x00c7 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00b0? 0x00c7 reserved r00000000 w 0x00c8 ? 0x00cf sci0 (asynchr onous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00c8 scibdh r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00c9 scibdl r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00ca scicr1 r loops sciswai rsrc m wake ilt pe pt w 0x00cb scicr2 r tie tcie rie ilie te re rwu sbk w 0x00cc scisr1 r tdre tc rdrf idle or nf fe pf w 0x00cd scisr2 r0 0 0 txpol 1 1 txpol and rxpol bits are available in version v04 of sci rxpol 1 brk13 txdir raf w 0x00ce scidrh rr8 t8 000000 w 0x00cf scidrl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 0x00d0 ? 0x00d7 sci1 (asynchr onous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d0 scibdh r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00d1 scibdl r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00d2 scicr1 r loops sciswai rsrc m wake ilt pe pt w 0x00d3 scicr2 r tie tcie rie ilie te re rwu sbk w 0x00d4 scisr1 r tdre tc rdrf idle or nf fe pf w chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 38 freescale semiconductor 0x00d5 scisr2 r0 0 0 txpol 1 rxpol 1 brk13 txdir raf w 0x00d6 scidrh rr8 t8 000000 w 0x00d7 scidrl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 1 txpol and rxpol are available in version v04 of sci 0x00d8 ? 0x00df spi (seria l peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d8 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x00d9 spicr2 r0 0 0 modfen bidiroe 0 spiswai spc0 w 0x00da spibr r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x00db spisr rspif0sptefmodf0000 w 0x00dc reserved r00000000 w 0x00dd spidr r bit7654321bit0 w 0x00de reserved r00000000 w 0x00df reserved r00000000 w 0x00e0 ? 0x00e7 iic (inter-ic bus) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e0 ibad r adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 w 0x00e1 ibfd r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w 0x00e2 ibcr r iben ibie ms/sl tx/rx txak 00 ibswai wrsta 0x00e3 ibsr r tcf iaas ibb ibal 0srw ibif rxak w 0x00d0 ? 0x00d7 sci1 (a synchronous serial interface) (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 39 0x00e4 ibdr r d7 d6 d5 d4 d3 d2 d1 d0 w 0x00e5 reserved r00000000 w 0x00e6 reserved r00000000 w 0x00e7 reserved r00000000 w 0x00e8 ? 0x00ef sci2 (asynchr onous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e8 scibdh r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00e9 scibdl r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00ea scicr1 r loops sciswai rsrc m wake ilt pe pt w 0x00eb scicr2 r tie tcie rie ilie te re rwu sbk w 0x00ec scisr1 r tdre tc rdrf idle or nf fe pf w 0x00ed scisr2 r0 0 0 txpol 1 1 txpol and rxpol are available in version v04 of sci rxpol 1 brk13 txdir raf w 0x00ee scidrh rr8 t8 000000 w 0x00ef scidrl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 0x00e0 ? 0x00e7 iic (int er-ic bus) (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 40 freescale semiconductor 0x00f0 ? 0x00f3 dac0 (digit al-to-analog converter) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00f0 dacc0 r dace dacte 0 0 djm dsgn dacwai dacoe w 0x00f1 dacc1 r00000000 w 0x00f2 dacd r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 w 0x00f3 dacd r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 w 0x00f4 ? 0x00f7 dac1 (digit al-to-analog converter) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00f4 dacc0 r dace dacte 0 0 djm dsgn dacwai dacoe w 0x00f5 dacc1 r00000000 w 0x00f6 dacd r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 w 0x00f7 dacd r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 w 0x00f8 ? 0x00ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00f8? 0x00ff reserved r00000000 w 0x0100 ? 0x010f flash co ntrol register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0100 fclkdiv rfdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0101 fsec r keyen1 nv6 nv5 nv4 nv3 nv2 sec1 sec0 w 0x0102 reserved for factory test r00000000 w 0x0103 fcnfg r cbeie ccie keyacc 00000 w 0x0104 fprot r fpopen nv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 41 0x0105 fstat r cbeif ccif pviol accerr 0 blank 00 w 0x0106 fcmd r0 cmdb6 cmdb5 00 cmdb2 0 cmdb0 w 0x0107 reserved for factory test r00000000 w 0x0108 reserved for factory test r00000000 w 0x0109 reserved for factory test r00000000 w 0x010a reserved for factory test r00000000 w 0x010b reserved for factory test r00000000 w 0x010c reserved r00000000 w 0x010d reserved r00000000 w 0x010e reserved r00000000 w 0x010f reserved r00000000 w 0x0110 ? 0x013f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0110? 0x013f reserved r00000000 w 0x0140 ? 0x016f tim1 (timer 16 bi t 4 channels) (s heet 1 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0140 tios r ios7 ios6 ios5 ios4 0000 w 0x0141 cforc r00000000 wfoc7foc6foc5foc4 0x0142 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 0000 w 0x0143 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 0000 w 0x0100 ? 0x010f flash control register (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 42 freescale semiconductor 0x0144 tcnt (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0145 tcnt (lo) rbit 7654321bit 0 w 0x0146 tscr1 r ten tswai tsfrz tffca 0000 w 0x0147 ttov r tov7 tov6 tov5 tov4 0000 w 0x0148 tctl1 r om7ol7om6ol6om5ol5om4ol4 w 0x0149 reserved r00000000 w 0x014a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x014b reserved r00000000 w 0x014c tie r c7i c6i c5i c4i 0000 w 0x014d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x014e tflg1 r c7f c6f c5f c4f 0000 w 0x014f tflg2 r tof 0000000 w 0x0150 reserved r00000000 w 0x0151 reserved r00000000 w 0x0152 reserved r00000000 w 0x0153 reserved r00000000 w 0x0154 reserved r00000000 w 0x0155 reserved r00000000 w 0x0156 reserved r00000000 w 0x0140 ? 0x016f tim1 (timer 16 bi t 4 channels) (s heet 2 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 43 0x0157 reserved r00000000 w 0x0158 tc4 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0159 tc4 (lo) r bit 7654321bit 0 w 0x015a tc5 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x015b tc5 (lo) r bit 7654321bit 0 w 0x015c tc6 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x015d tc6 (lo) r bit 7654321bit 0 w 0x015e tc7 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x015f tc7 (lo) r bit 7654321bit 0 w 0x0160 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x0161 paflg r000000 paov f pa i f w 0x0162 pacnt (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0163 pacnt (lo) r bit 7654321bit 0 w 0x0164 reserved r00000000 w 0x0165 reserved r00000000 w 0x0166 reserved r00000000 w 0x0167 reserved r00000000 w 0x0168 reserved r00000000 w 0x0169 reserved r00000000 w 0x0140 ? 0x016f tim1 (timer 16 bi t 4 channels) (s heet 3 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 44 freescale semiconductor 0x016a reserved r00000000 w 0x016b reserved r00000000 w 0x016c reserved r00000000 w 0x016d reserved r00000000 w 0x016e reserved r00000000 w 0x016f reserved r00000000 w 0x0170 ? 0x017f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0110? 0x013f reserved r00000000 w 0x0180 ? 0x01af tim2 (timer 16 bi t 4 channels) (sheet 1 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0180 tios r ios7 ios6 ios5 ios4 0000 w 0x0181 cforc r00000000 wfoc7foc6foc5foc4 0x0182 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 0000 w 0x0183 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 0000 w 0x0184 tcnt (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0185 tcnt (lo) rbit 7654321bit 0 w 0x0186 tscr1 r ten tswai tsfrz tffca 0000 w 0x0187 ttov r tov7 tov6 tov5 tov4 0000 w 0x0188 tctl1 r om7ol7om6ol6om5ol5om4ol4 w 0x0140 ? 0x016f tim1 (timer 16 bi t 4 channels) (s heet 4 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 45 0x0189 reserved r00000000 w 0x018a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x018b reserved r00000000 w 0x018c tie r c7i c6i c5i c4i 0000 w 0x018d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x018e tflg1 r c7f c6f c5f c4f 0000 w 0x018f tflg2 r tof 0000000 w 0x0190 reserved r00000000 w 0x0191 reserved r00000000 w 0x0192 reserved r00000000 w 0x0193 reserved r00000000 w 0x0194 reserved r00000000 w 0x0195 reserved r00000000 w 0x0196 reserved r00000000 w 0x0197 reserved r00000000 w 0x0198 tc4 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0199 tc4 (lo) r bit 7654321bit 0 w 0x015a tc5 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x019b tc5 (lo) r bit 7654321bit 0 w 0x019c tc6 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0180 ? 0x01af tim2 (timer 16 bi t 4 channels) (sheet 2 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 46 freescale semiconductor 0x019d tc6 (lo) r bit 7654321bit 0 w 0x019e tc7 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x019f tc7 (lo) r bit 7654321bit 0 w 0x01a0 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x01a1 paflg r000000 paov f pa i f w 0x01a2 pacnt (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x01a3 pacnt (lo) r bit 7654321bit 0 w 0x01a4 reserved r00000000 w 0x01a5 reserved r00000000 w 0x01a6 reserved r00000000 w 0x01a7 reserved r00000000 w 0x01a8 reserved r00000000 w 0x01a9 reserved r00000000 w 0x01aa reserved r00000000 w 0x01ab reserved r00000000 w 0x01ac reserved r00000000 w 0x01ad reserved r00000000 w 0x01ae reserved r00000000 w 0x01af reserved r00000000 w 0x0180 ? 0x01af tim2 (timer 16 bi t 4 channels) (sheet 3 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 47 0x01b0 ? 0x01df reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01b0? 0x01df reserved r00000000 w 0x01e0 ? 0x01ff pwm (pulse width modulator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01e0 pwme r0 0 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w 0x01e1 pwmpol r0 0 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w 0x01e2 pwmclk r0 0 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w 0x01e3 pwmprclk r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w 0x01e4 pwmcae r0 0 cae5 cae4 cae3 cae2 cae1 cae0 w 0x01e5 pwmctl r0 con45 con23 con01 pswai pfrz 00 w 0x01e6 pwmtst te s t o n l y r00000000 w 0x01e7 pwmprsc r00000000 w 0x01e8 pwmscla r bit 7 6 5 4 3 2 1 bit 0 w 0x01e9 pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w 0x01ea pwmscnta r00000000 w 0x01eb pwmscntb r00000000 w 0x01ec pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x01ed pwmcnt1 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x01ee pwmcnt2 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x01ef pwmcnt3 r bit 7 6 5 4 3 2 1 bit 0 w00000000 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 48 freescale semiconductor 0x01f0 pwmcnt4 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x01f1 pwmcnt5 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x01f2 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w 0x01f3 pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w 0x01f4 pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w 0x01f5 pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w 0x01f6 pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w 0x01f7 pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w 0x01f8 pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w 0x01f9 pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 w 0x01fa pwmdty2 r bit 7 6 5 4 3 2 1 bit 0 w 0x01fb pwmdty3 r bit 7 6 5 4 3 2 1 bit 0 w 0x01fc pwmdty4 r bit 7 6 5 4 3 2 1 bit 0 w 0x01fd pwmdty5 r bit 7 6 5 4 3 2 1 bit 0 w 0x01fe pwmsdn r pwmif pwmie 0 pwmlvl 0pwm5in pwm5inl pwm5ena w pwmrstrt 0x01ff reserved r00000000 w 0x01e0 ? 0x01ff pwm (pul se width modulator) (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 49 0x0200 ? 0x023f pmf (p ulse width m odulator with f ault protection) (sheet 1 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0200 pmfcfg0 r wp mtg edgec edgeb edgea indepc indepb indepa w 0x0201 pmfcfg1 r enha 0 botnegc topnegc botnegb topnegb botnega topnega w 0x0202 pmfcfg2 r0 0 msk5 msk4 msk3 msk2 msk1 msk0 w 0x0203 pmfcfg3 r pmfwai pmffrz 0 vlmode swapc swapb swapa w 0x0204 pmffctl r fmode3 fie3 fmode2 fie2 fmode1 fie1 fmode0 fie0 w 0x0205 pmffpin r0 fpine3 0 fpine2 0 fpine1 0 fpine0 w 0x0206 pmffsta r0 fflag3 0 fflag2 0 fflag1 0 fflag0 w 0x0207 pmfqsmp r qsmp3 qsmp2 qsmp1 qsmp0 w 0x0208 pmfdmpa r dmp13 dmp12 dmp11 dmp10 dmp03 dmp02 dmp01 dmp00 w 0x0209 pmfdmpb r dmp33 dmp32 dmp31 dmp30 dmp23 dmp22 dmp21 dmp20 w 0x020a pmfdmpc r dmp53 dmp52 dmp51 dmp50 dmp43 dmp42 dmp41 dmp40 w 0x020b reserved r00000000 w 0x020c pmfoutc r0 0 outctl5 outctl4 outctl3 outctl2 outctl1 outctl0 w 0x020d pmfoutb r0 0 out5 out4 out3 out2 out1 out0 w 0x020e pmfdtms r 0 0 dt5 dt4 dt3 dt2 dt1 dt0 w 0x020f pmfcctl r0 0 isens 0 ipolc ipolb ipola w 0x0210 pmfval0 r bit 15 14 13 12 11 10 9 bit 8 w 0x0211 pmfval0 r bit 7654321bit 0 w 0x0212 pmfval1 r bit 15 14 13 12 11 10 9 bit 8 w chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 50 freescale semiconductor 0x0213 pmfval1 r bit 7654321bit 0 w 0x0214 pmfval2 r bit 15 14 13 12 11 10 9 bit 8 w 0x0215 pmfval2 r bit 7654321bit 0 w 0x0216 pmfval3 r bit 15 14 13 12 11 10 9 bit 8 w 0x0217 pmfval3 r bit 7654321bit 0 w 0x0218 pmfval4 r bit 15 14 13 12 11 10 9 bit 8 w 0x0219 pmfval4 r bit 7654321bit 0 w 0x021a pmfval5 r bit 15 14 13 12 11 10 9 bit 8 w 0x021b pmfval5 r bit 7654321bit 0 w 0x021c reserved r00000000 w 0x021d reserved r00000000 w 0x021e reserved r00000000 w 0x021f reserved r00000000 w 0x0220 pmfenca r pwmena 00000 ldoka pwmriea w 0x0221 pmffqca r ldfqa halfa prsca pwmrfa w 0x0222 pmfcnta r0 bit 14 13 12 11 10 9 bit 8 w 0x0223 pmfcnta r bit 7654321bit 0 w 0x0224 pmfmoda r0 bit 14 13 12 11 10 9 bit 8 w 0x0225 pmfmoda r bit 7654321bit 0 w 0x0200 ? 0x023f pmf (p ulse width m odulator with f ault protection) (sheet 2 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 51 0x0226 pmfdtma r0000 bit 11 10 9 bit 8 w 0x0227 pmfdtma r bit 7654321bit 0 w 0x0228 pmfencb r pwmenb 00000 ldokb pwmrieb w 0x0229 pmffqcb r ldfqb halfb prscb pwmrfb w 0x022a pmfcntb r0 bit 14 13 12 11 10 9 bit 8 w 0x022b pmfcntb r bit 7654321bit 0 w 0x022c pmfmodb r0 bit 14 13 12 11 10 9 bit 8 w 0x022d pmfmodb r bit 7654321bit 0 w 0x022e pmfdtmb r0000 bit 11 10 9 bit 8 w 0x022f pmfdtmb r bit 7654321bit 0 w 0x0230 pmfencc r pwmenc 00000 ldokc pwmriec w 0x0231 pmffqcc r ldfqc halfc prscc pwmrfc w 0x0232 pmfcntc r0 bit 14 13 12 11 10 9 bit 8 w 0x0233 pmfcntc r bit 7654321bit 0 w 0x0234 pmfmodc r0 bit 14 13 12 11 10 9 bit 8 w 0x0235 pmfmodc r bit 7654321bit 0 w 0x0236 pmfdtmc r0000 bit 11 10 9 bit 8 w 0x0237 pmfdtmc r bit 7654321bit 0 w 0x0238 reserved r00000000 w 0x0200 ? 0x023f pmf (p ulse width m odulator with f ault protection) (sheet 3 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 52 freescale semiconductor 0x0239 reserved r00000000 w 0x023a reserved r00000000 w 0x023b reserved r00000000 w 0x023c reserved r00000000 w 0x023d reserved r00000000 w 0x023e reserved r00000000 w 0x023f reserved r00000000 w 0x0240 ? 0x027f pim (port interf ace module) (sheet 1 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0240 ptt r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w 0x0241 ptit r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w 0x0242 ddrt r ddrt7 ddrt7 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w 0x0243 rdrt r rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 w 0x0244 pert r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w 0x0245 ppst r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w 0x0246 reserved r00000000 w 0x0247 reserved r00000000 w 0x0248 pts r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w 0x0249 ptis r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w 0x0200 ? 0x023f pmf (p ulse width m odulator with f ault protection) (sheet 4 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 53 0x024a ddrs r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w 0x024b rdrs r rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 w 0x024c pers r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w 0x024d ppss r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w 0x024e woms r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w 0x024f reserved r00000000 w 0x0250 ptm r ptm7 ptm6 ptm5 ptm4 ptm3 0 ptm1 ptm0 w 0x0251 ptim r ptim7 ptim6 ptim5 ptim4 ptim3 0 ptim1 ptim0 w 0x0252 ddrm r ddrm7 ddrm6 ddrm5 ddrm4 ddrm3 0 ddrm1 ddrm0 w 0x0253 rdrm r rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 0 rdrm1 rdrm0 w 0x0254 perm r perm7 perm6 perm5 perm4 perm3 0 perm1 perm0 w 0x0255 ppsm r ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 0 ppsm1 ppsm0 w 0x0256 womm r womm7 womm6 womm5 womm4 0000 w 0x0257 reserved r00000000 w 0x0258 ptp r0 0 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w 0x0259 ptip r 0 0 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w 0x025a ddrp r0 0 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w 0x025b rdrp r0 0 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 w 0x025c perp r0 0 perp5 perp4 perp3 perp2 perp1 perp0 w 0x0240 ? 0x027f pim (port interf ace module) (sheet 2 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 54 freescale semiconductor 0x025d ppsp r0 0 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppsp0 w 0x025e reserved r00000000 w 0x025f reserved r00000000 w 0x0260 ptq r0 ptq6 ptq5 ptq4 ptq3 ptq2 ptq1 ptq0 w 0x0261 ptiq r 0 ptiq6 ptiq5 ptiq4 ptiq3 ptiq2 ptiq1 ptiq0 w 0x0262 ddrq r0 ddrq6 ddrq5 ddrq4 ddrq3 ddrq2 ddrq1 ddrq0 w 0x0263 rdrq r0 rdrq6 rdrq5 rdrq4 rdrq3 rdrq2 rdrq1 rdrq0 w 0x0264 perq r0 perq6 perq5 perq4 perq3 perq2 perq1 perq0 w 0x0265 ppsq r0 ppsq6 ppsq5 ppsq4 ppsq3 ppsq2 ppsq1 ppsq0 w 0x0266 reserved r00000000 w 0x0267 reserved r00000000 w 0x0268 ptu r ptu7 ptu6 ptu5 ptu4 ptu3 ptu2 ptu1 ptu0 w 0x0269 ptiu r ptiu7 ptiu6 ptiu5 ptiu4 ptiu3 ptiu2 ptiu1 ptiu0 w 0x026a ddru r ddru7 ddru6 ddru5 ddru4 ddru3 ddru2 ddru1 ddru0 w 0x026b rdru r rdru7 rdru6 rdru5 rdru4 rdru3 rdru2 rdru1 rdru0 w 0x026c peru r peru7 peru6 peru5 peru4 peru3 peru2 peru1 peru0 w 0x026d ppsu r ppsu7 ppsu6 ppsu5 ppsu4 ppsu3 ppsu2 ppsu1 ppsu0 w 0x026e modrr r0000 modrr3 modrr2 modrr1 modrr0 w 0x026f reserved r00000000 w 0x0240 ? 0x027f pim (port interf ace module) (sheet 3 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 55 0x0270 ptad(h) r ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 w 0x0271 ptad(l) r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w 0x0272 ptiad(h) r ptiad15 ptiad14 ptiad13 ptiad1 2 ptiad11 ptiad10 ptiad9 ptiad8 w 0x0273 ptiad(l) r ptiad7 ptiad6 ptiad5 ptiad4 p tiad3 ptiad2 ptiad1 ptiad0 w 0x0274 ddrad(h) r ddrad15 ddrad14 ddrad13 ddrad12 ddrad11 ddrad10 ddrad9 ddrad8 w 0x0275 ddrad(l) r ddrad7 ddrad6 ddrad5 ddrad4 ddrad3 ddrad2 ddrad1 ddrad0 w 0x0276 rdrad(h) r rdrad15 rdrad14 rdrad13 rdrad12 rdrad11 rdrad10 rdrad9 rdrad8 w 0x0277 rdrad(l) r rdrad7 rdrad6 rdrad5 rdrad4 rdrad3 rdrad2 rdrad1 rdrad0 w 0x0278 perad(h) r perad15 perad14 perad13 perad12 perad11 perad10 perad9 perad8 w 0x0279 perad(l) r perad7 perad6 perad5 perad4 perad3 perad2 perad1 perad0 w 0x027a ppsad(h) r ppsad15 ppsad14 ppsad13 ppsad12 ppsad11 ppsad10 ppsad9 ppsad8 w 0x027b ppsad(l) r ppsad7 ppsad6 ppsad5 ppsad4 ppsad3 ppsad2 ppsad1 ppsad0 w 0x027c piead(h) r piead15 piead14 piead13 piead12 piead11 piead10 piead9 piead8 w 0x027d piead(l) r piead7 piead6 piead5 piead4 p iead3 piead2 piead1 piead0 w 0x027e pifad(h) r pifad15 pifad14 pifad13 pifad12 pifad11 pifad10 pifad9 pifad8 w 0x027f pifad(l) r pifad7 pifad6 pifad5 pifad4 pifad3 pifad2 pifad1 pifad0 w 0x0280 ? 0x03ff r eserved space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0280? 0x2ff reserved r00000000 w 0x0300? 0x03ff unimpl emented r00000000 w 0x0240 ? 0x027f pim (port interf ace module) (sheet 4 of 4) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 56 freescale semiconductor 1.2.2 part id assignments the part id is located in two 8-bit registers partidh and partid l (addresses 0x001a and 0x001b after reset. the read-only value is a unique part id for each re vision of the chip. table 1-2 shows the assigned part id numbers. the device memory sizes are lo cated in two 8-bit registers me msiz0 and memsiz1 (addresses 0x001c and 0x001d after reset). table 1-3 shows the read-only values of these registers. refer to chapter 19, ?module mapping control (mmcv4)? for further details. table 1-2. assigned part id numbers device mask set number part id 1 1 the coding is as follows: bit 15?12: major family identifier bit 11?8: minor family identifier bit 7?4: major mask set revision number including fab transfers bit 3?0: minor ? non full ? mask set revision mc9s12e256 0l43x 0x5000 table 1-3. memory size registers device register name value mc9s12e256 memsiz0 0x07 mc9s12e256 memsiz1 0x81 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 57 1.3 signal description 1.3.1 device pinout figure 1-3. pin assignments for 112-lqfp vrh vdda pad07/an07/kwad07 pad06/an06/kwad06 pad05/an05/kwad05 pad04/an04/kwad04 pad03/an03/kwad03 pad02/an02/kwad02 pad01/an01/kwad01 pad00/an00/kwad00 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 vss2 vdd2 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 ps7/ss ps6/sck ps5/mosi ps4/miso ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 pp0/pw00 pp1/pw01 pp2/pw02 pp3/pw03 pp4/pw04 pp5/pw05 pk7/ecs /romctl pk6/xcs pk5/xaddr19 pk4/xaddr18 vdd1 vss1 pk3/xaddr17 pk2/xaddr16 pk1/xaddr15 pk0/xaddr14 pm1/da1 pm0/da0 pad15/an15/kwad15 pad14/an14/kwad14 pad13/an13/kwad13 pad12/an12/kwad12 pad11/an11/kwad11 pad10/an10/kwad10 pad09/an09/kwad09 pad08/an08/kwad08 vssa vrl pm3 rxd2/pm4 txd2/pm5 sda/pm6 scl/pm7 fault0/pq0 fault1/pq1 fault2/pq2 fault3/pq3 addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 vddx vssx addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 is0 /pq4 is1 /pq5 is2 /pq6 modc/taghi/ bkgd ioc04/pt0 ioc05/pt1 ioc06/pt2 ioc07/pt3 ioc14/pt4 ioc15/pt5 ioc16/pt6 ioc17/pt7 pw10/ioc24/pu0 pw11/ioc25/pu1 pw14/pu4 pw15/pu5 xclks /noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test pu6 pu7 pw12/ioc26/pu2 pw13/ioc27pu3 lstrb /taglo /pe3 r/w /pe2 irq /pe1 xirq /pe0 signals shown in bold are not available on the 80-pin package mc9s12e256 112 lqfp 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 58 freescale semiconductor figure 1-4. pin assignments for 80-qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 mc9s12e256 80 qfp vrh vdda pad07/an07/kwad07 pad06/an06/kwad06 pad05/an05/kwad05 pad04/an04/kwad04 pad03/an03/kwad03 pad02/an02/kwad02 pad01/an01/kwad01 pad00/an00/kwad00 vss2 vdd2 ps7/ss ps6/sck ps5/mosi ps4/miso ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 pp0/pw00 pp1/pw01 pp2/pw02 pp3/pw03 pp4/pw04 pp5/pw05 vdd1 vss1 pm1/da1 pm0/da0 pad15/an15/kwad15 pad14/an14/kwad14 pad13/an13/kwad13 pad12/an12/kwad12 pad11/an11/kwad11 pad10/an10/kwad10 pad09/an09/kwad09 pad08/an08/kwad08 vssa vrl pm3 rxd2/pm4 txd2/pm5 sda/pm6 scl/pm7 fault0/pq0 fault1/pq1 fault2/pq2 fault3/pq3 vddx vssx is0 /pq4 is1 /pq5 is2 /pq6 modc/taghi/ bkgd ioc04/pt0 ioc05/pt1 ioc06/pt2 ioc07/pt3 ioc14/pt4 ioc15/pt5 ioc16/pt6 ioc17/pt7 pw10/ioc24/pu0 pw11/ioc25/pu1 xclks /noacc/pe7 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test pw12/ioc26/pu2 pw13/ioc27/pu3 irq /pe1 xirq /pe0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 59 1.3.2 signal properties summary table 1-4. signal properties pin name function 1 pin name function 2 pin name function 3 power domain internal pull resistor description ctrl reset state extal ? ? vddpll na na oscillator pins xtal ? ? vddpll na na xfc ? ? vddpll na na pll loop filter pin reset ? ? vddx none none external reset pin bkgd modc taghi vddx up up background debug, mode pin, tag signal high test vpp ? na na na test pin only pad[15,13, 12,8,6,4,2,0] an[15,13, 12,8,6,4,2,0] kwad[15,13, 12,8,6,4,2,0] vddx perad/ ppsad disabled port ad i/o pins, atd inputs, keypad wake-up pad[14,11, 10,9,7,5,3,1] an[14,11, 10,9,7,5,3,1] kwad[14,11, 10,9,7,5,3,1] vddx perad/ ppsad disabled port ad i/o pins, atd inputs, keypad wake-up pa[7:0] addr[15:8]/ data[15:8] ? vddx pucr disabled port a i/o pin, multiplexed address/data pb[7:0] addr[7:0]/ data[7:0] ? vddx pucr disabled port b i/o pin, multiplexed address/data pe7 noacc xclks vddx input input port e i/o pin, access, clock select pe6 ipipe1 modb vddx while reset is low: down port e i/o pin, pipe status, mode selection pe5 ipipe0 moda vddx while reset is low: down port e i/o pin, pipe status, mode selection pe4 eclk ? vddx pucr mode dep 1 port e i/o pin, bus clock output pe3 lstrb taglo vddx pucr mode dep 1 port e i/o pin, low strobe, tag signal low pe2 r/w ? vddx pucr mode dep 1 port e i/o pin, r/w in expanded modes pe1 irq ? vddx pucr up port e input, external interrupt pin pe0 xirq ? vddx pucr up port e input, non-maskable interrupt pin pk[7] ecs romctl vddx pucr up port k i/o pin, emulation chip select pk[6] xcs ? vddx pucr up port k i/o pin, external chip select pk[5:0] xaddr[19:14] ? vddx pucr up port k i/o pins, extended addresses pm7 scl ? vddx perm/ ppsm up port m i/o pin, iic scl signal pm6 sda ? vddx perm/ ppsm up port m i/o pin, iic sda signal pm5 txd2 ? vddx perm/ ppsm up port m i/o pin, sci2 transmit signal pm4 rxd2 ? vddx perm/ ppsm up port m i/o pin, sci2 receive signal pm3 ? ? vddx perm/ ppsm disabled port m i/o pin pm1 dao1 ? vddx perm/ ppsm disabled port m i/o pin, dac1 output chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 60 freescale semiconductor note signals shown in bold are not available in the 112-pin package. signals shown in italic are not available in the 80-pin package. if the port pins are not bonded out in the chosen package the user should in itialize the regist ers to be inputs with enabled pull resistance to avoid excess curren t consumption. this applie s to the following pins: (80qfp): port a[7:0], port b[7:0], port e[6,5,3,2], po rt k[7:0], port u[7:4] (64qfn): port u[3:0], port q[ 6:4], port m[3], port ad[14,11,10,9,7,5,3,1] pm0 dao0 ? vddx perm/ ppsm disabled port m i/o pin, dac0 output pp[5:0] pw0[5:0] ? vddx perp/ ppsp disabled port p i/o pins, pwm output pq[6:4] is [6:4] ? vddx perq/ ppsq disabled port q i/o pins, is [6:4] input pq[3:0] fault[3:0] ? vddx perq/ ppsq disabled port q i/o pins, fault[3:0] input ps7 ss ? vddx pers/ ppss up port s i/o pin, spi ss signal ps6 sck ? vddx pers/ ppss up port s i/o pin, spi sck signal ps5 mosi ? vddx pers/ ppss up port s i/o pin, spi mosi signal ps4 miso ? vddx pers/ ppss up port s i/o pin, spi miso signal ps3 txd1 ? vddx pers/ ppss up port s i/o pin, sci1 transmit signal ps2 rxd1 ? vddx pers/ ppss up port s i/o pin, sci1 receive signal ps1 txd0 ? vddx pers/ ppss up port s i/o pin, sci0 transmit signal ps0 rxd0 ? vddx pers/ ppss up port s i/o pin, sci0 receive signal pt[7:4] ioc1[7:4] ? vddx pert/ ppst disabled port t i/o pins, timer (tim1) pt[3:0] ioc0[7:4] ? vddx pert/ ppst disabled port t i/o pins, timer (tim0) pu[7:6] ? ? vddx peru/ ppsu disabled port u i/o pins pu[5:4] pw1[5:4] ? vddx peru/ ppsu disabled port u i/o pins, pwm outputs pu[3:0] ioc2[7:4] pw1[3:0] vddx peru/ ppsu disabled port u i/o pins, timer (tim2), pwm outputs 1 the port e output buffer enable signal control at reset is determined by the pear regist er and is mode dependent. for example, in special test mode rdwe = lstre = 1 which enable s the pe[3:2] output buffers and disables the pull-ups. refer to chapter 18, ?multiplexed external bus interface (mebiv3)? for pear register details. table 1-4. signal properties pin name function 1 pin name function 2 pin name function 3 power domain internal pull resistor description ctrl reset state chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 61 1.4 detailed signal descriptions 1.4.1 extal, xtal ? oscillator pins extal and xtal are the external clock and crystal driv er pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. 1.4.2 reset ? external reset pin reset is an active low bidirectional control signal that acts as an input to initialize the mcu to a known start-up state. it also acts as an open-drain output to indicate that an in ternal failure has been detected in either the clock monitor or cop watchdog circuit. ex ternal circuitry connected to the reset pin should not include a large capacitance that w ould interfere with the ability of this signal to rise to a valid logic one within 32 eclk cycles after the low drive is released. upon detection of any reset, an internal circuit drives the reset pin low and a clocked reset se quence controls when the mcu can begin normal processing. 1.4.3 test ? test pin the test pin is reserved for test and must be tied to vss in all applications. 1.4.4 xfc ? pll loop filter pin dedicated pin used to create the pll loop filter. see chapter 4, ?clocks and reset generator (crgv4)? for more detailed information. 1.4.5 bkgd / taghi / modc ? background debug, tag high & mode pin the bkgd / taghi / modc pin is used as a pseudo-op en-drain pin for the background debug communication. it is used as a mcu operating mode select pin during re set. the state of th is pin is latched to the modc bit at the rising e dge of reset. in mcu expanded modes of operation, when instruction tagging is on, an input low on this pin during the falling e dge of e-clock tags the hi gh half of the instruction word being read into the instruction queue . this pin always ha s an internal pull up. 1.4.6 pa[7:0] / addr[15:8] / data[15:8] ? port a i/o pins pa[7:0] are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external a ddress and data bus. pa[7:0] pins are not available in the 80 pin package version. 1.4.7 pb[7:0] / addr[7:0] / data[7:0] ? port b i/o pins pb[7:0] are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external a ddress and data bus. pb[7:0 ] pins are not available in the 80 pin package version. chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 62 freescale semiconductor 1.4.8 pe7 / noacc / xclks ? port e i/o pin 7 pe7 is a general purpose input or output pin. du ring mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the curr ent bus cycle is an unused or ?free cycle?. this signal will assert when the cpu is not using the bus. the xclks is an input signal which controls whether a crystal in combination with the internal colpitts (l ow power) oscillator is used or whether pierce oscillator/external clock circuitry is used. the state of this pin is la tched at the rising edge of reset . if the input is a logic low the extal pin is configured for an external cloc k drive or a pierce oscillator. if the input is a logic high a colpitts oscillator circuit is c onfigured on extal and xtal. since this pin is an input with a pull-up device during reset, if the pin is left floating, the de fault configuration is a colpitts oscillator circuit on extal and xtal. figure 1-5. colpitts oscillator connections (pe7 = 1) figure 1-6. pierce oscillator connections (pe7 = 0) 1.4.9 pe6 / modb / ipipe1 ? port e i/o pin 6 pe6 is a general purpose input or out put pin. it is used as a mcu operating mode se lect pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe1. this pin is an input with a pull-down device which is only active when reset is low. pe6 is not available in the 80 pin package version. mcu c2 extal xtal crystal or vsspll ceramic resonator c1 cdc 1 1. due to the nature of a translated ground colpitts oscillator a dc voltage bias is applied to the crystal. please contact the crystal manufacturer for crystal dc mcu extal xtal rs 1 rb vsspll crystal or ceramic resonator c2 c1 1. rs can be zero (shorted) when use with higher frequency crystals. refer to manufacturer?s data. chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 63 1.4.10 pe5 / moda / ipipe0 ? port e i/o pin 5 pe5 is a general purpose input or out put pin. it is used as a mcu operating mode se lect pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe0. this pin is an input with a pull-down device which is only active when reset is low. pe5 is not available in the 80-pin package version. 1.4.11 pe4 / eclk? port e i/o pin 4 / e-clock output pe4 is a general purpose input or output pin. in normal single chip mode pe4 is configured with an active pull-up while in reset and immediately out of reset. the pullup can be turned off by clearing pupee in the pucr register. in all modes except normal single chip mode, the pe4 pin is init ially configured as the output connection for the internal bus clock (eclk). eclk is used as a timing reference and to demultiplex the address and data in expanded modes. the eclk frequency is equal to 1/2 the crystal frequency out of reset. the eclk output function depends upon the settings of the neclk bit in the pear register, the ivis bit in the mode register and the estr bit in the ebictl register. all clocks, including the eclk, are halted when the mcu is in st op mode. it is possible to configure the mcu to interface to slow external memory. eclk can be st retched for such accesses. the pe4 pin is initially configured as eclk output with stretch in all expanded modes. reference the misc register (exstr[1:0] bits) for more information. in normal e xpanded narrow mode, the ec lk is available for use in external select decode logic or as a constant speed clock for use in the external application system. 1.4.12 pe3 / lstrb / taglo ? port e i/o pin 3 / low-byte strobe (lstrb ) pe3 can be used as a general-purpose i/o in all modes and is an input with an activ e pull-up out of reset. the pullup can be turned off by clearing pupee in th e pucr register. pe3 can also be configured as a low-byte strobe (lstrb ). the lstrb signal is used in write operations, so external low byte writes will not be possible until this function is enabled. lstrb can be enabled by setting the lstre bit in the pear register. in expanded wide and emulation narrow modes, and when bdm tagging is enabled, the lstrb function is multiplexed with the taglo function. when enabled a logic zero on the taglo pin at the falling edge of eclk will tag the lo w byte of an instruction word being read into the instruction queue. pe3 is not available in the 80 pin package version. 1.4.13 pe2 / r / w ? port e i/o pin 2 / read/write pe2 can be used as a gene ral-purpose i/o in all modes and is conf igured an input with an active pull-up out of reset. the pullup can be turned off by clear ing pupee in the pucr register. if the read/write function is required it should be enabled by setting the rdwe bit in the pear register. external writes will not be possible until the read/write function is enabled. the pe2 pin is not available in the 80 pin package version. 1.4.14 pe1 / irq ? port e input pin 1 / maskable interrupt pin pe1 is always an input and can always be read. the pe1 pin is also the irq input used fo r requesting an asynchronous interrupt to the mcu. du ring reset, the i bit in the conditi on code register (ccr) is set and any irq interrupt is masked until software en ables it by clearing the i bit. the irq is software chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 64 freescale semiconductor programmable to either falli ng edge-sensitive triggering or level-se nsitive triggering based on the setting of the irqe bit in the irqcr register. the irq is always enabled and conf igured to level-sensitive triggering out of reset. it can be disabled by clearing irqen bit in th e irqcr register. there is an active pull-up on this pin while in reset a nd immediately out of reset. the pul lup can be turned off by clearing pupee in the pucr register. 1.4.15 pe0 / xirq ? port e input pin 0 / non maskable interrupt pin pe0 is always an input and can always be read. the pe0 pin is also the xirq input for requesting a nonmaskable asynchronous interrupt to the mcu. during reset, the x bit in the condition code register (ccr) is set and any xirq interrupt is masked until mcu softwa re enables it by clearing the x bit. because the xirq input is level sensitive triggered, it can be connected to a multiple-source wired-or network. there is an active pull-up on this pin while in reset and immedi ately out of reset. the pullup can be turned off by clearing pu pee in the pucr register. 1.4.16 pk7 / ecs / romctl ? port k i/o pin 7 pk7 is a general purpose input or output pin. during mcu expanded modes of operation, when the emk bit in the mode register is set to 1, this pin is used as the emulati on chip select output (ecs ). in expanded modes the pk7 pin can be used to determine the rese t state of the romon bit in the misc register. at the rising edge of reset , the state of the pk7 pin is latched to the romon bit. there is an active pull-up on this pin while in reset and imme diately out of reset. the pullup can be turned off by clearing pupke in the pucr register. refer to chapter 18, ?multiplexed extern al bus interface (mebiv3)? for further details. pk7 is not available in the 80 pin package version. 1.4.17 pk6 / xcs ? port k i/o pin 6 pk6 is a general purpose input or output pin. during mcu expanded modes of operation, when the emk bit in the mode register is set to 1, this pin is used as an external chip select signal for most external accesses that are not select ed by ecs. there is an active pull-up on th is pin while in re set and immediately out of reset. the pullup can be turned off by clearing pupke in the pucr register. refer to chapter 18, ?multiplexed external bus interface (mebiv3)? for further details. pk6 is not available in the 80 pin package version. 1.4.18 pk[5:0] / xaddr[19:14] ? port k i/o pins [5:0] pk[5:0] are general purpose input or output pins. in mcu expanded modes of operation, when the emk bit in the mode register is set to 1, pk[5:0] provide the expanded a ddress xaddr[19:14] for the external bus. there are active pu ll-ups on pk[5:0] pins while in reset and immediately out of re set. the pullup can be turned off by clearing pupke in the pucr register. refer to chapter 18, ?multiplexed external bus interface (mebiv3)? for further details. pk[5:0] are not available in the 80 pin package version. chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 65 1.4.19 pad[15:0] / an[15:0] / kwad[15:0] ? port ad i/o pins [15:0] pad[15:0] are the analog inputs for the analog to digital convert er (adc). they can also be configured as general purpose digital input or output pin. when enabled as digita l inputs or outputs, the pad[15:0] can also be configured as keypad wa ke-up pins (kwu) and generate in terrupts causing the mcu to exit stop or wait mode. consult chapter 3, ?port integration module (pim9e256v1)? and the chapter 6, ?analog-to-digital converter (atd10b16cv4)? for information about pin configurations. 1.4.20 pm7 / scl ? port m i/o pin 7 pm7 is a general purpose input or output pin. when the iic module is enabled it b ecomes the serial clock line (scl) for the iic module (iic). while in reset a nd immediately out of reset the pm7 pin is configured as a high impedance input pin. consult chapter 3, ?port integrat ion module (pim9e256v1)? and chapter 10, ?inter-integ rated circuit (iicv2)? for information about pin configurations. 1.4.21 pm6 / sda ? port m i/o pin 6 pm6 is a general purpose i nput or output pin. when the iic module is enabled it becomes the serial data line (sdl) for the iic module (iic). while in reset and immediately out of reset the pm6 pin is configured as a high impedance input pin. consult chapter 3, ?port integrat ion module (pim9e256v1)? and chapter 10, ?inter-integ rated circuit (iicv2)? for information about pin configurations. 1.4.22 pm5 / txd2 ? port m i/o pin 5 pm5 is a general purpose input or output. when the se rial communications interf ace 2 (sci2) transmitter is enabled the pm5 pin is configured as the transmit pin txd2 of sc i2. while in reset and immediately out of reset the pm5 pin is configured as a high impedan ce input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 8, ?serial communication interface (sciv4)? for information about pin configurations. 1.4.23 pm4 / rxd2 ? port m i/o pin 4 pm4 is a general purpose input or output. when the serial communications interface 2 (sci2) receiver is enabled the pm4 pin is configured as the receive pin rxd2 of sci2. while in reset and immediately out of reset the pm4 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 8, ?serial communication interface (sciv4)? for information about pin configurations. 1.4.24 pm3 ? port m i/o pin 3 pm3 is a general purpose input or output pin. while in reset and immediately out of reset the pm3 pin is configured as a high impe dance input pin. consult chapter 3, ?port integration module (pim9e256v1)? for information about pin configurations. chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 66 freescale semiconductor 1.4.25 pm1 / dao1 ? port m i/o pin 1 pm1 is a general purpose input or output pin. when the digital to analog module 1 (dac1) is enabled the pm1 pin is configured as the analog output da01 of dac1. while in reset and immediately out of reset the pm1 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 7, ?digital-to-anal og converter (dac8b1cv1)? for information about pin configurations. 1.4.26 pm0 / dao2 ? port m i/o pin 0 pm0 is a general purpose input or output pin. when the digital to analog module 2 (dac2) is enabled the pm0 pin is configured as the analog output da02 of dac2. while in reset and immediately out of reset the pm0 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 7, ?digital-to-anal og converter (dac8b1cv1)? for information about pin configurations. 1.4.27 pp[5:0] / pw0[5:0] ? port p i/o pins [5:0] pp[5:0] are general purpose input or output pins. when the pulse widt h modulator with fault protection (pmf) is enabled the pp[5:0] output pi ns, as a whole or as pa irs, can be configured as pw0[5:0] outputs. while in reset and immediately out of reset the pp[5:0] pins are configur ed as a high impedance input pins. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 11, ?pulse width modulator with fault protection (pmf15b6cv2)? for information about pin configurations. 1.4.28 pq[6:4] / is[2:0] ? port q i/o pins [6:4] pq[6:4] are general purpose i nput or output pins. when enabled in the pulse wi dth modulator with fault protection module (pmf), the pq[6:4] pins become the current st atus input pins, is [2:0], for top/bottom pulse width correction. while in rese t and immediately out of reset pp[5: 0] pins are configured as a high impedance input pins. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 11, ?pulse width modulator with fault protection (pmf15b6cv2)? for information about pin configurations. 1.4.29 pq[3:0] / fault[3:0] ? port q i/o pins [3:0] pq[3:0] are general purpose i nput or output pins. when enabled in the pulse wi dth modulator with fault protection module (pmf), the pq[3:0] pins become th e fault protection inputs pins, fault[3:0], of the pmf. while in reset and immediately out of reset th e pq[3:0] pins are configured as a high impedance input pins. consult chapter 3, ?port integration module (pim9e256v1)? and the chapter 11, ?pulse width modulator with fault protection (pmf15b6cv2)? for information about pin configurations. 1.4.30 ps7 / ss ? port s i/o pin 7 ps7 is a general purpose input or output. when the serial peripheral interface (spi) is enabled ps7 becomes the slav e select pin ss . while in reset and immediately out of reset the ps7 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 9, ?serial peripheral interface (spiv3)? for information about pin configurations. chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 67 1.4.31 ps6 / sck ? port s i/o pin 6 ps6 is a general purpose input or output pin. when th e serial peripheral interface (spi) is enabled ps6 becomes the serial clock pin, sck. wh ile in reset and immedi ately out of reset the ps6 pin is configured as a high impedance input pin. consult chapter 3, ?port integrat ion module (pim9e256v1)? and chapter 9, ?serial peripheral interface (spiv3)? for information about pin configurations. 1.4.32 ps5 / mosi ? port s i/o pin 5 ps5 is a general purpose input or out put pin. when the serial peripheral interface (s pi) is enabled ps5 is the master output (during master mode) or slave input (during slav e mode) pin. while in reset and immediately out of rese t the ps5 pin is configured as a high impedance i nput pin consult chapter 3, ?port integration module (pim9e256v1)? and chapter 9, ?serial peripheral interface (spiv3)? for information about pin configurations. 1.4.33 ps4 / miso ? port s i/o pin 4 ps4 is a general purpose input or out put pin. when the serial peripheral interface (s pi) is enabled ps4 is the master input (during master mode) or slave output (during slav e mode) pin. while in reset and immediately out of reset the ps 4 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 9, ?serial peripheral interface (spiv3)? for information about pin configurations. 1.4.34 ps3 / txd1 ? port s i/o pin 3 ps3 is a general purpose input or ou tput. when the serial communications interface 1 (sci1) transmitter is enabled the ps3 pin is configured as the transmit pin, txd1, of sci1. while in reset and immediately out of reset the ps3 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 8, ?serial communication interface (sciv4)? for information about pin configurations. 1.4.35 ps2 / rxd1 ? port s i/o pin 2 ps2 is a general purpose input or output. when the serial communicati ons interface 1 (sci 1) receiver is enabled the ps2 pin is configured as the receive pi n rxd1 of sci1. while in reset and immediately out of reset the ps2 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 8, ?serial communication interface (sciv4)? for information about pin configurations. 1.4.36 ps1 / txd0 ? port s i/o pin 1 ps1 is a general purpose input or ou tput. when the serial communications interface 0 (sci0) transmitter is enabled the ps1 pin is configured as the transmit pin, txd0, of sci0. while in reset and immediately out of reset the ps1 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 8, ?serial communication interface (sciv4)? for information about pin configurations. chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 68 freescale semiconductor 1.4.37 ps0 / rxd0 ? port s i/o pin 0 ps0 is a general purpose input or output. when the serial communicati ons interface 0 (sci 0) receiver is enabled the ps0 pin is configured as the receive pi n rxd0 of sci0. while in reset and immediately out of reset the ps0 pin is configured as a high impedance input pin. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 8, ?serial communication interface (sciv4)? for information about pin configurations. 1.4.38 pt[7:4] / ioc1[7:4]? port t i/o pins [7:4] pt[7:4] are general purpose input or output pins. when the timer system 1 (tim1) is enabled they can also be configured as the tim1 input capture or output compare pins ioc1[7-4]. while in reset and immediately out of reset the pt[7:4] pins are c onfigured as a high impedan ce input pins. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 13, ?timer module (tim16b4cv1)? for information about pin configurations. 1.4.39 pt[3:0] / ioc0[7:4]? port t i/o pins [3:0] pt[3:0] are general purpose input or output pins. when the timer system 0 (tim0) is enabled they can also be configured as the tim0 input capture or output compare pins ioc0[7-4]. while in reset and immediately out of reset the pt[3:0] pins are c onfigured as a high impedan ce input pins. consult chapter 3, ?port integration module (pim9e256v1)? and chapter 13, ?timer module (tim16b4cv1)? for information about pin configurations. 1.4.40 pu[7:6] ? port u i/o pins [7:6] pu[7:6] are general purpose input or output pins. while in re set and immediately out of reset the pu[7:6] pins are configured as a high impedance input pins. consult chapter 3, ?port integration module (pim9e256v1)? for information about pin conf igurations. pu[7:6] are not av ailable in the 80 pin package version. 1.4.41 pu[5:4] / pw1[5:4] ? port u i/o pins [5:4] pu[5:4] are general purpose input or output pins. when the pulse widt h modulator (pwm) is enabled the pu[5:4] output pins, individually or as a pair, can be configured as pw 1[5:4] outputs. while in reset and immediately out of reset the pu[5:4] pins are c onfigured as a high impedance input pins. consult chapter 3, ?port integrat ion module (p im9e256v1)? and chapter 12, ?pulse-width modulator (pwm8b6cv1)? for information about pin conf igurations. pu[5:4] are not av ailable in the 80 pin package version. 1.4.42 pu[3:0] / ioc2[7:4]/pw1[3: 0] ? port u i/o pins [3:0] pu[3:0] are general purpose input or output pins. when the timer system 2 (tim2) is enabled they can also be configured as the tim2 input capture or output compare pins ioc2[7-4]. when the pulse width modulator (pwm) is enabled the pu[3:0] output pins, individually or as a pair, can be configured as pw1[3:0] outputs. the mod rr register in the port integration module determin es if the tim2 or pwm chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 69 function is selected. while in reset and immediately out of reset the pu[3 :0] pins are configured as a high impedance input pins. consult chapter 3, ?port integrat ion module (pim9e256v1)? , chapter 13, ?timer module (tim16b4cv1)? , and chapter 12, ?pulse-width modulator (pwm8b6cv1)? for information about pin configurations. 1.4.43 vddx,vssx ? power & ground pins for i/o drivers external power and ground for i/o dr ivers. bypass requirements depend on how heavily the mcu pins are loaded. 1.4.44 vddr, vssr ? power supply pi ns for i/o drivers & for internal voltage regulator external power and ground for i/o dr ivers and input to the internal vo ltage regulator. bypass requirements depend on how heavily the mcu pins are loaded. 1.4.45 vdd1, vdd2, vss1, vss2 ? powe r supply pins for internal logic power is supplied to the mcu through vdd and vss. this 2.5v supply is deri ved from the internal voltage regulator. there is no static load on those pins al lowed. the internal voltage regulator is turned off, if vddr is tied to ground. 1.4.46 vdda, vssa ? power supply pins for atd and vreg vdda, vssa are the power supply and ground input pi ns for the voltage regulator and the analog to digital converter. 1.4.47 vrh, vrl ? atd refe rence voltage input pins vrh and vrl are the reference voltage input pins for the analog to digital converter. 1.4.48 vddpll, vsspll ? power supply pins for pll provides operating voltage and ground for the oscillator and the phased-locked loop. this allows the supply voltage to the oscillator a nd pll to be bypassed independently. this 2.5v voltage is generated by the internal voltage regulator. chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 70 freescale semiconductor note all vss pins must be connected togeth er in the application. because fast signal transitions place high, short- duration current demands on the power supply, use bypass capacitors with hi gh-frequency characteristics and place them as close to the mcu as possi ble. bypass requirements depend on mcu pin load. table 1-5. mc9s12e256 power and ground connection summary mnemonic nominal voltag e description vdd1, vdd2 2.5 v internal power and ground generated by internal regulator. these also allow an external source to supply the core vdd/vss voltages and bypass the internal voltage regulator. vss1, vss2 0v vddr 3.3/5.0 v external power and ground, supply to internal voltage regulator. to disable voltage regulator attach v ddr to v ssr . vssr 0 v vddx 3.3/5.0 v external power and ground, supply to pin drivers. vssx 0 v vdda 3.3/5.0 v operating voltage and ground for the analog-to-digital converter, the reference for the internal voltage regulator and the digital-to-analog converters, allows the supply voltage to the a/d to be bypassed independently. vssa 0 v vrh 3.3/5.0 v reference voltage high for the atd converter, and dac. vrl 0 v reference voltage low for the atd converter. vddpll 2.5 v provides operating voltage and ground fo r the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. vsspll 0 v chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 71 1.5 system clock description the clock and reset generator provide s the internal clock signals for th e core and all peripheral modules. figure 1-7 shows the clock connections from the crg to all modules. consult chapter 4, ?clocks and reset generator (crgv4)? for details on clock generation. figure 1-7. clock connections table 1-6. clock selection based on pe7 pe7 = xclks description 1 colpitts oscillator selected 0 pierce oscillator/external clock selected crg bus clock core clock extal xtal oscillator clock hcs12 core pwm ram pim iic dac flash at d sci0, sci1, sci2 pmf spi bdm osc cpu mebi mmc int dbg tim0, tim1, tim2 vreg chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 72 freescale semiconductor 1.6 modes of operation 1.6.1 overview eight possible modes determine the operating confi guration of the mc9s12e 256. each mode has an associated default memory map and external bus configuration controlled by a further pin. three low power modes exist for the device. 1.6.2 chip configuration summary the operating mode out of reset is determined by th e states of the modc, mo db, and moda pins during reset. the modc, modb, and moda bits in the m ode register show the cu rrent operating mode and provide limited mode switching dur ing operation. the states of th e modc, modb, and moda pins are latched into these bits on the rising edge of the reset signal. the romc tl signal allows the setting of the romon bit in the misc regi ster thus controlling whether the internal flash is visible in the memory map. romon = 1 mean the flash is visible in the memory map. the state of the romctl pin is latched into the romon bit in the misc register on the rising edge of the reset signal. for further explanation on the modes refer to chapter 18, ?multiplexed external bus interface (mebiv3)? . table 1-7. mode selection bkgd = modc pe6 = modb pe5 = moda pk7 = romctl romon bit mode description 0 0 0 x 1 special single chip, bdm allowed and active. bdm is allowed in all other modes but a serial command is required to make bdm active. 00101emulation expanded narrow, bdm allowed 10 0 1 0 x 0 special test (expanded wide), bdm allowed 01101emulation expanded wide, bdm allowed 10 1 0 0 x 1 normal single chip, bdm allowed 10100normal expanded narrow, bdm allowed 11 1 1 0 x 1 peripheral; bdm allowed but bus operations would cause bus conflicts (must not be used) 11100normal expanded wide, bdm allowed 11 table 1-8. clock selection based on pe7 pe7 = xclks description 1 colpitts oscillator selected 0 pierce oscillator/external clock selected chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 73 1.7 security the device will make avai lable a security feature preventing the unauthorized read and write of the memory contents. this feature allows: ? protection of the contents of flash, ? operation in single-chip mode, ? operation from external memory with internal flash disabled. the user must be reminded that part of the security must lie with the user?s code. an extreme example would be user?s code that dumps th e contents of the internal program. this code would defeat the purpose of security. at the same time the us er may also wish to put a back door in the user?s program. an example of this is the user downloads a key through the sc i which allows access to a programming routine that updates parameters. 1.7.1 securing the microcontroller once the user has programmed the flash, the part can be secured by program ming the security bits located in the flash module. these non-volatile bits will ke ep the part secured th rough resetting the part and through powering down the part. the security byte resides in a portion of the flash array. check chapter 2, ?256 kbyte flash module (fts256k2v1)? for more details on the security configuration. 1.7.2 operation of the secured microcontroller 1.7.2.1 normal single chip mode this will be the most common usage of the secured part. ever ything will appear the same as if the part was not secured with the exception of bdm ope ration. the bdm operatio n will be blocked. 1.7.2.2 executing from external memory the user may wish to execute from external space wi th a secured microcontroller. this is accomplished by resetting directly into expanded mode. the internal flash will be disabled. bdm operations will be blocked. 1.7.3 unsecuring the microcontroller in order to unsecure the microcontro ller, the internal flash must be erased. this can be done through an external program in expanded mode. once the user has erased the flash, the part can be reset into special single chip mode. this invokes a program that verifies the erasure of the internal flas h. once this program completes, the user can erase and program the flash security bits to the unsecured state. this is generally done through the bdm, but the user could also change to expa nded mode (by writing the mode bits through the bdm) and jumping to chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 74 freescale semiconductor an external program (again through bdm commands). no te that if the part goes through a reset before the security bits are reprogramme d to the unsecure state, the part will be secured again. 1.8 low power modes the microcontroller features three main low power modes. consult the respec tive block description chapter for information on the module behavior in st op, pseudo stop, and wait mode. an important source of information about the clock system is chapter 4, ?clocks and reset generator (crgv4)? . 1.8.1 stop executing the cpu stop instruction st ops all clocks and the oscillator t hus putting the chip in fully static mode. wake up from this mode can be done via reset or external interrupts. 1.8.2 pseudo stop this mode is entered by executing the cpu stop instru ction. in this mode the os cillator is still running and the real time interrupt (rti) or watchdog (cop) sub module can stay active. other peripherals are turned off. this mode consumes more current than the full stop mode, but the wake up time from this mode is signif icantly shorter. 1.8.3 wait this mode is entered by executing the cpu wai inst ruction. in this mode th e cpu will not execute instructions. the internal cpu signals (address and data bus) will be fully static. all peripherals stay active. for further power consumpt ion the peripherals can individuall y turn off their local clocks. 1.8.4 run although this is not a low power mode, unused periphera l modules should not be en abled in order to save power. 1.9 resets and interrupts consult the exception processing section of the cpu 12 reference manual for information on resets and interrupts. system resets can be genera ted through external control of the reset pin, through the clock and reset generator module crg or through the low volta ge reset (lvr) generator of the voltage regulator module. refer to chapter 4, ?clocks and reset generator (crgv4)? and chapter 14, ?dual output voltage regulator (vreg3v3v2)? for detailed information on reset generation. 1.9.1 vectors table 1-9 lists interrupt sources and vector s in default order of priority. chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 75 table 1-9. interrupt vector locations vector address interrupt source ccr mask local enable hprio value to elevate 0xfffe, 0xffff external reset, power on reset or low voltage reset (see section 4.3.2.4, ?crg flags register (crgflg)? to determine reset source) none none ? 0xfffc, 0xfffd clock monitor fail reset none copctl (cme, fcme) ? 0xfffa, 0xfffb cop failure reset none cop rate select ? 0xfff8, 0xfff9 unimplemented instruction trap none none ? 0xfff6, 0xfff7 swi none none ? 0xfff4, 0xfff5 xirq x-bit none ? 0xfff2, 0xfff3 irq i-bit intcr (irqen) 0xf2 0xfff0, 0xfff1 real time interrupt i-bit crgint (rtie) 0xf0 0xffe8 to 0xffef reserved 0xffe6, 0xffe7 standard timer 0 channel 4 i-bit tie (c4i) 0xe6 0xffe4, 0xffe5 standard timer 0 channel 5 i-bit tie (c5i) 0xe4 0xffe2, 0xffe3 standard timer 0 channel 6 i-bit tie (c6i) 0xe2 0xffe0, 0xffe1 standard timer 0 channel 7 i-bit tie (c7i) 0xe0 0xffde, 0xffdf standard timer overflow i-bit tscr2 (toi) 0xde 0xffdc, 0xffdd pulse accumulator overflow i-bit pactl(paovi) 0xdc 0xffda, 0xffdb pulse accumulator input edge i-bit pactl (pai) 0xda 0xffd8, 0xffd9 spi i-bit spicr1 (spie, sptie) 0xd8 0xffd6, 0xffd7 sci0 i-bit scicr2 (tie, tcie, rie, ilie) 0xd6 0xffd4, 0xffd5 sci1 i-bit scicr2 (tie, tcie, rie, ilie) 0xd4 0xffd2, 0xffd3 sci2 i-bit scicr2 (tie, tcie, rie, ilie) 0xd2 0xffd0, 0xffd1 atd i-bit atdctl2 (ascie) 0xd0 0xffce, 0xffcf port ad (kwu) i-bit ptadif (ptadie) 0xce 0xffc8 to 0xffcd reserved 0xffc6, 0xffc7 crg pll lock i-bit pllcr (lockie) 0xc6 0xffc4, 0xffc5 crg self clock mode i-bit pllcr (scmie) 0xc4 0xffc2, 0xffc3 reserved 0xffc0, 0xffc1 iic bus i-bit ibcr (ibie) 0xc0 0xffba to 0xffbf reserved 0xffb8, 0xffb9 flash i-bit fcnfg (ccie, cbeie) 0xb8 0xffb6, 0xffb7 standard timer 1 channel 4 i-bit tie (c4i) 0xb6 0xffb4, 0xffb5 standard timer 1 channel 5 i-bit tie (c5i) 0xb4 0xffb2, 0xffb3 standard timer 1 channel 6 i-bit tie (c6i) 0xb2 0xffb0, 0xffb1 standard timer 1 channel 7 i-bit tie (c7i) 0xb0 0xffae, 0xffaf standard timer 1 overflow i-bit tscr2 (toi) 0xae chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 76 freescale semiconductor 1.9.2 resets resets are a subset of th e interrupts featured in table 1-9 . the different sources capable of generating a system reset are summarized in table 1-10 . 1.9.2.1 reset summary table 0xffac, 0xffad standard timer 1 pulse accumulator overflow i-bit pactl (paovi) 0xac 0xffaa, 0xffab standard timer 1 pulse accumulator input edge i-bit pactl (pai) 0xaa 0xffa8, 0xffa9 reserved 0xffa6, 0xffa7 standard timer 2 channel 4 i-bit tie (c4i) 0xa6 0xffa4, 0xffa5 standard timer 2 channel 5 i-bit tie (c5i) 0xa4 0xffa2, 0xffa3 standard timer 2 channel 6 i-bit tie (c6i) 0xa2 0xffa0, 0xffa1 standard timer 2 channel 7 i-bit tie (c7i) 0xa0 0xff9e, 0xff9f standard timer overflow i-bit tscr2 (toi) 0x9e 0xff9c, 0xff9d standard timer 2 pulse accumulator overflow i-bit pactl (paovi) 0x9c 0xff9a, 0xff9b standard timer 2 pulse accumulator input edge i-bit pactl (pai) 0x9a 0xff98, 0xff99 pmf generator a reload i-bit pmfenca (pwmriea) 0x98 0xff96, 0xff97 pmf generator b reload i-bit pmfencb (pwmrieb) 0x96 0xff94, 0xff95 pmf generator c reload i-bit pmfencc (pwmriec) 0x94 0xff92, 0xff93 pmf fault 0 i-bit pmffctl (fie0) 0x92 0xff90, 0xff91 pmf fault 1 i-bit pmffctl (fie1) 0x90 0xff8e, 0xff8f pmf fault 2 i-bit pmffctl (fie2) 0x8e 0xff8c, 0xff8d pmf fault 3 i-bit pmffctl (fie3) 0x8c 0xff8a, 0xff8b vreg lvi i-bit ctrl0 (lvie) 0x8a 0xff88, 0xff89 pwm emergency s hutdown i-bit pwmsdn(pwmie) 0x88 0xff80 to 0xff87 reserved table 1-10. reset summary reset priority source vector power-on reset 1 crg module 0xfffe, 0xffff external reset 1 reset pin 0xfffe, 0xffff low voltage reset 1 vreg module 0xfffe, 0xffff clock monitor reset 2 crg module 0xfffc, 0xfffd cop watchdog reset 3 crg module 0xfffa, 0xfffb table 1-9. interrupt vector locations (continued) vector address interrupt source ccr mask local enable hprio value to elevate chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 77 1.9.2.2 effects of reset when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block description chapte rs for register reset states. refer to chapter 18, ?multiplexed external bus interface (mebiv3)? for mode dependent pin configuration of port a, b and e out of reset. refer to chapter 3, ?port integrat ion module (pim9e256v1)? for reset configurations of all peripheral module ports. refer to table 1-1 for locations of the memories depe nding on the operating mode after reset. the ram array is not automatica lly initialized out of reset. 1.10 recommended printed circuit board layout the printed circuit board (pcb) must be carefully laid out to ensu re proper operation of the voltage regulator as well as the mcu itself. the following rules must be observed: ? every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (c1?c6). ? central point of the ground star should be the vssr pin. ? use low ohmic low inductance connect ions between vss1, vss2 and vssr. ? vsspll must be directly connected to vssr. ? keep traces of vsspll, extal a nd xtal as short as possible an d occupied board area for c7, c8, c11 and q1 as small as possible. ? do not place other signals or supplies underneath area occupied by c7, c8, c10 and q1 and the connection area to the mcu. ? central power input should be fed in at the vdda/vssa pins. table 1-11. recommended decoupling capacitor choice component purpose type value c1 vdd1 filter cap ceramic x7r 100?220nf c2 vdd2 filter cap (80 qfp only) ceramic x7r 100?220nf c3 vdda filter cap ceramic x7r 100nf c4 vddr filter cap x7r/tantalum >=100nf c5 vddpll filter cap ceramic x7r 100nf c6 vddx filter cap x7r/tantalum >=100nf c7 osc load cap see pll specification chapter c8 osc load cap c9 pll loop filter cap c10 pll loop filter cap c11 dc cutoff cap r1 pll loop filter res q1 quartz chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 78 freescale semiconductor figure 1-8. recommended pcb layout (112-lqfp) note: oscillator in colpitts mode. c5 c4 c6 c1 c3 c2 c8 c7 q1 c10 c9 r1 vdd1 vss1 vddr vssr vddx vssx vdd2 vss2 vddpll vsspll vdda vssa c11 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 79 figure 1-9. recommended pcb layout (80-qfp) note: oscillator in colpitts mode. vdda c5 c4 c8 c7 q1 c10 c9 r1 vddr vssr vddpll vsspll c11 c1 c3 vdd1 vss1 vssa c6 vddx vssx c2 vdd2 vss2 chapter 1 mc9s12e256 device overview (mc9s12e256dgv1) mc9s12e256 data sheet, rev. 1.08 80 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 81 chapter 2 256 kbyte flash module (fts256k2v1) 2.1 introduction this document describes the fts256k2 module that includes a 256 kbyte flas h (nonvolatile) memory. the flash memory may be read as either bytes, aligne d words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. the flash memory is ideal for program and data stor age for single-supply applic ations allowing for field reprogramming without requiring exte rnal voltage sources for program or erase. program and erase functions are controlled by a comm and driven interface. the flash module supports both block erase and sector erase. an erased bit reads 1 and a program med bit reads 0. the high voltage required to program and erase the flash memory is generated internally. it is not possible to read from a flash block while it is being erased or programmed. caution a flash word must be in the eras ed state before being programmed. cumulative programming of bits with in a flash word is not allowed. 2.1.1 glossary banked register ? a memory-mapped register operating on one flash block which shares the same register address as the equivalent registers for the other flash blocks. the active register bank is selected by the bksel bit in the fcnfg register. command write sequence ? a three-step mcu instruction se quence to execute built-in algorithms (including program and eras e) on the flash memory. common register ? a memory-mapped register wh ich operates on all flash blocks. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 82 freescale semiconductor 2.1.2 features ? 256 kbytes of flash memory comprised of two 128 kbyte blocks with each block divided into 128 sectors of 1024 bytes ? automated program and erase algorithm ? interrupts on flash command co mpletion, command buffer empty ? fast sector erase and word program operation ? 2-stage command pipeline for fa ster multi-word program times ? sector erase abort feature fo r critical interrupt response ? flexible protection scheme to pr event accidental program or erase ? single power supply for all flash ope rations including program and erase ? security feature to prevent unaut horized access to the flash memory ? code integrity check using built-in data compression 2.1.3 modes of operation program, erase, erase veri fy, and data compress operations (please refer to section 2.4.1, ?flash command operations? for details). 2.1.4 block diagram a block diagram of the flash module is shown in figure 2-1 . chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 83 figure 2-1. fts256k2 block diagram fts256k2 oscillator clock divider clock command interface command pipelines comm2 command interrupt request common fclk addr2 data2 comm1 addr1 data1 flash block 0 64k * 16 bits flash block 1 64k * 16 bits registers banked registers protection security sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 flash block 0-1 chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 84 freescale semiconductor 2.2 external signal description the flash module contains no si gnals that connect off-chip. 2.3 memory map and register definition this subsection describes the memory map and registers for the flash module. 2.3.1 module memory map the flash memory map is shown in figure 2-2 . the hcs12 architecture places the flash memory addresses between 0x4000 and 0xffff which corresponds to three 16-kbyte pages. the content of the hcs12 core ppage register is used to map the logical middle page rangi ng from address 0x8000 to 0xbfff to any physical 16 kbyte page in the flash memory. by placing 0x3e or 0x3f in the hcs12 core ppage register, the associated 16 kbyte pa ges appear twice in the mcu memory map. the fprot register, described in section 2.3.2.5, ?flash protect ion register (fprot)? , can be set to globally protect a flash block. however, three sepa rate memory regions, one growing upward from the first address in the next-to-last page in the flash block (called th e lower region), one growing downward from the last address in the last page in the fl ash block (called the higher region), and the remaining addresses in the flash block, can be activated for protection. the flash locati ons of these protectable regions are shown in table 2-2 . the higher address region of flash block 0 is mainly targeted to hold the boot loader code because it covers the vector space. the lower address region of any flash block can be used for eeprom emulation in an mcu without an eeprom module because it can remain unprotected while the remaining addresses are protected from program or erase. security information that allows the mcu to restrict access to the flash module is stored in the flash configuration field found in flash block 0, described in table 2-1 . table 2-1. flash configuration field unpaged flash address paged flash address (ppage 0x3f) size (bytes) description 0xff00 ? 0xff07 0xbf00 ? 0xbf07 8 backdoor comparison key refer to section 2.6.1, ?unsecuring the mcu using backdoor key access? 0xff08 ? 0xff0b 0xbf08 ? 0xbf0b 4 reserved 0xff0c 0xbf0c 1 block 1 flash protection byte refer to section 2.3.2.7, ?flash st atus register (fstat)? 0xff0d 0xbf0d 1 block 0 flash protection byte refer to section 2.3.2.7, ?flash status register (fstat)? 0xff0e 0xbf0e 1 flash nonvolatile byte refer to section 2.3.2.9, ?flash co ntrol register (fctl)? 0xff0f 0xbf0f 1 flash security byte refer to section 2.3.2.2, ?flash se curity register (fsec)? chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 85 figure 2-2. flash memory map 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 block 1 flash registers module base + 0x0000 0xff00 ? 0xff0f, flash configuration field module base + 0x000f 0x8000 (16 bytes) flash protected low sectors 1, 2, 4, 8 kbytes flash_start = 0x4000 0x5000 0x4400 0x6000 16k paged memory 0x38 0x39 0x3a 0x3b 0x3e 0x3c 0x3d 0x3e 0x3f note: 0x30?0x3f correspond to the ppage register content flash_end = 0xffff 0xf800 0xf000 0xc000 0xe000 flash protected high sectors 2, 4, 8, 16 kbytes 0x3f block 0 0x4800 flash blocks chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 86 freescale semiconductor table 2-2. detailed flash memory map mcu address range ppage protectable lower range protectable higher range flash block block relative address 1 1 block relative address for each 128 kbyte flash block consists of 17 address bits. 0x4000?0x7fff unpaged (0x3e) 0x4000?0x43ff n.a. 0 0x018000?0x01bfff 0x4000?0x47ff 0x4000?0x4fff 0x4000?0x5fff 0x8000?0xbfff 0x30 n.a. n.a. 1 0x000000?0x003fff 0x31 n.a. n.a. 0x004000?0x007fff 0x32 n.a. n.a. 0x008000?0x00bfff 0x33 n.a. n.a. 0x00c000?0x00ffff 0x34 n.a. n.a. 0x010000?0x013fff 0x35 n.a. n.a. 0x014000?0x017fff 0x36 0x8000?0x83ff n.a. 0x018000?0x01bfff 0x8000?0x87ff 0x8000?0x8fff 0x8000?0x9fff 0x37 n.a. 0xb800?0xbfff 0x01c000?0x01ffff 0xb000?0xbfff 0xa000?0xbfff 0x8000?0xbfff 0x8000?0xbfff 0x38 n.a. n.a. 0 0x000000?0x003fff 0x39 n.a. n.a. 0x004000?0x007fff 0x3a n.a. n.a. 0x008000?0x00bfff 0x3b n.a. n.a. 0x00 c000?0x00ffff 0x3c n.a. n.a. 0x010000?0x013fff 0x3d n.a. n.a. 0x014000?0x017fff 0x3e 0x8000?0x83ff n.a. 0x018000?0x01bfff 0x8000?0x87ff 0x8000?0x8fff 0x8000?0x9fff 0x3f n.a. 0xb800?0xbfff 0x01c000?0x01ffff 0xb000?0xbfff 0xa000?0xbfff 0x8000?0xbfff 0xc000?0xffff unpaged (0x3f) n.a. 0xf800?0xffff 0 0x01c000?0x01ffff 0xf000?0xffff 0xe000?0xffff 0xc000?0xffff chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 87 the flash module also contains a set of 16 control and status registers loca ted in address space module base + 0x0000 to module base + 0x000f. in order to accommodate more than one flash block with a minimum register address space, a set of regi sters located from module base + 0x0004 to module base + 0x000b are repeated in all banks. the active re gister bank is selected by the bksel bits in the unbanked flash configuration regi ster (fcnfg). a summary of these registers is given in table 2-3 while their accessibility in normal and special modes is detailed in section 2.3.2, ?register descriptions? . table 2-3. flash register map module base + register name normal mode access 0x0000 flash clock divider register (fclkdiv) r/w 0x0001 flash security register (fsec) r 0x0002 flash test mode register (ftstmod) 1 1 intended for factory test purposes only. r 0x0003 flash configuration register (fcnfg) r/w 0x0004 flash protection register (fprot) r/w 0x0005 flash status register (fstat) r/w 0x0006 flash command register (fcmd) r/w 0x0007 flash control register (fctl) r 0x0008 flash high address register (faddrhi) 1 r 0x0009 flash low address register (faddrlo) 1 r 0x000a flash high data register (fdatahi) r 0x000b flash low data register (fdatalo) r 0x000c reserved1 1 r 0x000d reserved2 1 r 0x000e reserved3 1 r 0x000f reserved4 1 r chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 88 freescale semiconductor 2.3.2 register descriptions register name bit 7654321bit 0 fclkdiv r fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w fsec r keyen rnv5 rnv4 rnv3 rnv2 sec w ftstmod r 0 0 0 wrall 0000 w fcnfg r cbeie ccie keyacc 0000 bksel w fprot r fpopen rnv6 fphdis fphs fpldis fpls w fstat r cbeif ccif pviol accerr 0blank0 0 w fcmd r 0 cmdb w fctl r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w faddrhi r faddrhi w faddrlo r faddrlo w fdatahi r fdatahi w fdatalo r fdatalo w reserved1 r 0 0000000 w = unimplemented or reserved figure 2-3. fts256k2 register summary chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 89 2.3.2.1 flash clock divider register (fclkdiv) the unbanked fclkdiv register is used to contro l timed events in program and erase algorithms. all bits in the fclkdiv register are readable, b its 6-0 are write once and bit 7 is not writable. reserved2 r 0 0000000 w reserved3 r 0 0000000 w reserved4 r 0 0000000 w 76543210 r fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w reset00000000 = unimplemented or reserved figure 2-4. flash clock divider register (fclkdiv) table 2-4. fclkdiv field descriptions field description 7 fdivld clock divider loaded. 0 register has not been written. 1 register has been written to since the last reset. 6 prdiv8 enable prescalar by 8 . 0 the oscillator clock is directly fed into the clock divider . 1 the oscillator clock is divided by 8 before feeding into the clock divider. 5-0 fdiv[5:0] clock divider bits ? the combination of prdiv8 and fdiv[5:0] must divide the oscillator clock down to a frequency of 150 khz?200 khz. the maximum divide ratio is 512. please refer to section 2.4.1.1, ?writing the fclkdiv register? for more information. register name bit 7654321bit 0 = unimplemented or reserved figure 2-3. fts256k2 register summary (continued) chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 90 freescale semiconductor 2.3.2.2 flash security register (fsec) the unbanked fsec register holds all bits associated with the security of the mcu and flash module. all bits in the fsec register ar e readable but are not writable. the fsec register is loaded from the flash conf iguration field at address $ff0f during the reset sequence, indicated by f in figure 2-5 . the security function in the flash module is described in section 2.6, ?flash module security? . 76543210 r keyen rnv5 rnv4 rnv3 rnv2 sec w resetffffffff = unimplemented or reserved figure 2-5. flash security register (fsec) table 2-5. fsec field descriptions field description 1-0 keyen[1:0] backdoor key security enable bits ?the keyen[1:0] bits define the enabli ng of backdoor key access to the flash module as shown in ta b l e 2 - 6 . 5-2 rnv[5:2] reserved nonvolatile bits ? the rnv[5:2] bits must remain in t he erased 1 state for future enhancements. 1-0 sec[1:0] flash security bits ? the sec[1:0] bits define the securi ty state of the mcu as shown in ta b l e 2 - 7 . if the flash module is unsecured using backdoor key access, the sec bits are forced to 10. table 2-6. flas h keyen states keyen[1:0] status of backdoor key access 00 disabled 01 1 1 preferred keyen stat e to disable backdoor key access. disabled 10 enabled 11 disabled table 2-7. flash security states sec[1:0] status of security 00 secured 01 1 1 preferred sec state to se t mcu to secured state. secured 10 unsecured 11 secured chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 91 2.3.2.3 flash test mode register (ftstmod) the unbanked ftstmod register is us ed to control flash test features. all bits read 0 and are no t writable in normal mode. the wrall bit is writable only in special mode to simplify mass erase and erase verify operations. when writing to the ftstmod register in special mode, all unimplemented/reserved bits must be written to 0. 76543210 r0 0 0 wrall 0000 w reset00000000 = unimplemented or reserved figure 2-6. flash test mode register (ftstmod) table 2-8. ftstmod field descriptions field description 4 wrall write to all register banks ? if the wrall bit is set, all banked registers sharing the same register address will be written simultaneously during a register write. 0 write only to the bank selected via bksel. 1 write to all register banks. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 92 freescale semiconductor 2.3.2.4 flash configur ation register (fcnfg) the unbanked fcnfg register enab les the flash interrupts and gate s the security backdoor writes. cbeie, ccie, keyacc and bks el bits are readable and writable wh ile all remaining bits read 0 and are not writable. keyacc is only writable if keyen (see section 2.3.2.2, ?flash security register (fsec)? ) is set to the enabled state. 76543210 r cbeie ccie keyacc 0000 bksel w reset00000000 = unimplemented or reserved figure 2-7. flash configur ation register (fcnfg) table 2-9. fcnfg field descriptions field description 7 cbeie command buffer empty interrupt enable ? the cbeie bit enables an interrupt in case of an empty command buffer in the flash module. 0 command buffer empty interrupt disabled. 1 an interrupt will be requested whenever the cbeif flag (see section 2.3.2.7, ?flash status register (fstat)?) is set. 6 ccie command complete interrupt enable ? the ccie bit enables an interrupt in case all commands have been completed in the flash module. 0 command complete interrupt disabled. 1 an interrupt will be requested whenever the ccif flag (see section 2.3.2.7, ?flash st atus register (fstat)? ) is set. 5 keyacc enable security key writing 0 flash writes are interpreted as th e start of a command write sequence. 1 writes to flash array are interpreted as keys to open the backdoor. reads of the flash array return invalid data. 0 bksel block select ? the bksel bit indicates which register bank is active. 0 select register bank associated with flash block 0. 1 select register bank associated with flash block 1. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 93 2.3.2.5 flash protection register (fprot) the banked fprot register defines which flash sector s are protected against pr ogram or erase operations. all bits in the fprot register are readable and writable with restrict ions except for rnv[6] which is only readable (see section 2.3.2.6, ?flash protection restrictions? ). during reset, the banked fprot registers are loaded from the flash configurat ion field at the address shown in table 2-10 . to change the flash protection that will be loaded during the reset sequence, the upper sector of the flash memory must be unprotected, then the flas h protect/security byte located as described in table 2-1 must be reprogrammed. trying to alter data in any of the pr otected areas in the flash block will result in a protection violation error and the pviol flag will be set in the fstat register . a mass erase of the flash block is not possible if any of the contained flas h sectors are protected. 76543210 r fpopen rnv6 fphdis fphs fpldis fpls w resetffffffff = unimplemented or reserved figure 2-8. flash protection register (fprot) table 2-10. reset loading of fprot flash address protection byte for 0xff0d flash block 0 0xff0c flash block 1 table 2-11. fprot field descriptions field description 7 fpopen protection function bit ? the fpopen bit determines the protecti on function for program or erase as shown in ta bl e 2 - 1 2 . 0 fphdis and fpldis bits define unprotected address ranges as specified by the corresponding fphs[1:0] and fpls[1:0] bits. for an mcu witho ut an eeprom module, the fpopen cl ear state allows the main part of the flash block to be protected while a smal l address range can remain unprotected for eeprom emulation. 1 fphdis and fpldis bits enable protection for the address range specified by the corresponding fphs[1:0] and fpls[1:0] bits. 6 rnv[6] reserved nonvolatile bit ? the rnv[6] bit must remain in the erased state 1 for future enhancements. 5 fphdis flash protection higher address range disable ? the fphdis bit determines whether there is a protected/unprotecte d area in the higher address space of the flash block. 0 protection/unprotection enabled 1 protection/unprotection disabled 4:3 fphs[1:0] flash protection higher address size ? the fphs[1:0] bits determine the size of the prot ected/unprotected area as shown in ta b l e 2 - 1 3 . the fphs[1:0] bits can only be wr itten to while the fphdis bit is set. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 94 freescale semiconductor all possible flash protection scenarios are illustrated in figure 2-9 . although the protection scheme is loaded from the flash array after re set, it can be changed by the user. this protection scheme can be used by applications requiring re-program ming in single-chip mode while providing as much protection as possible if re-program ming is not required. 2 fpldis flash protection lower address range disable ? the fpldis bit determines whether there is a protected/unprotec ted area in the lower address space of the flash block. 0 protection/unprotection enabled 1 protection/unprotection disabled 1:0 fpls[1:0] flash protection lower address size ? the fpls[1:0] bits determine the size of the protected/unprotected area as shown in ta b l e 2 - 1 4 . the fpls[1:0] bits can only be wri tten to while the fpldis bit is set. table 2-12. flash protection function fpopen fphdis fpldis function 1 1 for range sizes, refer to ta b l e 2 - 1 3 and ta b l e 2 - 1 4 . 1 1 1 no protection 1 1 0 protected low range 1 0 1 protected high range 1 0 0 protected high and low ranges 0 1 1 full block protected 0 1 0 unprotected low range 0 0 1 unprotected high range 0 0 0 unprotected high and low ranges table 2-13. flash protection higher address range fphs[1:0] unpaged address range paged address range protected size 00 0xf800?0xffff 0x0037/0x0 03f: 0xc800?0xcfff 2 kbytes 01 0xf000?0xffff 0x0037/0x0 03f: 0xc000?0xcfff 4 kbytes 10 0xe000?0xffff 0x0037/0x003f: 0xb000?0xcfff 8 kbytes 11 0xc000?0xffff 0x0037/0x003 f: 0x8000?0xcfff 16 kbytes table 2-14. flash protection lower address range fpls[1:0] unpaged address range paged address range protected size 00 0x4000?0x43ff 0x0036/0x00 3e: 0x8000?0x83ff 1 kbyte 01 0x4000?0x47ff 0x0036/0x00 3e: 0x8000?0x87ff 2 kbytes 10 0x4000?0x4fff 0x0036/0x00 3e: 0x8000?0x8fff 4 kbytes 11 0x4000?0x5fff 0x0036/0x00 3e: 0x8000?0x9fff 8 kbytes table 2-11. fprot field descriptions (continued) field description chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 95 figure 2-9. flash protection scenarios 7 6 5 4 fphs[1:0] fpls[1:0] 3 2 1 0 fphs[1:0] fpls[1:0] fphdis = 1 fpldis = 1 fphdis = 1 fpldis = 0 fphdis = 0 fpldis = 1 fphdis = 0 fpldis = 0 scenario scenario unprotected region protected region with size protected region protected region with size defined by fpls defined by fphs not defined by fpls, fphs fpopen = 1 fpopen = 0 ppage 0x0036?0x0037 0x003e?0x003f ppage 0x0030?0x0035 0x0038?0x003d ppage 0x0036?0x0037 0x003e?0x003f ppage 0x0030?0x0035 0x0038?0x003d chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 96 freescale semiconductor 2.3.2.6 flash protection restrictions the general guideline is th at flash protection can only be added and not removed. table 2-15 specifies all valid transitions between flash protection scenarios. any attempt to write an invalid scenario to the fprot register will be ignored and the fprot regi ster will remain unchanged. the contents of the fprot register reflect the active protection scenario. see the fphs and fpls descri ptions for additional restrictions. 2.3.2.7 flash status register (fstat) the banked fstat register defines th e operational status of the module. table 2-15. flash protection scenario transitions from protection scenario to protection scenario 1 1 allowed transitions marked with x. 01234567 0 xxxx 1xx 2xx 3x 4xx 5 xxxx 6xxxx 7 xxxxxxxx 76543210 r cbeif ccif pviol accerr 0blank0 0 w reset11000000 = unimplemented or reserved figure 2-10. flash status register (fstat ? normal mode) 76543210 r cbeif ccif pviol accerr 0blank fail 0 w reset11000000 = unimplemented or reserved figure 2-11. flash status register (fstat ? special mode) chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 97 cbeif, pviol, and accerr are readab le and writable, ccif and blank are readab le and not writable, remaining bits read 0and are not writ able in normal mode. fail is readable and writable in special mode. fail must be clear when st arting a command write sequence. table 2-16. fstat field descriptions field description 7 cbeif command buffer empt y interrupt flag ? the cbeif flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. the cbeif fl ag is cleared by writing a 1 to cbeif. writing a 0 to the cbeif flag has no effect on cbeif. writing a 0 to cbeif after writing an aligned word to the flash address space but before cbeif is cleared will abort a command write sequence and cause the accerr flag to be set. writing a 0 to cbeif outsi de of a command write sequence will not set the accerr flag. the cbeif flag is used together with the cbeie bit in the fcnfg regist er to generate an interrupt request (see figure 2-29 ) . 0 buffers are full. 1 buffers are ready to accept a new command. 6 ccif command complete interrupt flag ? the ccif flag indicates that ther e are no more commands pending. the ccif flag is cleared when cbeif is clear and sets automatically upon completion of all active and pending commands. the ccif flag does not set when an active commands completes and a pending command is fetched from the command buffer. writing to the ccif flag has no effect on ccif. the ccif flag is used together with the ccie bit in the fcnfg register to generate an interrupt request (see figure 2-29 ). 0 command in progress. 1 all commands are completed. 5 pviol protection violation flag ? the pviol flag indicates an attempt was made to program or erase an address in a protected area of the flash block during a command wr ite sequence. the pviol flag is cleared by writing a 1 to pviol. writing a 0 to the pviol flag has no effect on pvi ol. while pviol is set, it is not possible to launch a command or start a command write sequence. 0 no failure. 1 a protection violation has occurred. 4 accerr access error flag ? the accerr flag indicates an illegal access to the flash array caused by either a violation of the command write sequence, issuing an ille gal command (illegal combination of the cmdbx bits in the fcmd register), launching the sector erase abort co mmand terminating a sector erase operation early or the execution of a cpu stop instruction while a command is executing (ccif = 0). the accerr flag is cleared by writing a 1 to accerr. writing a 0 to the accerr flag has no effect on accerr. while accerr is set in any of the banked ftsat registers, it is not possible to l aunch a command or start a command write sequence in any of the flash blocks. if accerr is set by an erase verify operation or a data compress operation, any buffered command will not launch. 0 no access error detected. 1 access error has occurred. 2 blank erase verify operation status flag ? when the ccif flag is set after completion of an erase verify command, the blank flag indicates the result of the erase verify operation. the blank flag is cleared by the flash module when cbeif is cleared as part of a new valid command write sequence. writing to t he blank flag has no effect on blank. 0 flash block verified as not erased. 1 flash block verified as erased. 1 fail flag indicating a fa iled flash operation ? the fail flag will set if the erase verify operation fails (selected flash block verified as not erased). the fail flag is clear ed by writing a 1 to fail. wr iting a 0 to the fail flag has no effect on fail. 0 flash operation completed without error. 1 flash operation failed. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 98 freescale semiconductor 2.3.2.8 flash command register (fcmd) the banked fcmd register is the flash command register. all cmdb bits are readable and wr itable during a command write sequence while bit 7 reads 0 and is not writable. 76543210 r0 cmdb w reset00000000 = unimplemented or reserved figure 2-12. flash command register (fcmd - nvm user mode) table 2-17. fcmd field descriptions field description 6-0 cmdb[6:0] flash command ? valid flash commands are shown in ta bl e 2 - 1 8 . writing any command other than those listed in ta bl e 2 - 1 8 sets the accerr flag in the fstat register. table 2-18. valid flash command list cmdb[6:0] nvm command 0x05 erase verify 0x06 data compress 0x20 word program 0x40 sector erase 0x41 mass erase 0x47 sector erase abort chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 99 2.3.2.9 flash control register (fctl) the banked fctl register is the flash control register. all bits in the fctl register ar e readable but are not writable. the fctl register is loaded from the flash configuration field byte at $ff0e during the reset sequence, indicated by f in figure 2-13 . 2.3.2.10 flash address registers (faddr) the banked faddrhi and faddrlo regist ers are the flash address registers. all faddrhi and faddrlo bits are readable but are not writable. after an ar ray write as part of a command write sequence, the faddr registers wi ll contain the mapped mcu address written. 76543210 r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w resetffffffff = unimplemented or reserved figure 2-13. flash control register (fctl) table 2-19. fctl fi eld descriptions field description 7-0 nv[7:0] nonvolatile bits ? the nv[7:0] bits are available as nonvolatile bits. refer to the device user guide for proper use of the nv bits. 76543210 r faddrhi w reset00000000 = unimplemented or reserved figure 2-14. flash address high register (faddrhi) 76543210 r faddrlo w reset00000000 = unimplemented or reserved figure 2-15. flash address low register (faddrlo) chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 100 freescale semiconductor 2.3.2.11 flash data registers (fdata) the banked fdatahi and fdatalo regist ers are the flash data registers. all fdatahi and fdatalo bits are re adable but are not writable. afte r an array write as part of a command write sequence, the fdata registers will contain the data written. at the comp letion of a data compress operation, the result ing 16-bit signature is stored in the fdata regi sters. the data compression signature is readable in the fdata register s until a new command write sequence is started . 2.3.2.12 reserved1 this register is reserved for fa ctory testing and is not accessible. all bits read 0 and are not writable. 2.3.2.13 reserved2 this register is reserved for fact ory testing and is not accessible. all bits read 0 and are not writable. 76543210 rfdatahi w reset00000000 = unimplemented or reserved figure 2-16. flash data high register (fdatahi) 76543210 rfdatalo w reset00000000 = unimplemented or reserved figure 2-17. flash data low register (fdatalo) 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 2-18. reserved1 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 2-19. reserved2 chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 101 2.3.2.14 reserved3 this register is reserved for fa ctory testing and is not accessible. all bits read 0 and are not writable. 2.3.2.15 reserved4 this register is reserved for fa ctory testing and is not accessible. all bits read 0 and are not writable. 2.4 functional description 2.4.1 flash command operations write and read operations are both used for the program , erase, erase verify, a nd data compress algorithms described in this subsection. the program and erase algorithms are time controlled by a state machine whose timebase, fclk, is derived from the oscillat or clock via a programmabl e divider. the command register as well as the associated address and data re gisters operate as a buffer a nd a register (2-stage fifo) so that a second command al ong with the necessary data and address can be stored to the buffer while the first command remains in progress. this pipeli ned operation allows a time optimization when programming more than one word on a specific row in the flash block as the high voltage generation can be kept active in between tw o programming commands. the pipe lined operation also allows a simplification of command launching. buffer empty as well as co mmand completion are signalled by flags in the flash status register with interrupts generated, if enabled. the next paragraphs describe: 1. how to write the fclkdiv register. 2. command write sequences used to program , erase, and verify the flash memory. 3. valid flash commands. 4. effects resulting from illegal flash command write sequences or aborting flash operations. 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 2-20. reserved3 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 2-21. reserved4 chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 102 freescale semiconductor 2.4.1.1 writing the fclkdiv register prior to issuing any program, erase, erase verify, or data compress comm and, it is first n ecessary to write the fclkdiv register to divide the oscillator clock down to within the 150 khz to 200 khz range. because the program and erase timings are al so a function of the bus clock, the fclkdiv dete rmination must take this information into account. if we define: ? fclk as the clock of the flash timing control block, ? tbus as the period of the bus clock, and ? int(x) as taking the integer part of x (e.g. int(4.323)=4). then, fclkdiv register bits prdiv8 and fd iv[5:0] are to be set as described in figure 2-22 . for example, if the oscillator clock frequency is 950 khz and the bus clock frequency is 10 mhz, fclkdiv bits fdiv[5:0] must be set to 4 (000100) and bit prdiv8 set to 0. the resulting fclk frequency is then 190 khz. as a result, the flash pr ogram and erase al gorithm timings ar e increased over the optimum target by: caution program and erase command executi on time will incr ease proportionally with the period of fclk. because of the impact of clock synchronization on the accuracy of the functional timi ngs, programming or erasing the flash memory cannot be performed if the bu s clock runs at less than 1 mhz. programming or erasing the flash me mory with fclk < 150 khz must be avoided. setting fclkdiv to a valu e such that fclk < 150 khz can destroy the flash memory due to overs tress. setting fclkdiv to a value such that (1/fclk + tbus) < 5 s can result in incomplete programming or erasure of the flash memory cells. if the fclkdiv register is written, the fdivld bit is set automatically. if the fdivld bit is 0, the fclkdiv register has not been written since the last reset. flash commands will not be executed if the fclkdiv register has not been written to. 200 190 ? () 200 ? 100 5% = chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 103 figure 2-22. determination procedure for prdiv8 and fdiv bits prdiv8=1 yes no prdiv8=0 (reset) fclk=(prdclk)/(1+fdiv[5:0]) prdclk=oscillator_clock prdclk=oscillator_clock/8 prdclk[mhz]*(5+tbus[ s]) no fdiv[5:0]=prdclk[mhz]*(5+tbus[ s])-1 yes start tbus < 1 s? an integer? fdiv[5:0]=int(prdcl k[mhz]*(5+tbus[ s])) 1/fclk[mhz] + tbus[ s] > 5 and fclk > 0.15 mhz ? end yes no fdiv[5:0] > 4? all commands impossible yes no all commands impossible no try to decrease tbus yes oscillator clock > 12.8 mhz? chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 104 freescale semiconductor 2.4.1.2 command write sequence the flash command controller is us ed to supervise the command wr ite sequence to execute program, erase, erase verify, and data compress algorithms. before starting a command write seque nce, the accerr and pviol flags in the fstat register must be clear (see section 2.3.2.7, ?flash status register (fstat)? ) and the cbeif flag must be tested to determine the state of the address, data, and comma nd buffers. if the cbeif flag is set, indicating the buffers are empty, a new command wr ite sequence can be started. if the cbeif flag is clear, indicating the buffers are not available, a new comm and write sequence will overwrite th e contents of th e address, data, and command buffers. a command write sequence consists of three steps whic h must be strictly adhered to with writes to the flash module not permitted between the steps. however, flash register and arra y reads are allowed during a command write sequence. a command write se quence consists of the following steps: 1. write an aligned data word to a valid flash array address. the address and da ta will be stored in the address and data buffers, respectively. if the cbeif flag is clear when the flash array write occurs, the contents of the address and data buffers will be overwritten and the cbeif flag will be set. 2. write a valid command to the fcmd register. a) for the erase verify command (see section 2.4.1.3.1, ?erase verify command? ), the contents of the data buffer are ignor ed and all address bits in the address buffer are ignored. b) for the data compress command (see section 2.4.1.3.2, ?data compress command? ), the contents of the data buffer represents the num ber of consecutive words to read for data compression and the contents of the addre ss buffer represents the starting address. c) for the program command (see section 2.4.1.3.3, ?program command? ), the contents of the data buffer will be programmed to the address sp ecified in the address buffer with all address bits valid. d) for the sector erase command (see section 2.4.1.3.4, ?sector erase command? ), the contents of the data buffer are ignored and address bits [9:0] contained in the a ddress buffer are ignored. e) for the mass erase command (see section 2.4.1.3.5, ?mass erase command? ), the contents of the data buffer and address buffer are ignored. f) for the sector erase abort command (see section 2.4.1.3.6, ?sector erase abort command? ), the contents of the data buffer and address buffer are ignored. 3. clear the cbeif flag by writing a 1 to cbeif to launch the command. when the cbeif flag is cleared, the ccif flag is cleared on the same bu s cycle by internal hardware indicating that the command was successfully launche d. for all command write sequen ces except data compress and sector erase abort, the cbeif flag will set four bus cycles after the ccif flag is cleared indicating that the address, data, and comm and buffers are ready for a new command write sequence to begin. for data compress and sector erase abort operati ons, the cbeif flag will remain clear until the operation completes. a command write sequence can be a borted prior to clearing the cbeif flag by writing a 0 to the cbeif flag and will result in the accerr flag being set. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 105 except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. the sector erase abort command is launched when the cbeif flag is cleared as part of a sector erase abort comman d write sequence. after a command is launched, the completion of the comm and operation is indica ted by the setting of the ccif flag. the ccif flag only sets when all active and buffered commands have been completed. 2.4.1.3 valid flash commands table 2-20 summarizes the valid flash commands along wi th the effects of the commands on the flash block. caution a flash word must be in the eras ed state before being programmed. cumulative programming of bits with in a flash word is not allowed. table 2-20. valid flash command description fcmdb nvm command function on flash memory 0x05 erase verify verify all memory bytes in the flash block ar e erased. if the flash block is erased, the blank flag in the fstat register will set upon command completion. 0x06 data compress compress data from a selected portion of the flas h block. the resulting signature is stored in the fdata register. 0x20 program program a word (two bytes) in the flash block. 0x40 sector erase erase all memory bytes in a sector of the flash block. 0x41 mass erase erase all memory bytes in the flash block. a mass erase of the full flash block is only possible when fpldis, fphdis, and fpopen bits in the fprot r egister are set prior to launching the command. 0x47 sector erase abort abort the sector erase operation. the sector er ase operation will terminate according to a set procedure. the flash sector must not be consid ered erased if the accerr flag is set upon command completion. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 106 freescale semiconductor 2.4.1.3.1 erase verify command the erase verify operation is used to confirm that a fl ash block is erased. after launching the erase verify command, the ccif flag in the fstat register will set after the opera tion has completed unless a second command has been buffered. the number of bus cycles required to execute the erase verify operation is equal to the number of addresses in the flash block plus 12 bus cycles as me asured from the time the cbeif flag is cleared until the ccif flag is set. the result of the erase verify operation is reflected in the state of the blank flag in the fstat register. if the blank flag is set in the fs tat register, the flash memory is erased. figure 2-23. example erase verify command flow write: register fclkdiv read: register fclkdiv bit fdivld set? write: flash block address write: register fcmd erase verify command 0x05 write: register fstat yes no clear bit cbeif 0x80 clock register loaded check 1. 2. 3. clear bit accerr 0x10 write: register fstat yes access error check read: register fstat no no and dummy data bit polling for command completion check read: register fstat note: command write sequence aborted by writing 0x00 to fstat register. note: command write sequence aborted by writing 0x00 to fstat register. ccif set? bit accerr set? bit exit yes blank set? bit yes no flash block not erased; mass erase flash block chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 107 2.4.1.3.2 data compress command the data compress command is used to check flash c ode integrity by compressing data from a selected portion of the flash block into a signature analyzer . the starting address for the data compress operation is defined by the address writte n during the command write sequence. the number of consecutive word addresses compressed is de fined by the data written dur ing the command write seque nce. if the data value written is 0x0000, 64k addresses or 128 kbytes will be compressed. after launching the data compress command, the ccif flag in the fstat register will set after the data compress operation has completed. the number of bus cycles required to execute the data compress operation is equa l to two times the number of addresses read plus 20 bus cycles as measured from the time the cb eif flag is cleared until the ccif flag is set. after the ccif flag is set, the signatu re generated by the data co mpress operation is available in the fdata register. the signature in the fdata re gister can be compared to the expected signature to determine the integrity of the selected data stored in the flash block. if the last address of the flash block is reached during the data compress operation, data compression will conti nue with the starting address of the flash block. note since the fdata register (or data buffer) is written to as part of the data compress operation, a command write sequence is not allowed to be buffered behind a data compress comma nd write sequence. the cbeif flag will not set after launching the data compress command to indicate that a command must not be buffered behind it. if an attempt is made to start a new command write sequence with a da ta compress operation active, the accerr flag in the fstat register will be set. a new command write sequence must only be started after re ading the signature stored in the fdata register. in order to take corrective action, it is recommended that the data co mpress command be executed on a flash sector or subset of a flash sector. if the data compress operation on a flash sector re turns an invalid signature, the flash sector must be erased using the sector erase co mmand and then reprogrammed using the program command. the data compress command can be used to verify that a sector or sequential se t of sectors are erased. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 108 freescale semiconductor figure 2-24. example data compress command flow write: register fclkdiv read: register fclkdiv bit fdivld set? write: flash address to start write: register fcmd data compress command 0x06 write: register fstat yes no clear bit cbeif 0x80 clock register loaded check 1. 2. 3. clear bit accerr 0x10 write: register fstat yes no access error check read: register fstat no exit compression and number of bit polling for command completion check read: register fstat yes note: command write sequence aborted by writing 0x00 to fstat register. note: command write sequence aborted by writing 0x00 to fstat register. ccif set? bit accerr set? bit word addresses to compress read: register fdata data compress signature no erase and reprogram yes signature valid? signature flash region compressed compared to known value chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 109 2.4.1.3.3 program command the program command is used to program a previous ly erased word in the flash memory using an embedded algorithm. if the word to be programmed is in a protected area of the flash block, the pviol flag in the fstat register will set and the program command will not launch. after the program command has successfully launched, the ccif flag in the fstat register will set after the program operation has completed unless a second command has been buffered. a summary of the launching of a program operation is shown in figure 2-25 . figure 2-25. example program command flow write: register fclkdiv read: register fclkdiv bit fdivld set? write: flash address and write: register fcmd program command 0x20 write: register fstat yes no clear bit cbeif 0x80 yes clock register loaded check 1. 2. 3. clear bit accerr 0x10 write: register fstat no yes no protection violation check access error check read: register fstat no no address, data, command buffer empty check next write? yes exit no program data clear bit pviol 0x20 write: register fstat yes bit polling for command completion check read: register fstat yes note: command write sequence aborted by writing 0x00 to fstat register. note: command write sequence aborted by writing 0x00 to fstat register. ccif set? bit cbeif set? bit accerr set? bit pviol set? bit chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 110 freescale semiconductor 2.4.1.3.4 sector erase command the sector erase command is used to erase the addressed sector in the flash memory using an embedded algorithm. if the flash sector to be erased is in a pr otected area of the flash bl ock, the pviol flag in the fstat register will set and the sector erase comm and will not launch. after the sector erase command has successfully launche d, the ccif flag in the fstat register will set after the sector erase operation has completed unless a second command has been buffered. figure 2-26. example sector erase command flow write: register fclkdiv read: register fclkdiv bit fdivld set? write: flash sector address write: register fcmd sector erase command 0x40 write: register fstat yes no clear bit cbeif 0x80 yes clock register loaded check 1. 2. 3. clear bit accerr 0x10 write: register fstat no yes no protection violation check access error check read: register fstat no no address, data, command buffer empty check next write? yes exit no and dummy data clear bit pviol 0x20 write: register fstat yes bit polling for command completion check read: register fstat yes note: command write sequence aborted by writing 0x00 to fstat register. note: command write sequence aborted by writing 0x00 to fstat register. ccif set? bit pviol set? bit accerr set? bit cbeif set? bit chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 111 2.4.1.3.5 mass erase command the mass erase command is used to erase a flash memory bl ock using an embedded al gorithm. if the flash block to be erased contains any protected area, the pviol flag in th e fstat register will set and the mass erase command will not la unch. after the mass erase command has successfully launched, the ccif flag in the fstat register will set after the mass erase opera tion has completed unle ss a second command has been buffered. figure 2-27. example mass erase command flow write: register fclkdiv read: register fclkdiv bit fdivld set? write: flash block address write: register fcmd mass erase command 0x41 write: register fstat yes no clear bit cbeif 0x80 yes clock register loaded check 1. 2. 3. clear bit accerr 0x10 write: register fstat no yes no protection violation check access error check read: register fstat ccif set? bit no no address, data, command buffer empty check next write? yes exit no and dummy data clear bit pviol 0x20 write: register fstat yes bit polling for command completion check read: register fstat yes note: command write sequence aborted by writing 0x00 to fstat register. note: command write sequence aborted by writing 0x00 to fstat register. pviol set? bit accerr set? bit cbeif set? bit chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 112 freescale semiconductor 2.4.1.3.6 sector erase abort command the sector erase abort comma nd is used to terminate the sector eras e operation so that ot her sectors in the flash block are available for read and program operations without wait ing for the sector erase operation to complete. if the sector erase a bort command is launched resulting in the early termination of an active sector erase operation, the accerr flag will set after the operation co mpletes as indicated by the ccif flag being set. the accerr flag sets to inform the us er that the sector may not be fully erased and a new sector erase command must be launched before program ming any location in that specific sector. if the sector erase abort command is la unched but the active sector eras e operation completes normally, the accerr flag will not set upon completion of the ope ration as indicated by the ccif flag being set. therefore, if the accerr flag is not set after the sector erase abort command has completed, the sector being erased when the abort comm and was launched is fully erase d. the maximum number of cycles required to abort a sector erase operation is equal to four fclk periods (see section 2.4.1.1, ?writing the fclkdiv register? ) plus five bus cycles as me asured from the time the cbeif flag is cleared until the ccif flag is set. note since the accerr bit in the fstat register may be set at the completion of the sector erase abort operati on, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. the cbeif flag will not set after laun ching the sector erase abort command to indicate that a command must not be buffered behind it. if an attempt is made to start a new command write sequence with a sector erase abort operation active, the accerr flag in the fstat register will be set. a new command write sequence may be started after clearing the accerr flag, if set. note the sector erase abort command must be used sparingly because a sector erase operation that is aborted counts as a complete program/erase cycle. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 113 figure 2-28. example sector erase abort command flow write: dummy flash address write: register fcmd sector erase abort cmd 0x47 write: register fstat clear bit cbeif 0x80 1. 2. 3. read: register fstat no exit and dummy data bit polling for command completion check read: register fstat yes note: command write sequence aborted by writing 0x00 to fstat register. note: command write sequence aborted by writing 0x00 to fstat register. ccif set? bit execute sector erase command flow no bit polling for command completion check read: register fstat yes ccif set? bit no yes abort needed? erase exit clear bit accerr 0x10 write: register fstat yes no access error check accerr set? bit exit sector erase completed sector erase aborted chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 114 freescale semiconductor 2.4.1.4 illegal flash operations the accerr flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. writing to a flash address before initializing the fclkdiv register. 2. writing to a flash address in the range 0x8000?0 xbfff when the ppage regi ster does not select a 16 kbyte page in the flash block select ed by the bksel bit in the fcnfg register. 3. writing to a flash address in the range 0x4000?0x7fff or 0xc000?0xffff with the bksel bit in the fcnfg register not selecting flash block 0. 4. writing a byte or misaligned wo rd to a valid flash address. 5. starting a command write sequence while a data compress operation is active. 6. starting a command write se quence while a sector erase abort operation is active. 7. writing a second word to a flash addr ess in the same command write sequence. 8. writing to any flash register other than fc md after writing a word to a flash address. 9. writing a second command to the fcmd regi ster in the same command write sequence. 10. writing an invalid command to the fcmd register. 11. when security is enabled, writing a command othe r than mass erase to the fcmd register when the write originates from a non-secure memory location or from the background debug mode. 12. writing to any flash register other than fs tat (to clear cbeif) after writing to the fcmd register. 13. writing a 0 to the cbeif flag in the fstat register to abort a command write sequence. the accerr flag will not be set if any flash regi ster is read during a va lid command write sequence. the accerr flag will also be set if any of the following events occur: 1. launching the sector erase abort command while a sector erase operation is active which results in the early termination of the sector erase operation (see section 2.4.1.3.6, ?sector erase abort command? ) 2. the mcu enters stop mode and a program or er ase operation is in progress. the operation is aborted immediately and any pe nding command is purged (see section 2.5.2, ?stop mode? ). if the flash memory is read during execution of an al gorithm (i.e., ccif flag in th e fstat register is low), the read operation will return invalid data and the accerr flag will not be set. if the accerr flag is set in the fstat register, th e user must clear the accerr flag before starting another command write sequence (see section 2.3.2.7, ?flash status register (fstat)? ). the pviol flag will be set after the command is wr itten to the fcmd register during a command write sequence if any of the following il legal operations are atte mpted, causing the comma nd write sequence to immediately abort: 1. writing the program command if the address wr itten in the command write sequence was in a protected area of the flash memory. 2. writing the sector erase comma nd if the address written in the command write sequence was in a protected area of the flash memory. 3. writing the mass erase command while any flash protection is enabled. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 115 if the pviol flag is set in the fstat register, the us er must clear the pviol fl ag before starting another command write sequence (see section 2.3.2.7, ?flash status register (fstat)? ). 2.5 operating modes 2.5.1 wait mode if a command is active (ccif = 0) when the mcu ente rs wait mode, the active command and any buffered command will be completed. the flash module can recover the mc u from wait mode if the cbeif and ccif interrupts are enabled ( section 2.8, ?interrupts? ). 2.5.2 stop mode if a command is active (ccif = 0) when the mcu enters stop mode, the operation wi ll be aborted and, if the operation is program or erase, the flash array da ta being programmed or eras ed may be corrupted and the ccif and accerr flags will be set. if active, the high voltage circuitry to the flash memory will immediately be switched off when entering stop mode . upon exit from stop mode, the cbeif flag is set and any buffered command will not be launched. the accerr flag must be cleared before starting a command write sequence (see section 2.4.1.2, ?command write sequence? ). note as active commands are immediately aborted when the mcu enters stop mode, it is strongly recommended th at the user does not use the stop instruction during program or erase operations. 2.5.3 background debug mode in background debug mode (bdm), the fprot register is writable. if the mcu is unsecured, then all flash commands listed in table 2-20 can be executed. 2.6 flash module security the flash module provides the necessary security info rmation to the mcu. after each reset, the flash module determines the security st ate of the mcu as defined in section 2.3.2.2, ?flash security register (fsec)? . the contents of the flash security byte at 0xff0f in the flas h configuration field must be changed directly by programming 0xff0f when the mcu is unsecured and the higher address sector is unprotected. if the flash security byte remains in a secured state, any reset will cause the mcu to initialize to a secure operating mode. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 116 freescale semiconductor 2.6.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor ke y access feature which requires knowledge of the contents of the backdoor keys (four 16-bit wo rds programmed at addre sses 0xff00?0xff07). if the keyen[1:0] bits are in the enabled state (see section 2.3.2.2, ?flash security register (fsec)? ) and the keyacc bit is set, a write to a backdoor key addres s in the flash memory triggers a comparison between the written data and the backdoor key data stored in the flash memory. if all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the flash memory, the mcu will be unsecured. the data must be written to the backdoor keys seque ntially starting with 0xff00?0xff01 and ending with 0xff06?0xf f07. 0x0000 and 0xffff are not permitted as backdoor keys. while the keyacc bit is set, reads of the flash memory wi ll return invalid data. the user code stored in the flash memory must have a method of receiving the backdoor key from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bits are in the enabled state (see section 2.3.2.2, ?flash security register (fsec)? ), the mcu can be unsecured by the bac kdoor access sequence described below: 1. set the keyacc bit in the flas h configuration re gister (fcnfg). 2. write the correct four 16-bit words to flash addresses 0xff00?0xff07 se quentially starting with 0xff00. 3. clear the keyacc bit. 4. if all four 16-bit words match the backdoor ke ys stored in flash addresses 0xff00?0xff07, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 1:0. the backdoor key access sequen ce is monitored by an inte rnal security state mach ine. an illegal operation during the backdoor key access sequence will cause the security state ma chine to lock, leaving the mcu in the secured state. a reset of the mcu will cause the security state machine to exit the lock state and allow a new backdoor key access seque nce to be attempted. the follow ing operations during the backdoor key access sequence will lock the security state machine: 1. if any of the four 16-bit words does not match the backdoor keys programmed in the flash array. 2. if the four 16-bit words are written in the wrong sequence. 3. if more than four 16-bit words are written. 4. if any of the four 16-bit words written are 0x0000 or 0xffff. 5. if the keyacc bit does not remain set while the four 16-bit words are written. 6. if any two of the four 16-bit words ar e written on successive mcu clock cycles. after the backdoor keys have been correctly matched, the mcu will be unsecured. after the mcu is unsecured, the flash security byte can be progr ammed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0xff00?0xff07 in the flash configuration field. the security as defined in the flash security byte (0xff0f) is not changed by using the backdoor key access sequence to unsecure. the backdoor keys st ored in addresses 0xff00?0xff07 are unaffected by the backdoor key access sequence. afte r the next reset of the mcu, the security state of the flash module chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 117 is determined by the flash secur ity byte (0xff0f). the backdoor key access sequence has no effect on the program and erase protections define d in the flash protection register. it is not possible to unsecure the mcu in specia l single-chip mode by using the backdoor key access sequence via the background debug mode (bdm). 2.6.2 unsecuring the flash module in special single-chip mode using bdm the mcu can be unsecured in special single-chip mode by erasing the flash module by the following method : ? reset the mcu into special single-chip mode, de lay while the erase test is performed by the bdm secure rom, send bdm commands to disable protection in the fl ash module, and execute a mass erase command write sequence to erase the flash memory. after the ccif flag sets to indicate that the mass operation has completed, reset the mcu into special single-chip mode. the bdm secure ro m will verify that the flash memo ry is erased and will assert the unsec bit in the bdm status regist er. this bdm action will cause the mcu to override the flash security state and the mcu will be unsecured. al l bdm commands will be enable d and the flash security byte may be programmed to the unsecur e state by the following method: ? send bdm commands to execute a word program sequence to progr am the flash security byte to the unsecured state and reset the mcu. 2.7 resets 2.7.1 flash reset sequence on each reset, the flash module executes a reset sequence to hold cpu activity while loading the following registers from the flash memory according to table 2-1 : ? fprot ? flash protection register (see section 2.3.2.5, ?flash protect ion register (fprot)? ). ? fctl ? flash control register (see section 2.3.2.9, ?flash control register (fctl)? ). ? fsec ? flash security register (see section 2.3.2.2, ?flash security register (fsec)? ). 2.7.2 reset while flash command active if a reset occurs while any flash command is in progr ess, that command will be immediately aborted. the state of the word being programmed or the se ctor / block being erased is not guaranteed. chapter 2 256 kbyte flash module (fts256k2v1) mc9s12e256 data sheet, rev. 1.08 118 freescale semiconductor 2.8 interrupts the flash module can generate an interrupt when all flash command operations have completed, when the flash address, data, a nd command buffers are empty. note vector addresses and their relative inte rrupt priority are determined at the mcu level. 2.8.1 description of flas h interrupt operation the logic used for generating interrupts is shown in figure 2-29 . the flash module uses the cbeif and ccif flags in combination with th e cbie and ccie enable bits to generate the flash command interrupt request. figure 2-29. flash interrupt implementation for a detailed description of the register bits, refer to section 2.3.2.4, ?flash co nfiguration register (fcnfg)? and section 2.3.2.7, ?flash status register (fstat)? . table 2-21. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash address, data and command buffers empty cbeif (fstat register) cbeie (fcnfg register) i bit all flash commands completed ccif (fstat register) ccie (fcnfg register) i bit block 0 cbeif flash command block 0 select cbeie block 1 cbeif block 1 select block 0 ccif block 0 select ccie block 1 ccif block 1 select interrupt request mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 119 chapter 3 port integration module (pim9e256v1) 3.1 lntroduction the port integration module establishes the interface between the peripheral modul es and the i/o pins for for ports ad, m, p, q, s, t and u. this section covers: ? port a, b, e, and k and the bkgd pin ? port ad associated with atd module (channels 15 through 0) and keyboard wake-up interrupts ? port m connected to 2 dac, 1 iic and 1 sci (sci2) modules ? port p and port q connected to pmf module ? port s connected to 2 sci (s ci0 and sci1) and 1 spi modules ? port t connected to 2 tim (tim0 and tim1) modules ? port u connected to 1 tim (tim2) and 1 pwm modules each i/o pin can be confi gured by several regist ers: input/output selection, drive strength reduction, enable and select of pull resistors, wi red-or mode selectio n, interrupt enable, and/or status flags. note refer to chapter 3, ?port integrat ion module (pim9e256v1)? for details on ports a, b, e and k, and the bkgd pin. 3.1.1 features a standard port has the fo llowing minimum features: ? input/output selection ? 5-v output drive with two selectab le drive strength (or slew rates) ? 5-v digital and analog input ? input with selectable pull-up or pull-down device optional features: ? open drain for wired-or connections ? interrupt input with glitch filtering chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 120 freescale semiconductor 3.1.2 block diagram figure 3-1 is a block diagram of the pim9e256v1. figure 3-1. pim9e256v1 block diagram port t pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 tim0/tim1 ioc04 ioc05 ioc06 ioc07 ioc14 ioc15 ioc16 ioc17 port p pp0 pp1 pp2 pp3 pp4 pp5 port s ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 rxd txd rxd txd sdi/miso sdo/mosi sck ss sci0 sci1 spi port q port m sci2 rxd2 txd2 iic sda scl port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port a pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 port e pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 port k pk0 pk1 pk2 pk3 pk7 pk4 pk5 addr8/data8 addr9/data9 addr10/data10 addr11/data11 addr12/data12 addr13/data13 addr14/data14 addr15/data15 addr0/data0 addr1/data1 addr2/data2 addr3/data3 addr4/data4 addr5/data5 addr6/data6 addr7/data7 xirq irq r/w lstrb /taglo eclk ipipe0/moda noacc/xclks ipipe1/modb xaddr15 xaddr16 xaddr17 ecs /romone xadrr18 xaddr19 core xaddr14 can0 routing bkgd/modc/taghi bkgd hhhkhkjsdhfshdfhskdf fault0 fault1 fault2 fault3 is0 pmf pm7 dao1 dao0 pm6 pm5 pm4 pm3 pm1 pm0 port u ioc24 ioc25 ioc27 port integration module tim2 pu0 pu1 pu2 pu3 pu4 pu5 pu6 pu7 adc pa d 8 pa d 9 pa d 0 pa d 1 pa d 2 pa d 3 pa d 4 pa d 5 pa d 6 pa d 7 port ad pa d 1 0 pa d 1 1 pa d 1 2 pa d 1 3 pa d 1 4 pa d 1 5 interrupt logic pq6 pq5 pq4 pq3 pq2 pq1 pq0 ioc26 pw15 pw14 pw13 pw12 pw11 pw04 pw03 pw02 pw01 pw00 pw10 pw05 mux pwm pk6 xcs an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 dac1 dac0 is2 is1 kwad0 kwad1 kwad2 kwad3 kwad4 kwad5 kwad6 kwad7 kwad8 kwad9 kwad10 kwad11 kwad12 kwad13 kwad14 kwad15 chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 121 3.2 external signal description this section lists and describes th e signals that connect off chip. table 3-1 shows all the pins and their functions that are controlled by the pim9e256v1. the order in which the pin functions are listed represents the func tions priority (top ? highest priority, bottom ? lowest priority). table 3-1. detailed signal descriptions (sheet 1 of 7) port pin name pin function description pin function after reset ? bkgd modc refer to chapter 18, ?multiplexed external bus interface (mebiv3)? refer to chapter 18, ?multiplexed external bus interface (mebiv3)? bkgd refer to chapter 15, ?background debug module (bdmv4)? tag h i refer to chapter 18, ?multiplexed external bus interface (mebiv3)? port a pa7 addr15/data15 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pa6 addr14/data14 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pa5 addr13/data13 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pa4 addr12/data12 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pa3 addr11/data11 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pa2 addr10/data10 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pa1 addr9/data9 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pa0 addr8/data8 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 122 freescale semiconductor port b pb7 addr7/data7 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pb6 addr6/data6 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pb5 addr5/data5 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pb4 addr4/data4 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pb3 addr3/data3 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pb2 addr2/data2 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pb1 addr1/data1 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pb0 addr0/data0 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o port e pe7 xclks refer to chapter 5, ?oscillator (oscv2)? refer to chapter 18, ?multiplexed external bus interface (mebiv3)? noacc refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pe6 ipipe1/modb refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pe5 ipipe0/moda refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pe4 eclk refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pe3 lstrb /taglo refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pe2 r/w refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pe1 irq refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pe0 xirq refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o table 3-1. detailed signal descriptions (sheet 2 of 7) port pin name pin function description pin function after reset chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 123 port k pk7 ecs /romone refer to chapter 18, ?multiplexed external bus interface (mebiv3)? refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pk6 xcs refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pk5 xaddr19 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pk4 xaddr18 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pk3 xaddr17 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pk2 xaddr16 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pk1 xaddr15 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o pk0 xaddr14 refer to chapter 18, ?multiplexed external bus interface (mebiv3)? gpio general-purpose i/o table 3-1. detailed signal descriptions (sheet 3 of 7) port pin name pin function description pin function after reset chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 124 freescale semiconductor port ad pad15 an15 analog-to-digital converter input channel 15 gpio kwad15 keyboard wake-up interrupt 15 gpio general-purpose i/o pad14 an14 analog-to-digital converter input channel 14 kwad14 keyboard wake-up interrupt 14 gpio general-purpose i/o pad13 an13 analog-to-digital converter input channel 13 kwad13 keyboard wake-up interrupt 13 gpio general-purpose i/o pad12 an12 analog-to-digital converter input channel 12 kwad12 keyboard wake-up interrupt 12 gpio general-purpose i/o pad11 an11 analog-to-digital converter input channel 11 kwad11 keyboard wake-up interrupt 11 gpio general-purpose i/o pad10 an10 analog-to-digital converter input channel 10 kwad10 keyboard wake-up interrupt 10 gpio general-purpose i/o pad9 an9 analog-to-digital converter input channel 9 kwad9 keyboard wake-up interrupt 9 gpio general-purpose i/o pad8 an8 analog-to-digital converter input channel 8 kwad8 keyboard wake-up interrupt 8 gpio general-purpose i/o pad7 an7 analog-to-digital converter input channel 7 kwad7 keyboard wake-up interrupt 7 gpio general-purpose i/o pad6 an6 analog-to-digital converter input channel 6 kwad6 keyboard wake-up interrupt 6 gpio general-purpose i/o pad5 an5 analog-to-digital converter input channel 5 kwad5 keyboard wake-up interrupt 5 gpio general-purpose i/o pad4 an4 analog-to-digital converter input channel 4 kwad4 keyboard wake-up interrupt 4 gpio general-purpose i/o pad3 an3 analog-to-digital converter input channel 3 kwad3 keyboard wake-up interrupt 3 gpio general-purpose i/o pad2 an2 analog-to-digital converter input channel 2 kwad2 keyboard wake-up interrupt 2 gpio general-purpose i/o pad1 an1 analog-to-digital converter input channel 1 kwad1 keyboard wake-up interrupt 1 gpio general-purpose i/o pad0 an0 analog-to-digital converter input channel 0 kwad0 keyboard wake-up interrupt 0 gpio general-purpose i/o table 3-1. detailed signal descriptions (sheet 4 of 7) port pin name pin function description pin function after reset chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 125 port m pm7 scl inter-integrated circuit serial clock line gpio gpio general-purpose i/o pm6 sda inter-integrated circuit serial data line gpio general-purpose i/o pm5 txd2 serial communication interface 2 transmit pin gpio general-purpose i/o pm4 rxd2 serial communication interface 2 receive pin gpio general-purpose i/o pm3 gpio general-purpose i/o pm1 dao1 digital to analog convertor 1 output gpio general-purpose i/o pm0 dao0 digital to analog convertor 0 output gpio general-purpose i/o port p pp5 pwm5 pulse-width modulator 0 channel 5 gpio gpio general-purpose i/o pp4 pwm4 pulse-width modulator 0 channel 4 gpio general-purpose i/o pp3 pwm3 pulse-width modulator 0 channel 3 gpio general-purpose i/o pp2 pwm2 pulse-width modulator 0 channel 2 gpio general-purpose i/o pp1 pwm1 pulse-width modulator 0 channel 1 gpio general-purpose i/o pp0 pwm0 pulse-width modulator 0 channel 0 gpio general-purpose i/o port q pq6 is2 pmf current status pin 2 gpio gpio general-purpose i/o pq5 is1 pmf current status pin 1 gpio general-purpose i/o pq4 is0 pmf current status pin 0 gpio general-purpose i/o pq3 fault3 pmf fault pin3 gpio general-purpose i/o pq2 fault2 pmf fault pin 2 gpio general-purpose i/o pq1 fault11 pmf fault pin 1 gpio general-purpose i/o pq0 fault0 pmf fault pin 0 gpio general-purpose i/o table 3-1. detailed signal descriptions (sheet 5 of 7) port pin name pin function description pin function after reset chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 126 freescale semiconductor port s ps7 ss serial peripheral interface slave select input/output in master mode, input in slave mode gpio gpio general-purpose i/o ps6 sck serial peripheral interface serial clock pin gpio general-purpose i/o ps5 mosi serial peripheral interface master out/slave in pin gpio general-purpose i/o ps4 miso serial peripheral interface master in/slave out pin gpio general-purpose i/o ps3 txd0 serial communication interface 1 transmit pin gpio general-purpose i/o ps2 rxd0 serial communication interface 1 receive pin gpio general-purpose i/o ps1 txd0 serial communication interface 0 transmit pin gpio general-purpose i/o ps0 rxd0 serial communication interface 0 receive pin gpio general-purpose i/o port t pt7 ioc7 timer 1 channel 7 gpio gpio general-purpose i/o pt6 ioc6 timer 1 channel 6 gpio general-purpose i/o pt5 ioc5 timer 1 channel 5 gpio general-purpose i/o pt4 ioc4 timer 1 channel 4 gpio general-purpose i/o pt3 ioc3 timer 0 channel 7 gpio general-purpose i/o pt2 ioc2 timer 0 channel 6 gpio general-purpose i/o pt1 ioc1 timer 0 channel 5 gpio general-purpose i/o pt0 ioc0 timer 0 channel 4 gpio general-purpose i/o table 3-1. detailed signal descriptions (sheet 6 of 7) port pin name pin function description pin function after reset chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 127 port u pu7 gpio general-purpose i/o gpio pu6 gpio general-purpose i/o pu5 pw15 pulse-width modulator 1 channel 5 gpio general-purpose i/o pu4 pw14 pulse-width modulator 1 channel 4 gpio general-purpose i/o pu3 ioc3 timer 2 channel 7 pw13 pulse-width modulator 1 channel 3 gpio general-purpose i/o pu2 ioc2 timer 2 channel 6 pw12 pulse-width modulator 1 channel 2 gpio general-purpose i/o pu1 ioc1 timer 2 channel 5 pw11 pulse-width modulator 1 channel 1 gpio general-purpose i/o pu0 ioc0 timer 2 channel 4 pw11 pulse-width modulator 1 channel 0 gpio general-purpose i/o table 3-1. detailed signal descriptions (sheet 7 of 7) port pin name pin function description pin function after reset chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 128 freescale semiconductor 3.3 memory map and register definition this section provides a detailed description of all registers. table 3-2 is a standard memory map of port integration module. table 3-2. pim9hz256 memory map address offset use access 0x0000 port t i/o register (ptt) r/w 0x0001 port t input register (ptit) r 0x0002 port t data direction register (ddrt) r/w 0x0003 port t reduced drive register (rdrt) r/w 0x0004 port t pull device enable register (pert) r/w 0x0005 port t polarity select register (ppst) r/w 0x0006 - 0x0007 reserved ? 0x0008 port s i/o register (pts) r/w 0x0009 port s input register (ptis) r 0x000a port s data direction register (ddrs) r/w 0x000b port s reduced drive register (rdrs) r/w 0x000c port s pull device enable register (pers) r/w 0x000d port s polarity select register (ppss) r/w 0x000e port s wired-or mode register (woms) r/w 0x000f reserved ? 0x0010 port m i/o register (ptm) r/w 0x0011 port m input register (ptim) r 0x0012 port m data direction register (ddrm) r/w 0x0013 port m reduced drive register (rdrm) r/w 0x0014 port m pull device enable register (perm) r/w 0x0015 port m polarity select register (ppsm) r/w 0x0016 port m wired-or mode register (womm) r/w 0x0017 reserved ? 0x0018 port p i/o register (ptp) r/w 0x0019 port p input register (ptip) r 0x001a port p data direction register (ddrp) r/w 0x001b port p reduced drive register (rdrp) r/w 0x001c port p pull device enable register (perp) r/w 0x001d port p polarity select register (ppsp) r/w 0x001e - 0x001f reserved ? chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 129 0x0020 port q i/o register (ptq) r/w 0x0021 port q input register (ptiq) r 0x0022 port q data direction register (ddrq) r/w 0x0023 port q reduced drive register (rdrq) r/w 0x0024 port q pull device enable register (perq) r/w 0x0025 port q polarity se lect register (ppsq) r/w 0x0026 - 0x0027 reserved ? 0x0028 port u i/o register (ptu) r/w 0x0029 port u input register (ptiu) r 0x002a port u data direction register (ddru) r/w 0x002b port u reduced drive register (rdru) r/w 0x002c port u pull device enable register (peru) r/w 0x002d port u polarity select register (ppsu) r/w 0x002e port u module routing register (modrr) r/w 0x002f reserved ? 0x0030 port ad i/o register (ptad) r/w 0x0031 0x0032 port ad input register (ptiad) r 0x0033 0x0034 port ad data direction register (ddrad) r/w 0x0035 0x0036 port ad reduced drive register (rdrad) r/w 0x0037 0x0038 port ad pull device enable register (perad) r/w 0x0039 0x003a port ad polarity select register (ppsad) r/w 0x003b 0x003d port ad interrupt enable register (piead) r/w 0x003d 0x003e port ad interrupt flag register (pifad) r/w 0x003f table 3-2. pim9hz256 memory map (continued) address offset use access chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 130 freescale semiconductor 3.3.1 port ad port ad is associated with the analog-to-dig ital converter (atd) a nd keyboard wake-up (kwu) interrupts. each pin is assigned to these modules according to the following priority: atd > kwu > general-purpose i/o. for the pins of port ad to be used as inputs, the corresponding bits of the atddien0 and atddien1 registers in the atd module must be set to 1 (d igital input buffer is en abled). the atddien0 and atddien1 registers do not affect the port ad pins when they are configured as outputs. refer to chapter 6, ?analog-to-digit al converter (atd10b16cv4)? for information on the atddien0 and atddien1 registers. during reset, port ad pins are configured as hi gh-impedance analog inputs (d igital input buffer is disabled). 3.3.1.1 port ad i/o register (ptad) read: anytime. write: anytime. if the data direction bit of the associated i/o pin (ddradx) is se t to 1 (output), a write to the corresponding i/o register bit sets the value to be driven to the po rt ad pin. if the data direction bit of the associated i/o pin (ddradx) is set to 0 (input), a wr ite to the corresponding i/o register bit takes place but has no effect on the port ad pin. if the associated data direction bit (ddradx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddradx) is se t to 0 (input) and the associated atddien0(1) bit is set to 0 (digital input buffer is disabled), the associated i/o register bit (ptadx) reads ?1?. if the associated data direction bit (ddradx) is se t to 0 (input) and the associated atddien0(1) bit is set to 1 (digital input buffer is enable d), a read returns the value of the pin. 76543210 r ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 w kwu: kwad15 kwad14 kwad13 kwa12 kwad11 kwad10 kwad9 kwad8 atd: an15 an14 an13 an12 an11 an10 an9 an8 reset00000000 76543210 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w kwu: kwad7 kwad6 kwad5 kwad4 kwad3 kwad2 kwad1 kwad0 atd: an7 an6 an5 an4 an3 an2 an1 an0 reset00000000 figure 3-2. port ad i/o register (ptad) chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 131 3.3.1.2 port ad input register (ptiad) read: anytime. write: never; writes to these registers have no effect. if the atddien0(1) bit of th e associated i/o pin is set to 0 (digital input buffer is disabled), a read returns a 1. if the atddien0(1) bit of the a ssociated i/o pin is set to 1 (digit al input buffer is enabled), a read returns the status of the associated pin. 3.3.1.3 port ad data direction register (ddrad) read: anytime. write: anytime. this register configures port pins pad[15:0] as either input or output. if a data direction bit is 0 (pin configured as input), then a read value on ptadx depends on the associated atddien0(1) bit. if the associated at ddien0(1) bit is set to 1 (digital input buffer is enabled), a read on ptadx returns the value on port ad pin. if the associ ated atddien0(1) bit is set to 0 (digital input buffer is disabled), a r ead on ptadx returns a 1. 76543210 r ptiad15 ptiad14 ptiad13 ptiad1 2 ptiad11 ptiad10 ptiad9 ptiad8 w reset11111111 76543210 r ptiad7 ptiad6 ptiad5 ptiad4 p tiad3 ptiad2 ptiad1 ptiad0 w reset11111111 = reserved or unimplemented figure 3-3. port ad input register (ptiad) 76543210 r ddrad15 ddrad14 ddrad13 ddrad12 ddrad11 ddrad10 ddrad9 ddrad8 w reset00000000 76543210 r ddrad7 ddrad6 ddrad5 ddrad4 ddrad3 ddrad2 ddrad1 ddrad0 w reset00000000 figure 3-4. port ad data direction register (ddrad) table 3-3. ddrad field descriptions field description 15:0 ddrad[15:0] data direction port ad 0 associated pin is configured as input. 1 associated pin is configured as output. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 132 freescale semiconductor 3.3.1.4 port ad reduced drive register (rdrad) read: anytime. write: anytime. this register configures the drive st rength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduc ed drive register bit has no effect. 3.3.1.5 port ad pull device enable register (perad) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down devi ce is activated on conf igured input pins. if a pin is configured as output, the corresponding pu ll device enable register bit has no effect. 76543210 r rdrad15 rdrad14 rdrad13 rdrad12 rdrad11 rdrad10 rdrad9 rdrad8 w reset00000000 76543210 r rdrad7 rdrad6 rdrad5 rdrad4 rdrad3 rdrad2 rdrad1 rdrad0 w reset00000000 figure 3-5. port ad reduced drive register (rdrad) table 3-4. rdrad field descriptions field description 15:0 rdrad[15:0] reduced drive port ad 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. 76543210 r perad15 perad14 perad13 perad12 perad11 perad10 perad9 perad8 w reset00000000 76543210 r perad7 perad6 perad5 perad4 perad3 perad2 perad1 perad0 w reset00000000 figure 3-6. port ad pull device enable register (perad) table 3-5. perad field descriptions field description 15:0 perad[15:0] pull device enable port ad 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 133 3.3.1.6 port ad polarity select register (ppsad) read: anytime. write: anytime. the port ad polarity select regist er serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull- up or pull-down device if enabled (p eradx = 1). the port ad polarity select register is effective only when the corresponding data direction register bit is set to 0 (input). in pull-down mode (ppsadx = 1), a rising edge on a por t ad pin sets the corresponding pifadx bit. in pull-up mode (ppsadx = 0), a falling edge on a port ad pin sets the corresponding pifadx bit. 76543210 r ppsad15 ppsad14 ppsad13 ppsad12 ppsad11 ppsad10 ppsad9 ppsad8 w reset00000000 76543210 r ppsad7 ppsad6 ppsad5 ppsad4 ppsad3 ppsad2 ppsad1 ppsad0 w reset00000000 figure 3-7. port ad polari ty select register (ppsad) table 3-6. ppsad field descriptions field description 15:0 ppsad[15:0] polarity select port ad 0 a pull-up device is connected to the associated port ad pin, and detects falling edge for interrupt generation. 1 a pull-down device is connected to the associated port ad pin, and detects rising edge for interrupt generation. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 134 freescale semiconductor 3.3.1.7 port ad interrupt enable register (piead) read: anytime. write: anytime. this register disables or enables on a per pin basis th e edge sensitive external interrupt associated with port ad. 76543210 r piead15 piead14 piead13 piead12 p iead11 piead10 piead9 piead8 w reset00000000 76543210 r piead7 piead6 piead5 piead4 p iead3 piead2 piead1 piead0 w reset00000000 figure 3-8. port ad interrupt enable register (piead) table 3-7. piead field descriptions field description 15:0 piead[15:0] interrupt enable port ad 0 interrupt is disabled (interrupt flag masked). 1 interrupt is enabled. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 135 3.3.1.8 port ad interrupt flag register (pifad) read: anytime. write: anytime. each flag is set by an active edge on the associated input pin. the active edge could be rising or falling based on the state of the corresponding ppsadx bit. to clear each flag, write ?1? to the corresponding pifadx bit. writing a ?0? has no effect. note if the atddien0(1) bit of the associated pin is set to 0 (digital input buffer is disabled), active edges can not be detected. 76543210 r pifad15 pifad14 pifad13 pifad12 pifad11 pifad10 pifad9 pifad8 w reset00000000 76543210 r pifad7 pifad6 pifad5 pifad4 pifad3 pifad2 pifad1 pifad0 w reset00000000 figure 3-9. port ad interrupt flag register (pifad) table 3-8. pifad field descriptions field description 15:0 pifad[15:0] interrupt flags port ad 0 no active edge pending. writing a ?0? has no effect. 1 active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). writing a ?1? clears the associated flag. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 136 freescale semiconductor 3.3.2 port m port m is associated with the serial communication in terface (sci2) , inter-ic bus (iic) and the digital to analog converter (dac0 and dac1) modules. each pin is assigned to these modules according to the following priority: iic/sci2/da c1/dac0 > general-purpose i/o. when the iic bus is enabled, the pm[7:6] pins become scl and sda respectively. refer to chapter 10, ?inter-integrated circuit (iicv2)? for information on enabling and disabling the iic bus. when the sci2 receiver and transmitter are enabled, the pm[5:4] become rxd2 and txd2 respectively. refer to chapter 8, ?serial communi cation interface (sciv4)? for information on en abling and disabling the sci receiver and transmitter. when the dac1 and dac0 outputs are enabled, th e pm[1:0] become dao1 and dao0 respectively. refer to chapter 7, ?digital-to-anal og converter (dac8b1cv1)? for information on enabling and disabling the dac output. during reset, pm[3] and pm[1:0] pins are configured as high-impedance inputs and pm[7:4] pins are configured as pull-up inputs. 3.3.2.1 port m i/o register (ptm) read: anytime. write: anytime. if the associated data dir ection bit (ddrmx) is set to 1 (output), a read returns th e value of the i/o register bit. if the associated data direction bit (ddrmx) is set to 0 (input), a read returns the value of the pin. 76543210 r ptm7 ptm6 ptm5 ptm4 ptm3 0 ptm1 ptm0 w iic: scl sda sci2: txd2 rxd2 dac1/dac0: dao1 dao0 reset00000000 = reserved or unimplemented figure 3-10. port m i/o register (ptm) chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 137 3.3.2.2 port m input register (ptim) read: anytime. write: never, writes to this register have no effect. this register always reads back th e status of the associated pins. 3.3.2.3 port m data direction register (ddrm) read: anytime. write: anytime. this register configures port pins pm[7:3 ] and pm[1:0] as either input or output. if the iic is enabled, the iic controls the scl and sda i/o direction, and the corresponding ddrm[7:6] bits have no effect on their i/o direction. refer to chapter 10, ?inter-integrated circuit (iicv2)? for details. if the sci2 transmitter is enabled, the i/o direction of the transmit pin txd2 is controlled by sci2, and the ddrm5 bit has no effect. if the sc i2 receiver is enabled, the i/o di rection of the rece ive pin rxd2 is controlled by sci2, and the ddrm 4 bit has no effect. refer to chapter 8, ?serial communication interface (sciv4)? for further details. if the dac1 or dac0 channel is enab led, the associated pin dao1 or dao0 is forced to be output, and the associated ddrm1 or ddrm0 bit has no effect. the ddrm bits do not change to reflect the pin i/ o direction when not being used as gpio. the ddrm[7:3]; ddrm[1:0] bits re vert to controlling the i/o direction of the pins when the associated iic, sci, or dac1/0 function are disabled. 76543210 r ptim7 ptim6 ptim5 ptim4 ptim3 0 ptim1 ptim0 w resetuuuuu0uu = reserved or unimplemented u = unaffected by reset figure 3-11. port m input register (ptim) 76543210 r ddrm7 ddrm6 ddrm5 ddrm4 ddrm3 0 ddrm1 ddrm0 w reset00000000 = reserved or unimplemented figure 3-12. port m data direction register (ddrm) table 3-9. ddrm field descriptions field description 7:3, 1:0 ddrm[7:3, 1:0] data direction port m 0 associated pin is configured as input. 1 associated pin is configured as output. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 138 freescale semiconductor 3.3.2.4 port m reduced drive register (rdrm) read: anytime. write: anytime. this register configures the drive st rength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduc ed drive register bit has no effect. 3.3.2.5 port m pull device enable register (perm) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input or wired-or output pins. if a pin is configured as push-pull output, the correspondi ng pull device enable register bit has no effect. 76543210 r rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 0 rdrm1 rdrm0 w reset00000000 = reserved or unimplemented figure 3-13. port m reduced drive register (rdrm) table 3-10. rdrm field descriptions field description 7:3, 1:0 rdrm[7:3, 1:0] reduced drive port m 0 full drive strength at output 1 associated pin drives at about 1/3 of the full drive strength. 76543210 r perm7 perm6 perm5 perm4 perm3 0 perm1 perm0 w reset00000000 = reserved or unimplemented figure 3-14. port m pull device enable register (perm) table 3-11. perm field descriptions field description 7:3, 1:0 perm[7:3, 1:0] pull device enable port m 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 139 3.3.2.6 port m polarity select register (ppsm) read: anytime. write: anytime. the port m polarity select regist er selects whether a pull-down or a pull-up device is connected to the pin. the port m polarity select re gister is effective only when the corresponding data di rection register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 76543210 r ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 0 ppsm1 ppsm0 w reset00000000 = reserved or unimplemented figure 3-15. port m polarity select register (ppsm) table 3-12. ppsm field descriptions field description 7:3, 1:0 ppsm[7:3, 1:0] pull select port m 0 a pull-up device is connected to the associated port m pin. 1 a pull-down device is connected to the associated port m pin. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 140 freescale semiconductor 3.3.2.7 port m wired-or mode register (womm) read: anytime. write: anytime. this register selects whether a por t m output is configured as push-pull or wired- or. when a wired-or mode register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. a wired-or mode register bit has no effect if the corresponding pin is configured as an input. these bits apply also to the sci2 outputs and allow a multi point connection of se veral serial modules. if the iic is enabled, the associated pins are al ways set to wired-or m ode, and the state of the womm[7:6] bits have no effect. the womm[7:6] bits will not change to reflect their wired-or mode configuration when the iic is enabled. 76543210 r womm7 womm6 womm5 womm4 0000 w reset00000000 = reserved or unimplemented figure 3-16. port m wired-or mode register (womm) table 3-13. womm field descriptions field description 7:4 womm[7:4] wired-or mode port m 0 output buffers operate as push-pull outputs. 1 output buffers operate as open-drain outputs. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 141 3.3.3 port p port p is associated with the pu lse width modulator (pmf) modules. e ach pin is assigned according to the following priority: pmf > general-purpose i/o. when a pmf channel is enabled, the corre sponding pin becomes a pwm output. refer to chapter 11, ?pulse width modulator with fault protection (pmf15b6cv2)? for information on enabling and disabling the pwm channels. during reset, port p pins are conf igured as high-impedance inputs. 3.3.3.1 port p i/o register (ptp) read: anytime. write: anytime. if the associated data direction bit (ddrpx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data directi on bit (ddrpx) is set to 0 (input), a read returns the value of the pin. the pmf function takes precedence over the general-purpose i/o function if the as sociated pwm channel is enabled. the pwm channels 5-0 are output s if the respective channels are enabled. 3.3.3.2 port p input register (ptip) read: anytime. write: never, writes to this register have no effect. this register always reads back th e status of the associated pins. 76543210 r0 0 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w pmf: pw05 pw04 pw03 pw02 pw01 pw00 reset00000000 = reserved or unimplemented figure 3-17. port p i/o register (ptp) 76543210 r 0 0 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w reset00uuuuuu = reserved or unimplemented u = unaffected by reset figure 3-18. port p input register (ptip) chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 142 freescale semiconductor 3.3.3.3 port p data direction register (ddrp) read: anytime. write: anytime. this register configures port pins pp[5:0] as either input or output. if a pmf channel is enabled, the corresponding pin is forced to be an output and the associated data direction register bit has no effect. if a pmf ch annel is disabled, the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 3.3.3.4 port p reduced drive register (rdrp) read:anytime. write:anytime. this register configures the drive st rength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduc ed drive register bit has no effect. 76543210 r0 0 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w reset00000000 = reserved or unimplemented figure 3-19. port p data direction register (ddrp) table 3-14. ddrp field descriptions field description 5:0 ddrp[5:0] data direction port p 0 associated pin is configured as input. 1 associated pin is configured as output. 76543210 r0 0 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 w reset00000000 = reserved or unimplemented figure 3-20. port p reduced drive register (rdrp) table 3-15. rdrp field descriptions field description 5:0 rdrp[5:0] reduced drive port p 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 143 3.3.3.5 port p pull device enable register (perp) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down devi ce is activated on conf igured input pins. if a pin is configured as output, the corresponding pu ll device enable register bit has no effect. 3.3.3.6 port p polarity select register (ppsp) read: anytime. write: anytime. the port p polarity select register selects wh ether a pull-down or a pull-up device is connected to the pin. the port p polarity select register is effective only when the corres ponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 76543210 r0 0 perp5 perp4 perp3 perp2 perp1 perp0 w reset00000000 = reserved or unimplemented figure 3-21. port p pull devi ce enable register (perp) table 3-16. perp field descriptions field description 5:0 perp[5:0] pull device enable port p 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 76543210 r0 0 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppsp0 w reset00000000 = reserved or unimplemented figure 3-22. port p polari ty select register (ppsp) table 3-17. ppsp field descriptions field description 5:0 ppsp[5:0] polarity select port p 0 a pull-up device is connected to the associated port p pin. 1 a pull-down device is connected to the associated port p pin. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 144 freescale semiconductor 3.3.4 port q port q is associated with the pulse width modulator (pmf) modules. each pin is assigned according to the following priority: pmf > general-purpose i/o. when a current status or fault function is enable d, the corresponding pin becomes an input. pq[3:0] are connected to fault[3:0] inputs and pq[6:4] are connected to is [2:0] inputs of the pmf module. refer to chapter 11, ?pulse width modulator with fault protection (pmf15b6cv2)? for information on enabling and disabling these pmf functions. during reset, port q pins are conf igured as high-impedance inputs. 3.3.4.1 port q i/o register (ptq) read: anytime. write: anytime. if the associated data dir ection bit (ddrqx) is set to 1 (output), a read returns th e value of the i/o register bit. if the associated data direction bit (ddrqx) is set to 0 (input), a read returns the value of the pin. 3.3.4.2 port q input register (ptiq) read: anytime. write: never, writes to this register have no effect. this register always reads back th e status of the associated pins. 76543210 r0 ptq5 ptq5 ptq4 ptq3 ptq2 ptq1 ptq0 w pmf: is2 is1 is0 fault3 fault2 fault1 fault0 reset00000000 = reserved or unimplemented figure 3-23. port q i/o register (ptq) 76543210 r 0 ptiq6 ptiq5 ptiq4 ptiq3 ptiq2 ptiq1 ptiq0 w reset0uuuuuuu = reserved or unimplemented u = unaffected by reset figure 3-24. port q input register (ptiq) chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 145 3.3.4.3 port q data direction register (ddrq) read: anytime. write: anytime. this register configures port pins pq[6:0] as either input or output. if a pmf function is enabled, the corresponding pin is forced to be an input and the associated data direction register bit has no effect. if a pmf ch annel is disabled, the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 3.3.4.4 port q reduced drive register (rdrq) read:anytime. write:anytime. this register configures the drive st rength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduc ed drive register bit has no effect. 76543210 r0 ddrq6 ddrq5 ddrq4 ddrq3 ddrq2 ddrq1 ddrq0 w reset00000000 = reserved or unimplemented figure 3-25. port q data direction register (ddrq) table 3-18. ddrq field descriptions field description 6:0 ddrq[6:0] data direction port q 0 associated pin is configured as input. 1 associated pin is configured as output. 76543210 r0 rdrq6 rdrq5 rdrq4 rdrq3 rdrq2 rdrq1 rdrq0 w reset00000000 = reserved or unimplemented figure 3-26. port q reduced drive register (rdrq) table 3-19. rdrq field descriptions field description 6:0 rdrq[6:0] reduced drive port q 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 146 freescale semiconductor 3.3.4.5 port q pull device enable register (perq) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down devi ce is activated on conf igured input pins. if a pin is configured as output, the corresponding pu ll device enable register bit has no effect. 3.3.4.6 port q polarity select register (ppsq) read: anytime. write: anytime. the port q polarity select register selects whether a pull-do wn or a pull-up device is connected to the pin. the port q polarity select regist er is effective only when the corr esponding data direct ion register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 76543210 r0 perq6 perq5 perq4 perq3 perq2 perq1 perq0 w reset00000000 = reserved or unimplemented figure 3-27. port q pull device enable register (perq) table 3-20. perq field descriptions field description 6:0 perq[6:0] pull device enable port p 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 76543210 r0 ppsq6 ppsq5 ppsq4 ppsq3 ppsq2 ppsq1 ppsq0 w reset00000000 = reserved or unimplemented figure 3-28. port q polarity select register (ppsq) table 3-21. ppsq field descriptions field description 6:0 ppsq[6:0] polarity select port q 0 a pull-up device is connected to the associated port q pin. 1 a pull-down device is connected to the associated port q pin. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 147 3.3.5 port s port s is associated with the se rial peripheral interface (spi) and serial communication interfaces (sci0 and sci1). each pin is assigned to these modules according to the following priority: spi/sci1/sci0 > general-purpose i/o. when the spi is enabled, the ps[7:4] pins become ss , sck, mosi, and miso respectively. refer to chapter 9, ?serial peripheral interface (spiv3)? for information on enabling and disabling the spi. when the sci1 receiver and transmitter are enab led, the ps[3:2] pins become txd1 and rxd1 respectively. when the sci0 receiver and transmit ter are enabled, the ps[1:0] pins become txd0 and rxd0 respectively. refer to chapter 8, ?serial communication interface (sciv4)? for information on enabling and disabling the sc i receiver and transmitter. during reset, port s pins are conf igured as high-impedance inputs. 3.3.5.1 port s i/o register (pts) read: anytime. write: anytime. if the associated data direction bit (ddrsx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data directi on bit (ddrsx) is set to 0 (input), a read returns the value of the pin. 3.3.5.2 port s input register (ptis) read: anytime. write: never, writes to this register have no effect. this register always reads back th e status of the associated pins. 76543210 r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w spi: ss sck mosi miso sci1/sci0: txd1 rxd1 txd0 rxd0 reset00000000 figure 3-29. port s i/o register (pts) 76543210 r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w resetuuuuuuuu = reserved or unimplemented u = unaffected by reset figure 3-30. port s input register (ptis) chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 148 freescale semiconductor 3.3.5.3 port s data direction register (ddrs) read: anytime. write: anytime. this register configures por t pins ps[7:4] and ps[2:0] as either input or output. when the spi is enabled, the ps[7:4] pins become the spi bidirectional pins. the associated data direction register bi ts have no effect. when the sci1 transmitter is enab led, the ps[3] pin become s the txd1 output pin a nd the associated data direction register bit has no effect . when the sci1 receiver is enab led, the ps[2] pin becomes the rxd1 input pin and the associated data di rection register bit has no effect. when the sci0 transmitter is enab led, the ps[1] pin become s the txd0 output pin a nd the associated data direction register bit has no effect . when the sci0 receiver is enab led, the ps[0] pin becomes the rxd0 input pin and the associated data di rection register bit has no effect. if the spi, sci1 and sci0 functions are disabled, the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 76543210 r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w reset00000000 figure 3-31. port s data direction register (ddrs) table 3-22. ddrs field descriptions field description 7:0 ddrs[7:0] data direction port s 0 associated pin is configured as input. 1 associated pin is configured as output. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 149 3.3.5.4 port s reduced drive register (rdrs) read: anytime. write: anytime. this register configures the drive st rength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduc ed drive register bit has no effect. 3.3.5.5 port s pull device enable register (pers) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input or wired-or (open drain) output pins . if a pin is configured as pus h-pull output, the corresponding pull device enable register bit has no effect. 76543210 r rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 w reset00000000 figure 3-32. port s reduced drive register (rdrs) table 3-23. rdrs field descriptions field description 7:0 rdrs[7:0] reduced drive port s 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. 76543210 r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w reset11111111 figure 3-33. port s pull devi ce enable register (pers) table 3-24. pers field descriptions field description 7:0 pers[7:0] pull device enable port s 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 150 freescale semiconductor 3.3.5.6 port s polarity select register (ppss) read: anytime. write: anytime. the port s polarity select register selects wh ether a pull-down or a pull-up device is connected to the pin. the port s polarity select register is effective only when the corres ponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 3.3.5.7 port s wired-or mode register (woms) read: anytime. write: anytime. this register selects whether a por t s output is configured as push-pul l or wired-or. when a wired-or mode register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. a wired-or mode register bit has no effect if the corresponding pin is configured as an input. 76543210 r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w reset00000000 figure 3-34. port s polari ty select register (ppss) table 3-25. ppss field descriptions field description 7:0 ppss[7:0] pull select port s 0 a pull-up device is connected to the associated port s pin. 1 a pull-down device is connected to the associated port s pin. 76543210 r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w reset00000000 figure 3-35. port s wired-or mode register (woms) table 3-26. woms field descriptions field description 7:0 woms[7:0] wired-or mode port s 0 output buffers operate as push-pull outputs. 1 output buffers operate as open-drain outputs. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 151 3.3.6 port t port t is associated with two 4-channel timers (tim 0 and tim1). each pin is assigned to these modules according to the following priori ty: tim1/tim0 > general-purpose i/o. if the timer tim0 is enabled, the channels confi gured for output compare ar e available on port t pins pt[3:0]. if the timer tim1 is enab led, the channels configured for out put compare are available on port t pins pt[7:4]. refer to chapter 13, ?timer module (tim16b4cv1)? for information on enablin g and disabling the tim module. during reset, port t pins are conf igured as high-impedance inputs. 3.3.6.1 port t i/o register (ptt) read: anytime. write: anytime. if the associated data direction bit (ddrtx) is set to 1 (output), a read returns th e value of the i/o register bit. if the associated data directi on bit (ddrtx) is set to 0 (input), a read returns the value of the pin. 3.3.6.2 port t input register (ptit) read: anytime. write: never, writes to this register have no effect. this register always reads back th e status of the associated pins. 76543210 r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w tim: oc17 oc16 oc15 oc14 oc07 oc06 oc05 oc04 reset00000000 figure 3-36. port t i/o register (ptt) 76543210 r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w resetuuuuuuuu = reserved or unimplemented u = unaffected by reset figure 3-37. port t input register (ptit) chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 152 freescale semiconductor 3.3.6.3 port t data direction register (ddrt) read: anytime. write: anytime. this register configures port pins pt[7:0] as either input or output. if the tim0(1) module is enabled, each port pin configur ed for output compare is forced to be an output and the associated data direction register bit has no effect. if the associated timer output compare is disabled, the corresponding ddrtx bi t reverts to control the i/o di rection of the associated pin. if the tim0(1) module is enabled, each port pin conf igured as an input capt ure has the corresponding ddrtx bit controlling the i/o di rection of the associated pin. 3.3.6.4 port t reduced drive register (rdrt) read: anytime. write: anytime. this register configures the drive st rength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduc ed drive register bit has no effect. 76543210 r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w reset00000000 figure 3-38. port t data direction register (ddrt) table 3-27. ddrt field descriptions field description 7:0 ddrt[7:0] data direction port t 0 associated pin is configured as input. 1 associated pin is configured as output. 76543210 r rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 w reset00000000 figure 3-39. port t reduced drive register (rdrt) table 3-28. rdrt field descriptions field description 7:0 rdrt[7:0] reduced drive port t 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 153 3.3.6.5 port t pull device enable register (pert) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down devi ce is activated on conf igured input pins. if a pin is configured as output, the corresponding pu ll device enable register bit has no effect. 3.3.6.6 port t polarity select register (ppst) read: anytime. write: anytime. the port t polarity select register selects whether a pull-down or a pul l-up device is connected to the pin. the port t polarity select register is effective only when the corres ponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 76543210 r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w reset00000000 figure 3-40. port t pull device enable register (pert) table 3-29. pert field descriptions field description 7:0 pert[7:0] pull device enable port t 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 76543210 r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w reset00000000 figure 3-41. port t polarity select register (ppst) table 3-30. ppst field descriptions field description 7:0 ppst[7:0] pull select port t 0 a pull-up device is connected to the associated port t pin. 1 a pull-down device is connected to the associated port t pin. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 154 freescale semiconductor 3.3.7 port u port u is associated with one 4- channel timer (tim2) and the pulse width modulator (pwm) module. each pin is assigned to these modules according to the following pr iority: tim2/pwm > general-purpose i/o. if the timer tim2 is enabled, the channels confi gured for output compare ar e available on port u pins pu[3:0]. refer to chapter 13, ?timer module (tim16b4cv1)? for information on enabling and disabling the tim module. when a pwm channel is enabled, the corres ponding pin becomes a pwm output. refer to chapter 3, ?port integration module (pim9e256v1)? for information on enabling a nd disabling the pwm channels. if both pwm and tim2 are enabled simultaneousl y, the pin functionality is determined by the configuration of the modrr bits during reset, port u pins are conf igured as high-impedance inputs. 3.3.7.1 port u i/o register (ptu) read: anytime. write: anytime. if the associated data dir ection bit (ddrux) is set to 1 (output), a read returns th e value of the i/o register bit. if the associated data direction bit (ddrux) is set to 0 (input), a read returns the value of the pin. 3.3.7.2 port u input register (ptiu) read: anytime. write: never, writes to this register have no effect. this register always reads back th e status of the associated pins. 76543210 r ptu7 ptu6 ptu5 ptu4 ptu3 ptu2 ptu1 ptu0 w pwm: pw15 pw14 pw13 pw12 pw11 pw10 tim2: oc27 oc26 oc25 oc24 reset00000000 figure 3-42. port u i/o register (ptu) 76543210 r ptiu7 ptiu6 ptiu5 ptiu4 ptiu3 ptiu2 ptiu1 ptiu0 w resetuuuuuuuu = reserved or unimplemented u = unaffected by reset figure 3-43. port u input register (ptiu) chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 155 3.3.7.3 port u data direction register (ddru) read: anytime. write: anytime. this register configures port pins pu[7:0] as either input or output. if a pulse width modulator channel is enabled, the a ssociated pin is forced to be an output and the associated data direction register bit has no effect. if th e associated pulse width modulator channel is disabled, the corresponding ddrux bit reverts to c ontrol the i/o direction of the associated pin. if the tim2 module is enabled, each port pin configured for output compar e is forced to be an output and the associated data direction register bit has no effect. if th e associated timer output compare is disabled, the corresponding ddrux bit reverts to control the i/o direction of the associated pin. if the tim2 module is enabled, each port pin confi gured as an input captur e has the corresponding ddrux bit controlling the i/o direc tion of the associated pin. when both a timer function and a pwm function ar e enabled on the same pin, the modrr register determines which function has control of the pin 76543210 r ddru7 ddru6 ddru5 ddru4 ddru3 ddru2 ddru1 ddru0 w reset00000000 figure 3-44. port u data direction register (ddru) table 3-31. ddru field descriptions field description 7:0 ddru[7:0] data direction port u 0 associated pin is configured as input. 1 associated pin is configured as output. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 156 freescale semiconductor 3.3.7.4 port u reduced drive register (rdru) read: anytime. write: anytime. this register configures the drive st rength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduc ed drive register bit has no effect. 3.3.7.5 port u pull device enable register (peru) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down devi ce is activated on conf igured input pins. if a pin is configured as output, the corresponding pu ll device enable register bit has no effect. 76543210 r rdru7 rdru6 rdru5 rdru4 rdru3 rdru2 rdru1 rdru0 w reset00000000 figure 3-45. port u reduced drive register (rdru) table 3-32. rdru field descriptions field description 7:0 rdru[7:0] reduced drive port u 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. 76543210 r peru7 peru6 peru5 peru4 peru3 peru2 peru1 peru0 w reset00000000 figure 3-46. port u pull device enable register (peru) table 3-33. peru field descriptions field description 7:0 peru[7:0] pull device enable port u 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 157 3.3.7.6 port u polarity select register (ppsu) read: anytime. write: anytime. the port u polarity select register selects whether a pull-do wn or a pull-up device is connected to the pin. the port u polarity select regist er is effective only when the corr esponding data direct ion register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 3.3.7.7 port u module routing register (modrr) read: anytime. write: anytime. this register selects the module connected to port u. 76543210 r ppsu7 ppsu6 ppsu5 ppsu4 ppsu3 ppsu2 ppsu1 ppsu0 w reset00000000 figure 3-47. port u polarity select register (ppsu) table 3-34. ppsu fi eld descriptions field description 7:0 ppsu[7:0] pull select port u 0 a pull-up device is connected to the associated port t pin. 1 a pull-down device is connected to the associated port t pin. 76543210 r0 0 0 0 modrr3 modrr2 modrr1 modrr0 w reset00000000 = reserved or unimplemented figure 3-48. port u module routing register (modrr) table 3-35. modrr field descriptions field description 3:0 modrr[3:0] pull select port u 0 if enabled, tim2 channel is connected to the associated port u pin. 1 if enabled, pwm channel is connected to the associated port u pin. chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 158 freescale semiconductor 3.4 functional description each pin associated with ports ad, m, p, q, s, t and u can act as ge neral-purpose i/o. in addition the pin can act as an output from a peripheral module or an i nput to a peripheral module. a set of configuration registers is common to all ports. all registers can be written at any time, however a specific configuration might not become active. example: selecting a pull-up resist or. this resistor does not beco me active while the port is used as a push-pull output. 3.4.1 i/o register the i/o register holds the va lue driven out to th e pin if the port is used as a general-purpose i/o. writing to the i/o register only has an effect on the pin if the port is used as general-purpose output. when reading the i/o register, th e value of each pin is returned if the corresponding data direction register bit is set to 0 (pin configured as input). if the data direction register bits is set to 1, the content of the i/o register bit is returned. this is independent of any other configuration ( figure 3-49 ). due to internal synchronization circui ts, it can take up to 2 bus cycles until the correct value is read on the i/o register when changing th e data direction register. 3.4.2 input register the input register is a read-only register and generally returns the value of the pin ( figure 3-49 ). it can be used to detect overload or short circuit conditions. due to internal synchronization circui ts, it can take up to 2 bus cycles until the correct value is read on the input register when changing the data direction register. 3.4.3 data direction register the data direction register defines whether the pin is used as an input or an output. a data direction register bit set to 0 confi gures the pin as an input. a data direction register bit set to 0 configures the pin as an output. if a peripheral module controls the pin th e contents of the data dire ction register is ignored ( figure 3-49 ). chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 159 figure 3-49. illustration of i/o pin functionality figure 3-50 shows the state of di gital inputs and outputs wh en an analog module driv es the port. when the analog module is enabled all associated digital output ports are disabled and all associated digital input ports read ?1?. figure 3-50. digital po rts and analog module 3.4.4 reduced drive register if the port is used as an output th e reduced drive register allows the configuration of the drive strength. 3.4.5 pull device enable register the pull device enable register turns on a pull-up or pull-down device. the pul l device becomes active only if the pin is used as an input or as a wired-or output. ptx ddrx output enable module enable 1 0 1 1 0 0 pad ptix data out digital module analog module 1 0 1 pad digital input digital output 1 0 analog module enable output pim boundary chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 160 freescale semiconductor 3.4.6 polarity select register the polarity select register se lects either a pull-up or pull-down device if enabled. the pull device becomes active only if the pin is used as an input or as a wired-or output. 3.4.7 pin configuration summary the following table summarizes th e effect of various configurati on in the data direction (ddr), input/output (i/o), reduced drive (rdr), pull enable (pe), pull select (ps) and interrupt enable (ie) register bits. the ps configurati on bit is used for two purposes: 1. configure the sensitive interrupt edge (ris ing or falling), if interrupt is enabled. 2. select either a pull-up or pull- down device if pe is set to ?1?. table 3-36. pin configuration summary ddr io rdr pe ps ie 1 1 applicable only on port ad. function 2 2 digital outputs are disabled and digital input logic is forced to ?1? when an analog module associated with the port is enabled . pull device interrupt 0 x x 0 x 0 input disabled disabled 0 x x 1 0 0 input pull up disabled 0 x x 1 1 0 input pull down disabled 0 x x 0 0 1 input disabled falling edge 0 x x 0 1 1 input disabled rising edge 0 x x 1 0 1 input pull up falling edge 0 x x 1 1 1 input pull down rising edge 1 0 0 x x 0 output to 0, full drive disabled disabled 1 1 0 x x 0 output to 1, full drive disabled disabled 1 0 1 x x 0 output to 0, reduced drive disabled disabled 1 1 1 x x 0 output to 1, reduced drive disabled disabled 1 0 0 x 0 1 output to 0, full drive disabled falling edge 1 1 0 x 1 1 output to 1, full drive disabled rising edge 1 0 1 x 0 1 output to 0, reduced drive disabled falling edge 1 1 1 x 1 1 output to 1, reduced drive disabled rising edge chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 161 3.5 resets the reset values of all registers are given in the register description in section 3.3, ?memory map and register definition? . all ports start up as gene ral-purpose inputs on reset. 3.5.1 reset initialization all registers including the data re gisters get set/reset asynchronously. table 3-37 summarizes the port properties after reset initialization. p table 3-37. port reset state summary port reset states data direction pull mode red. drive wired-or mode interrupt a refer to chapter 18, ?multiplexed external bus interface (mebiv3)? pull up refer to chapter 18, ?multiplexed external bus interface (mebiv3)? b e k bkgd pin ad input hi-z disabled n/a disabled m[7:4] input pull up disabled disabled n/a m[3,1:0] input hi-z disabled disabled n/a p input hi-z disabled n/a n/a q input hi-z disabled n/a n/a s input pull up disabled disabled n/a t input hi-z disabled n/a n/a u input hi-z disabled n/a n/a chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 162 freescale semiconductor 3.6 interrupts 3.6.1 general port ad generates an edge sensitiv e interrupt if enabled. it offers si xteen i/o pins with edge triggered interrupt capability in wired-or fashi on. the interrupt enable as well as the sensitivity to rising or falling edges can be individually c onfigured on per pin basis. all eight bits/pins share th e same interrupt vector. interrupts can be used with the pi ns configured as input s (with the corresponding at ddien1 bit set to 1) or outputs. an interrupt is generated when a bi t in the port interrupt flag regist er and its corres ponding port interrupt enable bit are both set. this external interrupt feature is ca pable to wake up the cpu when it is in stop or wait mode. a digital filter on each pin prevents pulses ( figure 3-52 ) shorter than a specified time from generating an interrupt. the minimum time varies over pr ocess conditions, temperature and voltage ( figure 3-51 and table 3-38 ). figure 3-51. interrupt glitch filter on port ad (pps = 0) table 3-38. pulse detection criteria pulse mode stop stop 1 1 these values include the spread of the o scillator frequency over temperature, voltage and process. unit unit ignored t pulse <= 3 bus clock t pulse <= 3.2 s uncertain 3 < t pulse < 4 bus clock 3.2 < t pulse < 10 s valid t pulse >= 4 bus clock t pulse >= 10 s glitch, filtered out, no interrupt flag set valid pulse, interrupt flag set t ifmin t ifmax chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 163 figure 3-52. pulse illustration a valid edge on an input is detected if 4 consec utive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly the filters are continuously clocked by the bus clock in run and wait mode. in stop mode the clock is generated by a single rc oscillator in the port integration module. to max imize current saving the rc oscillator runs only if the foll owing condition is true on any pin: sample count <= 4 and port interrupt enabled (p ie=1) and port interrupt flag not set (pif=0). 3.6.2 interrupt sources note vector addresses and their relative inte rrupt priority are determined at the mcu level. 3.6.3 operation in stop mode all clocks are stoppe d in stop mode. the port integration module has asynchronous paths on port ad to generate wake-up interrupts from stop mode. for other sources of external interrupts refer to the respective block description chapters. table 3-39. port integration module interrupt sources interrupt source interrupt flag local enable global (ccr) mask port ad pifad[15:0] piead[15:0] i bit t pulse chapter 3 port integration module (pim9e256v1) mc9s12e256 data sheet, rev. 1.08 164 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 165 chapter 4 clocks and reset generator (crgv4) 4.1 introduction this specification describes the function of the clocks and reset generator (crgv4). 4.1.1 features the main features of this block are: ? phase-locked loop (pll) frequency multiplier ? reference divider ? automatic bandwidth control mode for low-jitter operation ? automatic frequency lock detector ? cpu interrupt on entry or exit from locked condition ? self-clock mode in absence of reference clock ? system clock generator ? clock quality check ? clock switch for either oscillator- or pll-based system clocks ? user selectable disabling of clocks during wait mode fo r reduced power consumption ? computer operating properly (cop) watc hdog timer with time-out clear window ? system reset generation from the following possible sources: ? power-on reset ? low voltage reset refer to the device overview section for availability of this feature. ?cop reset ? loss of clock reset ? external pin reset ? real-time interrupt (rti) chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 166 freescale semiconductor 4.1.2 modes of operation this subsection lists and briefly describe s all operating modes supported by the crg. ? run mode all functional parts of the crg are running during normal run mode. if rti or cop functionality is required the individual bits of the associated rate select regist ers (copctl, rtictl) have to be set to a nonzero value. ? wait mode this mode allows to disable the system and co re clocks depending on the configuration of the individual bits in the clksel register. ? stop mode depending on the setting of the pstp bit, stop mode can be differentiated between full stop mode (pstp = 0) and pseudo-stop mode (pstp = 1). ? full stop mode the oscillator is disabled and thus all system and core clocks are stopped. the cop and the rti remain frozen. ? pseudo-stop mode the oscillator continues to r un and most of the system and core clocks are stopped. if the respective enable bits are set the cop and rti wi ll continue to run, else they remain frozen. ? self-clock mode self-clock mode will be entered if the clock m onitor enable bit (cme) and the self-clock mode enable bit (scme) are both asserted and the clock monitor in the osci llator block dete cts a loss of clock. as soon as self-clock mode is entered th e crgv4 starts to perform a clock quality check. self-clock mode remains active until the clock qua lity check indicates that the required quality of the incoming clock signal is met (frequency and amplitude ). self-clock mode should be used for safety purposes only. it provides re duced functionality to the mcu in case a loss of clock is causing severe system conditions. 4.1.3 block diagram figure 4-1 shows a block diagram of the crgv4. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 167 figure 4-1. crg block diagram 4.2 external signal description this section lists and describes th e signals that connect off chip. 4.2.1 v ddpll , v sspll ? pll operating voltage, pll ground these pins provides operating voltage (v ddpll ) and ground (v sspll ) for the pll circuitry. this allows the supply voltage to the pll to be independently bypassed. even if pll usage is not required v ddpll and v sspll must be connected properly. 4.2.2 xfc ? pll loop filter pin a passive external loop filter must be placed on the xfc pin. the filter is a second-order, low-pass filter to eliminate the vco input ripple. the value of the external filter network a nd the reference frequency determines the speed of the corrections and the stability of the pll. refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for calculation of pll loop fi lter (xfc) components. if pll usage is not required the xfc pin must be tied to v ddpll . crg registers clock and reset cop reset rti pll xfc v ddpll v sspll oscil- extal xtal control bus clock system reset oscillator clock pllclk oscclk core clock clock monitor cm fail clock quality checker reset generator xclks power-on reset low voltage reset 1 cop timeout real-time interrupt pll lock interrupt self-clock mode interrupt lator voltage regulator 1 refer to the device overview section for availability of the low-voltage reset feature. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 168 freescale semiconductor figure 4-2. pll loop filter connections 4.2.3 reset ? reset pin reset is an active low bidirectional reset pin. as an input it initializes th e mcu asynchronously to a known start-up state. as an open-drain output it indicates that an system reset (inter nal to mcu) has been triggered. 4.3 memory map and register definition this section provides a detailed descripti on of all registers acce ssible in the crgv4. 4.3.1 module memory map table 4-1 gives an overview on all crgv4 registers. table 4-1. crgv4 memory map address offset use access 0x0000 crg synthesizer register (synr) r/w 0x0001 crg reference divider register (refdv) r/w 0x0002 crg test flags register (ctflg) 1 1 ctflg is intended for factory test purposes only. r/w 0x0003 crg flags register (crgflg) r/w 0x0004 crg interrupt enable register (crgint) r/w 0x0005 crg clock select register (clksel) r/w 0x0006 crg pll control register (pllctl) r/w 0x0007 crg rti control register (rtictl) r/w 0x0008 crg cop control register (copctl) r/w 0x0009 crg force and bypass test register (forbyp) 2 2 forbyp is intended for fact ory test purposes only. r/w 0x000a crg test control register (ctctl) 3 3 ctctl is intended for factory test purposes only. r/w 0x000b crg cop arm/timer reset (armcop) r/w mcu xfc rs cs v ddpll cp chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 169 note register address = base a ddress + address offset, wh ere the base address is defined at the mcu level and the addr ess offset is defined at the module level. 4.3.2 register descriptions this section describes in address order all the crgv4 registers and their individual bits. register name bit 7654321bit 0 synr r 0 0 syn5 syn4 syn3 syn2 syn1 syn0 w refdvr0000 refdv3 refdv2 refdv1 refdv0 w ctflgr00000000 w crgflg r rtif porf lvrf lockif lock track scmif scm w crgint r rtie 00 lockie 00 scmie 0 w clksel r pllsel pstp syswai roawai pllwai cwai rtiwai copwai w pllctl r cme pllon auto acq 0 pre pce scme w rtictl r 0 rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w copctl r wcop rsbck 000 cr2 cr1 cr0 w forbypr00000000 w ctctlr00000000 w = unimplemented or reserved figure 4-3. crg register summary chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 170 freescale semiconductor 4.3.2.1 crg synthesizer register (synr) the synr register controls the multiplication factor of the pll. if the pll is on, the count in the loop divider (synr) register effectivel y multiplies up the p ll clock (pllclk) from the reference frequency by 2 x (synr+1). pllclk will not be below the minimum vco frequency (f scm ). note if pll is selected (pllsel= 1), bus clock = pllclk / 2 bus clock must not exceed the maxi mum operating system frequency. read: anytime write: anytime except if pllsel = 1 note write to this register init ializes the lock detector bit and the track detector bit. armcopr00000000 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 76543210 r0 0 syn5 synr syn3 syn2 syn1 syn0 w reset00000000 = unimplemented or reserved figure 4-4. crg synthesizer register (synr) register name bit 7654321bit 0 = unimplemented or reserved figure 4-3. crg register summary (continued) pllclk 2xoscclkx synr 1 + () refdv 1 + () ---------------------------------- - = chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 171 4.3.2.2 crg reference divider register (refdv) the refdv register provides a finer granularity for the pll multiplier st eps. the count in the reference divider divides oscclk frequency by refdv + 1. read: anytime write: anytime except when pllsel = 1 note write to this register init ializes the lock detector bit and the track detector bit. 4.3.2.3 reserved register (ctflg) this register is reserved for factory testing of the crgv4 module and is not available in normal modes. read: always reads 0x0000 in normal modes write: unimplemented in normal modes note writing to this register when in special mode can alter the crgv4 functionality. 76543210 r0 0 0 0 refdv3 refdv2 refdv1 refdv0 w reset00000000 = unimplemented or reserved figure 4-5. crg reference divider register (refdv) 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 4-6. crg reserved register (ctflg) chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 172 freescale semiconductor 4.3.2.4 crg flags register (crgflg) this register provides cr g status bits and flags. read: anytime write: refer to each bit fo r individual write conditions 76543210 r rtif porf lvrf lockif lock track scmif scm w reset0note 1note 200000 1. porf is set to 1 when a power-on re set occurs. unaffected by system reset. 2. lvrf is set to 1 when a low-voltage reset occurs. unaffected by system reset. = unimplemented or reserved figure 4-7. crg flag register (crgflg) table 4-2. crgflg field descriptions field description 7 rtif real-time interrupt flag ? rtif is set to 1 at the end of the rti period. this flag can only be cleared by writing a 1. writing a 0 has no effect. if enabled (r tie = 1), rtif causes an interrupt request. 0 rti time-out has not yet occurred. 1 rti time-out has occurred. 6 porf power-on reset flag ? porf is set to 1 when a power-on reset occurs. this flag can only be cleared by writing a 1. writing a 0 has no effect. 0 power-on reset has not occurred. 1 power-on reset has occurred. 5 lv r f low-voltage reset flag ? if low voltage reset feature is not available (see chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? ), lvrf always reads 0. lvrf is set to 1 when a low voltage reset occurs. this flag can only be cleared by writing a 1. writing a 0 has no effect. 0 low voltage reset has not occurred. 1 low voltage reset has occurred. 4 lockif pll lock interrupt flag ? lockif is set to 1 when lock status bi t changes. this flag can only be cleared by writing a 1. writing a 0 has no effect.if enabled (l ockie = 1), lockif causes an interrupt request. 0 no change in lock bit. 1 lock bit has changed. 3 lock lock status bit ? lock reflects the current state of pll lock c ondition. this bit is cleared in self-clock mode. writes have no effect. 0 pll vco is not within the desired tolerance of the target frequency. 1 pll vco is within the desired tolerance of the target frequency. 2 track track status bit ? track reflects the current state of pll track co ndition. this bit is cleared in self-clock mode. writes have no effect. 0 acquisition mode status. 1 tracking mode status. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 173 4.3.2.5 crg interrupt enable register (crgint) this register enables crg interrupt requests. read: anytime write: anytime 1 scmif self-clock mode interrupt flag ? scmif is set to 1 when scm status bit changes. this flag can only be cleared by writing a 1. writing a 0 has no effect. if enabled (scmie=1), scmif causes an interrupt request. 0 no change in scm bit. 1 scm bit has changed. 0 scm self-clock mode status bit ? scm reflects the current clocking mode. writes have no effect. 0 mcu is operating normally with oscclk available. 1 mcu is operating in self-clock mode with oscclk in an unknown state. all clocks are derived from pllclk running at its minimum frequency f scm . 76543210 r rtie 00 lockie 00 scmie 0 w reset00000000 = unimplemented or reserved figure 4-8. crg interrupt enable register (crgint) table 4-3. crgint field descriptions field description 7 rtie real-time interrupt enable bit 0 interrupt requests from rti are disabled. 1 interrupt will be requested whenever rtif is set. 4 lockie lock interrupt enable bit 0 lock interrupt requests are disabled. 1 interrupt will be requested whenever lockif is set. 1 scmie self-clock mode interrupt enable bit 0 scm interrupt requests are disabled. 1 interrupt will be requested whenever scmif is set. table 4-2. crgflg field descriptions (continued) field description chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 174 freescale semiconductor 4.3.2.6 crg clock select register (clksel) this register controls crg clock selection. refer to figure 4-17 for details on the effect of each bit. read: anytime write: refer to each bit fo r individual write conditions 76543210 r pllsel pstp syswai roawai pllwai cwai rtiwai copwai w reset00000000 figure 4-9. crg clock select register (clksel) table 4-4. clksel field descriptions field description 7 pllsel pll select bit ? write anytime. writing a 1 when lock = 0 and auto = 1, or track = 0 and auto = 0 has no effect. this prevents the selection of an unstable pl lclk as sysclk. pllsel bit is cleared when the mcu enters self-clock mode, stop mode or wait mode with pllwai bit set. 0 system clocks are derived from oscclk (bus clock = oscclk / 2). 1 system clocks are derived from pllclk (bus clock = pllclk / 2). 6 pstp pseudo-stop bit ? write: anytime ? this bit controls the func tionality of the oscillator during stop mode. 0 oscillator is disabled in stop mode. 1 oscillator continues to run in stop mode (pse udo-stop). the oscillator amplitude is reduced. refer to oscillator block description for availability of a reduced oscillator amplitude. note: pseudo-stop allows for faster stop recovery and r educes the mechanical stress and aging of the resonator in case of frequent stop conditions at the expen se of a slightly increased power consumption. note: lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro-magnetic susc eptibility (ems) tests. 5 syswai system clocks stop in wait mode bit ? write: anytime 0 in wait mode, the system clocks continue to run. 1 in wait mode, the system clocks stop. note: rti and cop are not affected by syswai bit. 4 roawai reduced oscillator amplitude in wait mode bit ? write: anytime ? refer to chapter 5, ?oscillator (oscv2)? for availability of a reduced oscillator amplitude. if no such feature exists in the oscillator block then setting this bit to 1 will not have any effect on power consumption. 0 normal oscillator amplitude in wait mode. 1 reduced oscillator amplitude in wait mode. note: lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro-magnetic susc eptibility (ems) tests. 3 pllwai pll stops in wait mode bit ? write: anytime ? if pllwai is set, th e crgv4 will clear the pllsel bit before entering wait mode. the pllon bit remains set during wa it mode but the pll is powered down. upon exiting wait mode, the pllsel bit has to be set manually if pll clock is required. while the pllwai bit is set the auto bit is set to 1 in or der to allow the pll to automatically lock on the selected target frequency after exiting wait mode. 0 pll keeps running in wait mode. 1 pll stops in wait mode. 2 cwai core stops in wait mode bit ? write: anytime 0 core clock keeps running in wait mode. 1 core clock stops in wait mode. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 175 4.3.2.7 crg pll control register (pllctl) this register controls the pll functionality. read: anytime write: refer to each bit fo r individual write conditions 1 rtiwai rti stops in wait mode bit ? write: anytime 0 rti keeps running in wait mode. 1 rti stops and initializes the rti dividers whenever the part goes into wait mode. 0 copwai cop stops in wait mode bit ? normal modes: write once ?special modes: write anytime 0 cop keeps running in wait mode. 1 cop stops and initializes the cop dividers whenever the part goes into wait mode. 76543210 r cme pllon auto acq 0 pre pce scme w reset11110001 = unimplemented or reserved figure 4-10. crg pll control register (pllctl) table 4-5. pllctl field descriptions field description 7 cme clock monitor enable bit ? cme enables the clock monitor. write anytime except when scm = 1. 0 clock monitor is disabled. 1 clock monitor is enabled. slow or stopped clocks wi ll cause a clock monitor reset sequence or self-clock mode. note: operating with cme = 0 will not detect any loss of clock. in case of poor clock quality this could cause unpredictable operation of the mcu. note: in stop mode (pstp = 0) the clock monitor is disabl ed independently of the cme bit setting and any loss of clock will not be detected. 6 pllon phase lock loop on bit ? pllon turns on the pll circuitry. in se lf-clock mode, the pll is turned on, but the pllon bit reads the last latched value. write anytime except when pllsel = 1. 0 pll is turned off. 1 pll is turned on. if auto bit is se t, the pll will lock automatically. 5 auto automatic bandwidth control bit ? auto selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the vco is running. write anytime except when pllwai=1, because pllwai sets the auto bit to 1. 0 automatic mode control is disabled and the pll is under software control, using acq bit. 1 automatic mode control is enabled and acq bit has no effect. 4 acq acquisition bit ? write anytime. if auto=1 this bit has no effect. 0 low bandwidth filter is selected. 1 high bandwidth filter is selected. table 4-4. clksel field descriptions (continued) field description chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 176 freescale semiconductor 4.3.2.8 crg rti contro l register (rtictl) this register selects the timeout period for the real-time interrupt. read: anytime write: anytime note a write to this register initializes the rti counter. 2 pre rti enable during pseudo-stop bit ? pre enables the rti during pseudo-stop mode. write anytime. 0 rti stops running during pseudo-stop mode. 1 rti continues running during pseudo-stop mode. note: if the pre bit is cleared the rti dividers will go static while pseudo-stop mode is active. the rti dividers will not initialize like in wait mode with rtiwai bit set. 1 pce cop enable during pseudo-stop bit ? pce enables the cop during pseudo-stop mode. write anytime. 0 cop stops running during pseudo-stop mode 1 cop continues running during pseudo-stop mode note: if the pce bit is cleared the cop dividers will go static while pseudo-stop mode is active. the cop dividers will not initialize like in wait mode with copwai bit set. 0 scme self-clock mode enable bit ? normal modes: write once ?special modes: write anytime ? scme can not be cleared while operating in self-clock mode (scm=1). 0 detection of crystal clock failure causes clock monitor reset (see section 4.5.1, ?clock monitor reset ?). 1 detection of crystal clock failure fo rces the mcu in self-clock mode (see section 4.4.7.2, ?self-clock mode ?). 76543210 r0 rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w reset00000000 = unimplemented or reserved figure 4-11. crg rti cont rol register (rtictl) table 4-6. rtictl field descriptions field description 6:4 rtr[6:4] real-time interrupt presc ale rate select bits ? these bits select the prescale rate for the rti. see ta b l e 4 - 7 . 3:0 rtr[3:0] real-time interrupt modu lus counter select bits ? these bits select the modulus counter target value to provide additional granularity. ta bl e 4 - 7 shows all possible divide values selectable by the rtictl register. the source clock for the rti is oscclk. table 4-5. pllctl field descriptions (continued) field description chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 177 table 4-7. rti frequency divide rates rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 ) 0000 ( 1) off * 2 10 2 11 2 12 2 13 2 14 2 15 2 16 0001 ( 2) off * 2x2 10 2x2 11 2x2 12 2x2 13 2x2 14 2x2 15 2x2 16 0010 ( 3) off * 3x2 10 3x2 11 3x2 12 3x2 13 3x2 14 3x2 15 3x2 16 0011 ( 4) off * 4x2 10 4x2 11 4x2 12 4x2 13 4x2 14 4x2 15 4x2 16 0100 ( 5) off * 5x2 10 5x2 11 5x2 12 5x2 13 5x2 14 5x2 15 5x2 16 0101 ( 6) off * 6x2 10 6x2 11 6x2 12 6x2 13 6x2 14 6x2 15 6x2 16 0110 ( 7) off * 7x2 10 7x2 11 7x2 12 7x2 13 7x2 14 7x2 15 7x2 16 0111 ( 8) off * 8x2 10 8x2 11 8x2 12 8x2 13 8x2 14 8x2 15 8x2 16 1000 ( 9) off * 9x2 10 9x2 11 9x2 12 9x2 13 9x2 14 9x2 15 9x2 16 1001 ( 10) off * 10x2 10 10x2 11 10x2 12 10x2 13 10x2 14 10x2 15 10x2 16 1010 (3 11) off * 11x2 10 11x2 11 11x2 12 11x2 13 11x2 14 11x2 15 11x2 16 1011 (3 12) off * 12x2 10 12x2 11 12x2 12 12x2 13 12x2 14 12x2 15 12x2 16 1100 ( 313) off * 13x2 10 13x2 11 13x2 12 13x2 13 13x2 14 13x2 15 13x2 16 1101 ( 14) off * 14x2 10 14x2 11 14x2 12 14x2 13 14x2 14 14x2 15 14x2 16 1110 (3 15) off * 15x2 10 15x2 11 15x2 12 15x2 13 15x2 14 15x2 15 15x2 16 1111 ( 316) off * 16x2 10 16x2 11 16x2 12 16x2 13 16x2 14 16x2 15 16x2 16 * denotes the default value out of reset.this value should be used to disable the rti to ensure future backwards compatibility. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 178 freescale semiconductor 4.3.2.9 crg cop control register (copctl) this register controls the cop (computer operating properly) watchdog. read: anytime write: wcop, cr2, cr1, cr0: once in user mode, anytime in special mode write: rsbck: once 76543210 r wcop rsbck 000 cr2 cr1 cr0 w reset00000000 = unimplemented or reserved figure 4-12. crg cop control register (copctl) table 4-8. copctl field descriptions field description 7 wcop window cop mode bit ? when set, a write to the armcop register must occur in the last 25% of the selected period. a write during the first 75% of the selected peri od will reset the part. as long as all writes occur during this window, 0x0055 can be written as often as desired . as soon as 0x00aa is written after the 0x0055, the time-out logic restarts and the user must wait until the next window before writing to armcop. ta b l e 4 - 9 shows the exact duration of this window for the seven available cop rates. 0 normal cop operation 1 window cop operation 6 rsbck cop and rti stop in active bdm mode bit 0 allows the cop and rti to keep running in active bdm mode. 1 stops the cop and rti counters whenever the part is in active bdm mode. 2:0 cr[2:0] cop watchdog timer rate select ? these bits select the cop time-out rate (see ta bl e 4 - 9 ). the cop time-out period is oscclk period divided by cr[2:0] valu e. writing a nonzero value to cr[2:0] enables the cop counter and starts the time-o ut period. a cop counter time -out causes a system reset. this can be avoided by periodically (before time-out) reinitializing the cop counter via the armcop register . table 4-9. cop watchdog rates 1 1 oscclk cycles are referenced from the previous cop time-out reset (writing 0x0055/0x00aa to the armcop register) cr2 cr1 cr0 oscclk cycles to time out 0 0 0 cop disabled 001 2 14 010 2 16 011 2 18 100 2 20 101 2 22 110 2 23 111 2 24 chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 179 4.3.2.10 reserved register (forbyp) note this reserved register is designed for factory test purposes only, and is not intended for general user access. writing to this register when in special modes can alter the crg?s functionality. read: always read 0x0000 except in special modes write: only in special modes 4.3.2.11 reserved register (ctctl) note this reserved register is designed for factory test purposes only, and is not intended for general user access. writing to this register when in special test modes can alter the crg?s functionality. read: always read 0x0080 except in special modes write: only in special modes 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 4-13. reserved register (forbyp) 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 4-14. reserved register (ctctl) chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 180 freescale semiconductor 4.3.2.12 crg cop timer arm/ reset register (armcop) this register is used to restart the cop time-out period. read: always reads 0x0000 write: anytime when the cop is disabled (cr[2:0] = ?000? ) writing to this register has no effect. when the cop is enabled by setting cr [2:0] nonzero, the following applies: writing any value other than 0x00 55 or 0x00aa causes a cop reset. to restart the cop time-out period you must write 0x0055 followed by a write of 0x00aa. other instructions may be executed between these writes but the sequence (0x0055, 0x00aa) must be completed prior to cop end of time-out period to avoid a cop reset. sequen ces of 0x0055 writes or se quences of 0x00aa writes are allowed. when the wcop bit is set, 0x0055 and 0x00aa writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a cop reset. 4.4 functional description this section gives detailed informations on the internal operation of the design. 4.4.1 phase locked loop (pll) the pll is used to run the mcu from a different time base than the incoming oscclk. for increased flexibility, oscclk can be divided in a range of 1 to 16 to generate the reference fr equency. this offers a finer multiplication granularity. th e pll can multiply this referenc e clock by a multiple of 2, 4, 6,... 126,128 based on the synr register. caution although it is possible to set the two di viders to command a very high clock frequency, do not exceed the specified bus frequency limit for the mcu. if (pllsel = 1), bus clock = pllclk / 2 the pll is a frequency generator th at operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and th e target frequency. the pll can change between acquisition and tracking modes eith er automatically or manually. 76543210 r00000000 wbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset00000000 figure 4-15. armcop register diagram pllclk 2 oscclk synr 1 + [] refdv 1 + [] ---------------------------------- - = chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 181 the vco has a minimum operating frequency, which corresponds to the self-clock mode frequency f scm . figure 4-16. pll functional diagram 4.4.1.1 pll operation the oscillator output clock signa l (oscclk) is fed through the refe rence programmable divider and is divided in a range of 1 to 16 (refdv+1) to output the reference clock. the vco output clock, (pllclk) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (synr +1)] to output the feedback clock. see figure 4-16 . the phase detector then compares the feedback cl ock, with the reference cl ock. correction pulses are generated based on the phase difference between the two signals. the loop filt er then slightly alters the dc voltage on the external fi lter capacitor connected to xfc pin, ba sed on the width and direction of the correction pulse. the filter can make fast or slow corrections depe nding on its mode, as described in the next subsection. the values of the ex ternal filter network and the reference freque ncy determine the speed of the corrections and the stability of the pll. 4.4.1.2 acquisition and tracking modes the lock detector compares the fre quencies of the feedback clock, and the reference clock. therefore, the speed of the lock detector is dire ctly proportional to the final referen ce frequency. the circuit determines the mode of the pll and the lock condition based on this comparison. reduced consumption oscillator extal xtal oscclk pllclk reference programmable divider pdet phase detector refdv <3:0> loop programmable divider syn <5:0> cpump vco lock loop filter xfc pin up down lock detector reference feedback vddpll vddpll/vsspll crystal monitor vddpll/vsspll vdd/vss supplied by: chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 182 freescale semiconductor the pll filter can be manually or automatically c onfigured into one of two possible operating modes: ? acquisition mode in acquisition mode, the filter can make large freque ncy corrections to the vco. this mode is used at pll start-up or when the pll has suffered a se vere noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the track status bit is cleared in the crgflg register. ? tracking mode in tracking mode, the filter make s only small corrections to the fr equency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct and the track bit is set in the crgflg register. the pll can change the bandwidth or operational m ode of the loop filter ma nually or automatically. in automatic bandwidth control mode (auto = 1), th e lock detector automatically switches between acquisition and tracking mode s. automatic bandwidth control mode al so is used to determine when the pll clock (pllclk) is safe to use as the source for the system and core clocks. if pll lock interrupt requests are enabled, the software can wait for an interrupt request and then check the lock bit. if cpu interrupts are disabled, software can poll the lock bit continuously (dur ing pll start-up, usually) or at periodic intervals. in either case, only when the lock bit is set, is the pllclk clock safe to use as the source for the system and core clocks. if the pll is selected as the source for the system and core clocks and the lock bit is clear, the pll has suffered a severe no ise hit and the software must take appropriate action, depending on the application. the following conditions apply when the pll is in automatic bandwidth co ntrol mode (auto = 1): ? the track bit is a read-only indi cator of the mode of the filter. ? the track bit is set when the vco fre quency is within a certain tolerance, ? trk , and is clear when the vco frequency is out of a certain tolerance, ? unt . ? the lock bit is a read-only indica tor of the locked state of the pll. ? the lock bit is set when the vco fre quency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . ? cpu interrupts can occur if enabled (lockie = 1) when the lock condition changes, toggling the lock bit. the pll can also operate in manua l mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operati on. such systems typicall y operate well below the maximum system frequency (f sys ) and require fast start- up. the following conditions apply when in manual mode: ? acq is a writable control bit th at controls the mode of the filt er. before turning on the pll in manual mode, the acq bit should be asserted to configure the filter in acquisition mode. ? after turning on the pll by setting the pllo n bit software must wait a given time (t acq ) before entering tracking mode (acq = 0). ? after entering tracking mode soft ware must wait a given time (t al ) before selecting the pllclk as the source for system a nd core clocks (pllsel = 1). chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 183 4.4.2 system clocks generator figure 4-17. system clocks generator the clock generator cr eates the clocks used in the mcu (see figure 4-17 ). the gating c ondition placed on top of the individual clock gates indicates the depende ncies of different modes (stop, wait) and the setting of the respective configuration bits. the peripheral modules use the bus clock. some periphe ral modules also use the oscillator clock. the memory blocks use the bus clock. if th e mcu enters self-clock mode (see section 4.4.7.2, ?self-clock mode ?), oscillator clock source is switched to pllclk running at its minimum frequency f scm . the bus clock is used to generate the clock visible at the eclk pin. the core clock signal is the clock for the cpu. the core clock is twice the bus clock as shown in figure 4-18 . but note that a cpu cycle corresponds to one bus clock. pll clock mode is selected with pllsel bit in the clksel regist er. when selected, the pll output clock drives sysclk for the main system including the cpu and peri pherals. the pll cannot be turned off by clearing the pllon bit, if the pll clock is selected. when pllsel is changed, it takes a maximum oscillator phase lock loop extal xtal sysclk rti oscclk pllclk clock phase generator bus clock clock monitor 1 0 pllsel or scm 2 core clock cop oscillator oscillator = clock gate gating condition wait(cwai,syswai), stop wait(rtiwai), stop(pstp ,pre ), rti enable wait(copwai), stop(pstp ,pce ), cop enable wait(syswai), stop stop(pstp ) 1 0 scm wait(syswai), stop clock clock (running during pseudo-stop mode chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 184 freescale semiconductor of 4 oscclk plus 4 pllclk cycles to make the tr ansition. during the transiti on, all clocks freeze and cpu activity ceases. figure 4-18. core clock and bus clock relationship 4.4.3 clock monitor (cm) if no oscclk edges are detected wi thin a certain time, the clock moni tor within the oscillator block generates a clock monitor fail event. the crgv4 then asserts self-clock mode or ge nerates a system reset depending on the state of scme bit. if the clock monitor is disabled or the presen ce of clocks is detected no failure is indicated by th e oscillator block.the cl ock monitor function is en abled/disabled by the cme control bit. 4.4.4 clock quality checker the clock monitor performs a coarse check on th e incoming clock signal. the clock quality checker provides a more accurate check in addition to the clock monitor. a clock quality check is triggere d by any of the following events: ? power-on reset (por) ? low voltage reset (lvr) ? wake-up from full stop mode (exit full stop) ? clock monitor fail indication (cm fail) a time window of 50000 vco clock cycles 1 is called check window . a number greater equal than 4096 rising oscclk edges within a check window is called osc ok . note that osc ok immediately terminates the current check window . see figure 4-19 as an example. 1. vco clock cycles are generated by the pll when running at minimum frequency f scm . core clock: bus clock / eclk chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 185 figure 4-19. check window example the sequence for clock quality check is shown in figure 4-20 . figure 4-20. sequence for clock quality check note remember that in parall el to additional actions ca used by self-clock mode or clock monitor reset 1 handling the clock quality checker continues to check the oscclk signal. 1. a clock monitor reset will always set the scme bit to logical?1? 12 49999 50000 vco clock check window 12345 4095 4096 3 oscclk osc ok check window osc ok ? scm active? switch to oscclk exit scm clock ok num=0 num<50 ? num=num+1 yes no yes scme=1 ? no enter scm scm active? yes clock monitor reset no yes no num=50 yes no por exit full stop cm fail lv r chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 186 freescale semiconductor note the clock quality checker enables the pll and the voltage regulator (vreg) anytime a clock check has to be performed. an ongoing clock quality check could also cause a running pll (f scm ) and an active vreg during pseudo-stop mode or wait mode 4.4.5 computer operating properly watchdog (cop) figure 4-21. clock chain for cop the cop (free running watchdog timer) enables the us er to check that a program is running and sequencing properly. the cop is disa bled out of reset. when the co p is being used, software is responsible for keeping the cop from timing out. if the cop times out it is an indication that the software is no longer being executed in the intended seque nce; thus a system reset is initiated (see section 4.5.2, ?computer operating prope rly watchdog (cop) reset ).? the cop runs with a gated oscclk (see figure 4-21 ). three control bits in the copctl register allow selection of seve n cop time-out periods. when cop is enabled, the program must write 0x0055 and 0x00aa (in this order) to the armcop register during the select ed time-out period. as soon as this is done , the cop time-out period is restarted. if the program fails to do this and the cop times out, the part will re set. also, if any value other than 0x0055 or 0x00aa is written, the part is immediately reset. windowed cop operation is enabled by setting wcop in the copctl register. in this mode, writes to the armcop register to clear the co p timer must occur in the last 25% of the selected time-out period. a premature write will im mediately reset the part. if pce bit is set, the cop will c ontinue to run in pseudo-stop mode. oscclk cr[2:0] cop timeout 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 4 4 2 4 2 16384 4 cr[2:0] = clock gate wait(copwai), stop(pstp ,pce ), cop enable gating condition chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 187 4.4.6 real-time interrupt (rti) the rti can be used to generate a hardware interr upt at a fixed periodic rate . if enabled (by setting rtie=1), this interrupt will occur at the rate sele cted by the rtictl register. the rti runs with a gated oscclk (see figure 4-22 ). at the end of the rti time-out period the rtif flag is set to 1 and a new rti time-out period starts immediately. a write to the rtictl register restarts the rti time-out period. if the pre bit is set, the rti will continue to run in pseudo-stop mode. . figure 4-22. clock chain for rti 4.4.7 modes of operation 4.4.7.1 normal mode the crgv4 block behaves as described within this specification in all normal modes. 4.4.7.2 self-clock mode the vco has a minimum operating frequency, f scm . if the external clock fre quency is not available due to a failure or due to long crystal start-up time, the bus cloc k and the core clock ar e derived from the vco oscclk rtr[6:4] 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 counter (rtr[3:0]) 4-bit modulus 1024 rti timeout = clock gate wait(rtiwai), stop(pstp ,pre ), rti enable gating condition chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 188 freescale semiconductor running at minimum operating frequency; this mode of operation is called self-clock mode. this requires cme = 1 and scme = 1. if the mcu was clocked by the pll clock prior to entering self-clock mode, the pllsel bit will be cleared. if the external clock signal has stabilized again, the crg will automatically select oscclk to be the system clock and return to normal mode. see section 4.4.4, ?clock quality checker ? for more information on enteri ng and leaving self-clock mode. note in order to detect a potential cloc k loss, the cme bit should be always enabled (cme=1). if cme bit is disabled and the mcu is configured to run on pll clock (pllclk), a loss of external clock (osc clk) will not be detected and will cause the system clock to drift towards the vco?s minimum frequency f scm . as soon as the external clock is available again the system clock ramps up to its pll target frequency. if the mcu is running on external clock any loss of clock will cause the system to go static. 4.4.8 low-power operation in run mode the rti can be stopped by setting the associated rate select bits to 0. the cop can be stopped by setting the a ssociated rate select bits to 0. 4.4.9 low-power operation in wait mode the wai instruction puts the mcu in a low power consumption stand-by mode depending on setting of the individual bits in the clksel regi ster. all individual wait mode conf iguration bits can be superposed. this provides enhanced granularity in reducing th e level of power consumption during wait mode. table 4-10 lists the individual configurati on bits and the parts of the mcu that are affected in wait mode. after executing the wai instruction the core request s the crg to switch mcu into wait mode. the crg then checks whether the pllwai, cwai and syswai bits are asserted (see figure 4-23 ). depending on the configuration the crg switches the system and core clocks to os cclk by clearing the pllsel bit, disables the pll, disables the core clocks and finall y disables the remaining syst em clocks. as soon as all clocks are switched off wait mode is active. table 4-10. mcu configuration during wait mode pllwai cwai syswai rtiwai copwai roawai pll stopped ????? core ? stopped stopped ? ? ? system ? ? stopped ? ? ? rti ???stopped?? cop ????stopped? oscillator ?????reduced 1 1 refer to oscillator block description for availability of a reduced oscillator amplitude. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 189 figure 4-23. wait mode entry/exit sequence enter wait mode pllwai=1 ? exit wait w. cmreset exit wait w. ext.reset exit wait mode enter scm exit wait mode core req?s wait mode. cwai or syswai=1 ? syswai=1 ? clear pllsel, disable pll disable core clocks disable system clocks cme=1 ? int ? cm fail ? scme=1 ? scmie=1 ? continue w. normal op no no no no no no no yes yes yes yes yes no yes yes yes wait mode left due to external reset generate scm interrupt (wakeup from wait) scm=1 ? enter scm no yes chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 190 freescale semiconductor there are five different scenarios for the crg to restart the mc u from wait mode: ? external reset ? clock monitor reset ?cop reset ? self-clock mode interrupt ? real-time interrupt (rti) if the mcu gets an external reset during wait mode active, th e crg asynchronously restores all configuration bits in the register sp ace to its default settings and starts the reset generator. after completing the reset sequence processing begins by fetching the norma l reset vector. wait mode is exited and the mcu is in run mode again. if the clock monitor is enabled (cme=1) the mc u is able to leave wait mode when loss of oscillator/external clock is detected by a clock monitor fail. if the scme bit is not asserted the crg generates a clock monitor fail reset (cmreset). the crg?s beha vior for cmreset is the same compared to external reset, but anot her reset vector is fetched after comp letion of the reset sequence. if the scme bit is asserted the crg ge nerates a scm interrupt if enable d (scmie=1). after generating the interrupt the crg enters self-clock mode and starts the clock quality checker (see section 4.4.4, ?clock quality checker ?). then the mcu continues with normal ope ration.if the scm interrupt is blocked by scmie = 0, the scmif flag will be asserted and clock quality checks will be performed but the mcu will not wake-up from wait mode. if any other interrupt sour ce (e.g. rti) triggers exit fr om wait mode the mcu im mediately continues with normal operation. if the pll has been powered-down during wait mode the pllsel bit is cleared and the mcu runs on oscclk after leaving wait mode. the software must manually set the pllsel bit again, in order to switch system a nd core clocks to the pllclk. if wait mode is entered from self-c lock mode, the crg will continue to check the clock quality until clock check is successful. the p ll and voltage regulator (vre g) will remain enabled. table 4-11 summarizes the outcome of a clock loss while in wait mode. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 191 table 4-11. outcome of clock loss in wait mode cme scme scmie crg actions 0 x x clock failure --> no action, clock loss not detected. 1 0 x clock failure --> crg performs clock monitor reset immediately 1 1 0 clock failure --> scenario 1: oscclk recovers prior to exiting wait mode. ? mcu remains in wait mode, ? vreg enabled, ? pll enabled, ? scm activated, ? start clock quality check, ? set scmif interrupt flag. some time later oscclk recovers. ? cm no longer indicates a failure, ? 4096 oscclk cycles later clock quality check indi cates clock o.k., ? scm deactivated, ? pll disabled depending on pllwai, ? vreg remains enabled (never gets disabled in wait mode) . ? mcu remains in wait mode. s ome time later either a wakeup interrupt occurs (no scm interrupt) ? exit wait mode using oscclk as system clock (sysclk), ? continue normal operation. or an external reset is applied. ? exit wait mode using oscclk as system clock, ? start reset sequence. scenario 2: oscclk does not recover prior to exiting wait mode. ? mcu remains in wait mode, ? vreg enabled, ? pll enabled, ? scm activated, ? start clock quality check, ? set scmif interrupt flag, ? keep performing clock quality checks (could continue infinitely) while in wait mode. s ome time later either a wakeup interrupt occurs (no scm interrupt) ? exit wait mode in scm using pll clock (f scm ) as system clock, ? continue to perform additional clock quality checks until oscclk is o.k. again. or an external reset is applied. ? exit wait mode in scm using pll clock (f scm ) as system clock, ? start reset sequence, ? continue to perform additional clock quality checks until oscclk is o.k.again. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 192 freescale semiconductor 4.4.10 low-power operation in stop mode all clocks are stopped in stop m ode, dependent of the setting of the pce, pre and pstp bit. the oscillator is disabled in stop mode unless the pstp bit is set. all counters and di viders remain frozen but do not initialize. if the pre or pce bits are set, the rti or cop conti nues to run in pseudo-stop mode. in addition to disabling system and core clocks the crg requests other functional units of the mcu (e.g. voltage-regulator) to enter their indi vidual power-saving modes (if available). this is the main difference between pseudo-stop mode and wait mode. after executing the stop instructi on the core requests the crg to swit ch the mcu into stop mode. if the pllsel bit remains set when entering stop mode, the crg will switch the system and core clocks to oscclk by clearing the pllsel bit. th en the crg disables the pll, disa bles the core clock and finally disables the remaining system clocks. as soon as all clocks are switched off, stop mode is active. if pseudo-stop mode (pstp = 1) is en tered from self-clock mode the crg will continue to check the clock quality until clock check is successful. the pll and the voltage regu lator (vreg) will remain enabled. if full stop mode (pstp = 0) is ente red from self-clock mode an ongoing clock quality check will be stopped. a complete timeout window check will be started when stop mode is exited again. wake-up from stop mode also depends on the setting of the pstp bit. 1 1 1 clock failure --> ? vreg enabled, ? pll enabled, ? scm activated, ? start clock quality check, ? scmif set. scmif generates self-clock mode wakeup interrupt. ? exit wait mode in scm using pll clock (f scm ) as system clock, ? continue to perform a additional clock quality checks until oscclk is o.k. again. table 4-11. outcome of clock loss in wait mode (continued) cme scme scmie crg actions chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 193 figure 4-24. stop mode entry/exit sequence exit stop w. cmreset exit stop mode enter scm exit stop mode core req?s stop mode. clear pllsel, disable pll cme=1 ? int ? cm fail ? scme=1 ? scmie=1 ? continue w. normal op no no no no yes yes yes yes yes generate scm interrupt (wakeup from stop) enter stop mode exit stop w. ext.reset wait mode left due to external clock ok ? scme=1 ? enter scm yes no yes exit stop w. cmreset no no no pstp=1 ? int ? yes no yes exit stop mode exit stop mode scm=1 ? enter scm no yes chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 194 freescale semiconductor 4.4.10.1 wake-up from pseudo-stop (pstp=1) wake-up from pseudo-st op is the same as wake-up from wait mode. there are also three different scenarios for the crg to restar t the mcu from pseudo-stop mode: ? external reset ? clock monitor fail ? wake-up interrupt if the mcu gets an external rese t during pseudo-stop mode active, th e crg asynchronously restores all configuration bits in the register sp ace to its default settings and starts the reset generator. after completing the reset sequence processi ng begins by fetching the normal reset v ector. pseudo-stop mode is exited and the mcu is in run mode again. if the clock monitor is enabled (cme = 1) the mcu is able to leave pseudo- stop mode when loss of oscillator/external clock is detected by a clock monitor fail. if the scme bit is not asserted the crg generates a clock monitor fail reset (cmreset). the crg?s beha vior for cmreset is the same compared to external reset, but anot her reset vector is fetched after comp letion of the reset sequence. if the scme bit is asserted the crg ge nerates a scm interrupt if enable d (scmie=1). after generating the interrupt the crg enters self-clock mode and starts the clock quality checker (see section 4.4.4, ?clock quality checker ?). then the mcu continues with normal ope ration. if the scm inte rrupt is blocked by scmie = 0, the scmif flag will be asserted but the crg will not wake-up from pseudo-stop mode. if any other interrupt source (e.g. rti) triggers exit from pseudo-stop m ode the mcu immediately continues with normal op eration. because the pll has been pow ered-down during stop mode the pllsel bit is cleared and the mcu runs on oscclk after leaving stop mode. th e software must set the pllsel bit again, in order to switch system and core clocks to the pllclk. table 4-12 summarizes the outcome of a clock loss while in pseudo-stop mode. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 195 table 4-12. outcome of clock loss in pseudo-stop mode cme scme scmie crg actions 0 x x clock failure --> no action, clock loss not detected. 1 0 x clock failure --> crg performs clock monitor reset immediately 1 1 0 clock monitor failure --> scenario 1: oscclk recovers prior to exiting pseudo-stop mode. ? mcu remains in pseudo-stop mode, ? vreg enabled, ? pll enabled, ? scm activated, ? start clock quality check, ? set scmif interrupt flag. some time later oscclk recovers. ? cm no longer indicates a failure, ? 4096 oscclk cycles later clock quality check indicates clock o.k., ? scm deactivated, ? pll disabled, ? vreg disabled. ? mcu remains in pseudo-stop mode. s ome time later either a wakeup interrupt occurs (no scm interrupt) ? exit pseudo-stop mode using oscclk as system clock (sysclk), ? continue normal operation. or an external reset is applied. ? exit pseudo-stop mode using oscclk as system clock, ? start reset sequence. scenario 2: oscclk does not recover prior to exiting pseudo-stop mode. ? mcu remains in pseudo-stop mode, ? vreg enabled, ? pll enabled, ? scm activated, ? start clock quality check, ? set scmif interrupt flag, ? keep performing clock quality checks (could continue infinitely) while in pseudo-stop mode. s ome time later either a wakeup interrupt occurs (no scm interrupt) ? exit pseudo-stop mode in scm using pll clock (f scm ) as system clock ? continue to perform additional clock quality checks until oscclk is o.k. again. or an external reset is applied. ? exit pseudo-stop mode in scm using pll clock (f scm ) as system clock ? start reset sequence, ? continue to perform additional clock quality checks until oscclk is o.k.again. chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 196 freescale semiconductor 4.4.10.2 wake-up from full stop (pstp=0) the mcu requires an external interrupt or an exte rnal reset in order to wake-up from stop mode. if the mcu gets an external rese t during full stop mode active, th e crg asynchronously restores all configuration bits in the register space to its defa ult settings and will perfo rm a maximum of 50 clock check_windows (see section 4.4.4, ?clock quality checker ?). after completing the clock quality check the crg starts the reset generator. after completing the reset sequence processing begins by fetching the normal reset vector. full stop mode is ex ited and the mcu is in run mode again. if the mcu is woken-up by an interrupt, the cr g will also perform a maximum of 50 clock check_window s (see section 4.4.4, ?clock quality checker ?). if the clock quality check is successful, the crg will release all system and core clocks and will continue with normal operation. if all clock checks within the timeout-window ar e failing, the crg will swit ch to self-clock mode or generate a clock monitor reset (cmreset) depending on the setting of the scme bit. because the pll has been powered- down during stop mode th e pllsel bit is cleare d and the mcu runs on oscclk after leaving stop mode. the software must manually se t the pllsel bit again, in order to switch system and core clocks to the pllclk. note in full stop mode, the clock monitor is disabled and any loss of clock will not be detected. 4.5 resets this section describes how to reset the crgv4 and how the crgv4 its elf controls the reset of the mcu. it explains all special reset requireme nts. because the reset generator for the mcu is part of the crg, this section also describes all automatic actions that occur during or as a re sult of individual reset conditions. the reset values of registers and signals are provided in section 4.3, ?memory map and register 1 1 1 clock failure --> ? vreg enabled, ? pll enabled, ? scm activated, ? start clock quality check, ? scmif set. scmif generates self-clock mode wakeup interrupt. ? exit pseudo-stop mode in scm using pll clock (f scm ) as system clock, ? continue to perform a additional clock quality checks until oscclk is o.k. again. table 4-12. outcome of clock loss in pseudo-stop mode (continued) cme scme scmie crg actions chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 197 definition .? all reset sources are listed in table 4-13 . refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for related vector a ddresses and priorities. the reset sequence is initiated by any of the following events: ? low level is detected at the reset pin (external reset). ? power on is detected. ? low voltage is detected. ? cop watchdog times out. ? clock monitor failure is detected and se lf-clock mode was disabled (scme = 0). upon detection of any reset event, an internal circuit drives the reset pin low for 128 sysclk cycles (see figure 4-25 ). because entry into reset is asynchrono us it does not require a running sysclk. however, the internal reset circuit of the crgv4 ca nnot sequence out of current reset condition without a running sysclk. the number of 128 sysclk cycles might be increased by n = 3 to 6 additional sysclk cycles depending on the internal synchronization latency. after 128+n sysclk cycles the reset pin is released. the reset generator of the crgv4 waits for additional 64 sysclk cycles and then samples the reset pin to determine the originating source. table 4-14 shows which vector will be fetched. note external circuitry connected to the reset pin should not include a large capacitance that would interfere with th e ability of this signal to rise to a valid logic 1 within 64 sysclk cycles after the low drive is released. table 4-13. reset summary reset source local enable power-on reset none low voltage reset none external reset none clock monitor reset pllctl (cme=1, scme=0) cop watchdog reset cop ctl (cr[2:0] nonzero) table 4-14. reset vector selection sampled reset pin (64 cycles after release) clock monitor reset pending cop reset pending vector fetch 1 0 0 por / lvr / external reset 1 1 x clock monitor reset 1 0 1 cop reset 0 x x por / lvr / external reset with rise of reset pin chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 198 freescale semiconductor the internal reset of the mcu remains asserted wh ile the reset generator completes the 192 sysclk long reset sequence. the reset generato r circuitry always makes sure th e internal reset is deasserted synchronously after comple tion of the 192 sysclk cycles. in case the reset pin is externally driven low for more than these 192 sysclk cycles (externa l reset), the internal reset remains asserted too. figure 4-25. reset timing 4.5.1 clock monitor reset the crgv4 generates a clock monitor reset in case all of the following conditions are true: ? clock monitor is enabled (cme=1) ? loss of clock is detected ? self-clock mode is disabled (scme=0) the reset event asynchronously for ces the configuration registers to their de fault settings (see section 4.3, ?memory map and register definition ?). in detail the cme and the scme are reset to logical ?1? (which doesn?t change the state of the cme bit, because it has already been set). as a consequence, the crg immediately enters self-clock mode and starts its internal reset sequenc e. in parallel the clock quality check starts. as soon as clock quality check indicat es a valid oscillator cl ock the crg switches to oscclk and leaves self-clock mode. because the clock quality checker is running in parallel to the reset generator, the crg may leave self-clock mode whil e completing the internal reset sequence. when the reset sequence is finished the crg checks the internally latched state of the clock monitor fail circuit. if a clock monitor fail is indicate d processing begins by fetching th e clock monitor reset vector. 4.5.2 computer operating prop erly watchdog (cop) reset when cop is enabled, the crg expects sequential write of 0x0055 and 0x00aa (in this order) to the armcop register during the select ed time-out period. as soon as this is done, the cop time-out period restarts. if the program fails to do this the crg will generate a reset. also, if any value other than 0x0055 or 0x00aa is written, the crg immedi ately generates a reset. in case windowed cop operation is enabled ) ( ) ( ) ( ) sysclk 128+ n cycles 64 cycles with n being min 3 / max 6 cycles depending on internal synchronization delay crg drives reset pin low possibly sysclk not running possibly reset driven low externally ) ( ( reset reset pin released chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 199 writes (0x0055 or 0x00aa) to the armcop register must occur in the last 25% of the sel ected time-out period. a premature write the crg w ill immediately generate a reset. as soon as the reset sequence is completed the reset generator checks the reset condition. if no clock monitor failure is indicated and the latched state of the cop timeout is true, processing begins by fetching the cop vector. 4.5.3 power-on reset, low voltage reset the on-chip voltage regulator detects when v dd to the mcu has reached a certain level and asserts power-on reset or low voltage reset or both. as soon as a pow er-on reset or low volta ge reset is triggered the crg performs a quality check on the incoming clock signal. as soon as clock quality check indicates a valid oscillator clock si gnal the reset sequence starts using the oscillator cl ock. if after 50 check windows the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock mode. figure 4-26 and figure 4-27 show the power-up sequence for cases when the reset pin is tied to v dd and when the reset pin is held low. figure 4-26. reset pin tied to v dd (by a pull-up resistor) figure 4-27. reset pin held low externally reset internal por 128 sysclk 64 sysclk internal reset clock quality check (no self-clock mode) ) ( ) ( ) ( clock quality check reset internal por internal reset 128 sysclk 64 sysclk (no self-clock mode) ) ( ) ( ) ( chapter 4 clocks and reset generator (crgv4) mc9s12e256 data sheet, rev. 1.08 200 freescale semiconductor 4.6 interrupts the interrupts/reset vectors reque sted by the crg are listed in table 4-15 . refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for related vector addresses and priorities. 4.6.1 real-time interrupt the crgv4 generates a real-time inte rrupt when the selected interrupt time period elapses. rti interrupts are locally disabled by setting the rtie bit to 0. the real-time interrupt flag (rtif) is set to 1 when a timeout occurs, and is cleared to 0 by writing a 1 to the rtif bit. the rti continues to run during pseudo-stop mode if the pre bit is set to 1. this feature can be used for periodic wakeup from pseu do-stop if the rti interrupt is enabled. 4.6.2 pll lock interrupt the crgv4 generates a pll lock interrupt when th e lock condition of the pll has changed, either from a locked state to an unlocked state or vice ve rsa. lock interrupts are locally disabled by setting the lockie bit to 0. the pll lock interrupt flag (l ockif) is set to1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the lockif bit. 4.6.3 self-clock mode interrupt the crgv4 generates a self-clock mode interrupt when the scm condition of the system has changed, either entered or exited self-clock mode. scm conditi ons can only change if the self-clock mode enable bit (scme) is set to 1. scm conditions are caused by a failing clock quality check after power-on reset (por) or low voltage reset (lvr) or recovery from full stop mode (p stp = 0) or clock monitor failure. for details on the clock quality check refer to section 4.4.4, ?clock quality checker .? if the clock monitor is enabled (cme = 1) a loss of external cloc k will also cause a scm condition (scme = 1). scm interrupts are locally disabled by setting the sc mie bit to 0. the scm interr upt flag (scmif) is set to 1 when the scm condition has changed, and is cleared to 0 by writing a 1 to the scmif bit. table 4-15. crg interrupt vectors interrupt source ccr mask local enable real-time interrupt i bit crgint (rtie) lock interrupt i bit crgint (lockie) scm interrupt i bit crgint (scmie) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 201 chapter 5 oscillator (oscv2) 5.1 introduction the oscv2 module provides two alte rnative oscillator concepts: ? a low noise and low power colpitts oscillat or with amplitude li mitation control (alc) ? a robust full swing pierce oscillator with the po ssibility to feed in an external square wave 5.1.1 features the colpitts oscv2 option provi des the following features: ? amplitude limitation control (alc) loop: ? low power consumption and lo w current induced rf emission ? sinusoidal waveform with low rf emission ? low crystal stress (an external damping resistor is not required) ? normal and low amplitude mode for fu rther reduction of power and emission ? an external biasing resistor is not required the pierce osc option provide s the following features: ? wider high frequency operation range ? no dc voltage applied across the crystal ? full rail-to-rail (2.5 v nom inal) swing oscillation wi th low em susceptibility ? fast start up common features: ? clock monitor (cm) ? operation from the v ddpll 2.5 v (nominal) supply rail 5.1.2 modes of operation two modes of operation exist: ? amplitude limitation controlled colpitts oscillator mode suitable for power and emission critical applications ? full swing pierce oscillator mode that can also be used to feed in an externally generated square wave suitable for high frequenc y operation and harsh environments chapter 5 oscillator (oscv2) mc9s12e256 data sheet, rev. 1.08 202 freescale semiconductor 5.2 external signal description this section lists and describes th e signals that connect off chip. 5.2.1 v ddpll and v sspll ? pll operating voltage, pll ground these pins provide the operating voltage (v ddpll ) and ground (v sspll ) for the oscv2 circuitry. this allows the supply voltage to the os cv2 to be independently bypassed. 5.2.2 extal and xtal ? clock/crystal source pins these pins provide the interface for either a crystal or a cmos compatib le clock to control the internal clock generator circuitry. exta l is the external cl ock input or the input to the crystal osc illator amplifier. xtal is the output of the crystal osci llator amplifier. all the mcu intern al system clocks are derived from the extal input frequency. in full stop mode (pstp = 0) the extal pin is pulled down by an internal resistor of typical 200 k ? . note freescale semiconductor recommends an evaluation of the application board and chosen resonator or crysta l by the resonator or crystal supplier . the crystal circuit is changed from standard. the colpitts circuit is not suited fo r overtone resonators and crystals. figure 5-1. colpitts oscillator connections (xclks = 0) note the pierce circuit is not su ited for overtone resonato rs and crystals without a careful component selection. mcu c2 extal xtal v sspll c1 cdc* crystal or ceramic resonator * due to the nature of a translated ground colpitts oscillator a dc voltage bias is applied to the crystal. please contact the crystal manu facturer for crystal dc bias conditions and recommended capacitor value cdc. chapter 5 oscillator (oscv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 203 figure 5-2. pierce oscillator connections (xclks = 1) figure 5-3. external clock connections (xclks = 1) 5.2.3 xclks ? colpitts/pierce oscillator selection signal the xclks is an input signa l which controls whether a crystal in combination with the internal colpitts (low power) oscillator is us ed or whether the pierce oscillator/external clock circuitry is used. the xclks signal is sampled during reset with the rising edge of reset . table 5-1 lists the state coding of the sampled xclks signal. refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for polarity of the xclks pin. table 5-1. clock selection based on xclks xclks description 0 colpitts oscillator selected 1 pierce oscillator/external clock selected mcu extal xtal rs* rb v sspll crystal or ceramic resonator c4 c3 * rs can be zero (shorted) when used with higher frequency crystals. refer to manufacturer?s data. mcu extal xtal cmos-compatible external oscillator not connected (v ddpll level) chapter 5 oscillator (oscv2) mc9s12e256 data sheet, rev. 1.08 204 freescale semiconductor 5.3 memory map and register definition the crg contains the registers a nd associated bits for controlli ng and monitoring the oscv2 module. 5.4 functional description the oscv2 block has two external pins, extal and xtal. the oscillat or input pin, extal, is intended to be connected to either a crystal or an external clock source. the selectio n of colpitts oscillator or pierce oscillator/external clock depends on the xclks signal which is sample d during reset. the xtal pin is an output signal that provide s crystal circuit feedback. a buffered extal signal, oscclk, becomes the intern al reference clock. to improve noise immunity, the oscillator is powered by the v ddpll and v sspll power supply pins. the pierce oscillator can be used for higher frequencies compared to the low power colpitts oscillator. 5.4.1 amplitude limitation control (alc) the colpitts oscillator is equipped with a feedback system which does not wa ste current by generating harmonics. its configuration is ?c olpitts oscillator with translated ground.? the transconductor used is driven by a current source under the control of a peak detector which will measure the amplitude of the ac signal appearing on extal node in order to implement an amplit ude limitation control (alc) loop. the alc loop is in charge of reducin g the quiescent current in the transc onductor as a result of an increase in the oscillation amplitude . the oscillation amplitude can be limited to two va lues. the normal amplitude which is intended for non power saving modes and a small amplitude which is intended for low power operation modes. please refer to chapter 4, ?clocks and reset generator (crgv4)? for the control and assignment of the amplitude value to operation modes. 5.4.2 clock monitor (cm) the clock monitor circuit is based on an internal resistor-capacitor (rc) time delay so that it can operate without any mcu clocks. if no oscclk edges are detected within this rc time delay, the clock monitor indicates a failure which asserts se lf clock mode or generates a syst em reset depending on the state of scme bit. if the clock monitor is disabled or the pres ence of clocks is detected no failure is indicated.the clock monitor function is en abled/disabled by the cme control bit, described in chapter 4, ?clocks and reset generator (crgv4)? . 5.5 interrupts oscv2 contains a clock monitor, which can trigger an in terrupt or reset. the cont rol bits and status bits for the clock monitor are described in chapter 4, ?clocks and reset generator (crgv4)? . mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 205 chapter 6 analog-to-digital converter (atd10b16cv4) 6.1 introduction the atd10b16c is a 16-channel, 10-bit, multiplexe d input successive approxi mation analog-to-digital converter. refer to appendix a, ?electrical characteristics? for atd accuracy. 6.1.1 features ? 8-/10-bit resolution ?7 s, 10-bit single conversion time ? sample buffer amplifier ? programmable sample time ? left/right justified, sign ed/unsigned result data ? external trigger control ? conversion completion interrupt generation ? analog input multiplexer for 16 analog input channels ? analog/digital input pin multiplexing ? 1 to 16 conversion sequence lengths ? continuous conversion mode ? multiple channel scans ? configurable external trigger functionality on any ad channel or any of four additional trigger inputs. the four additional trigger inputs can be chip external or internal. refer to device specification for availa bility and connectivity ? configurable location for channel wrap around (whe n converting multiple channels in a sequence) 6.1.2 modes of operation there is software programmabl e selection between performing single or continuous conversion on a single channel or multiple channels . 6.1.3 block diagram refer to figure 6-1 for a block diagram of the atd10b16c block. chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 206 freescale semiconductor figure 6-1. atd10b16c block diagram v ssa an8 atd10b16c analog mux mode and successive approximation register (sar) results at d 0 at d 1 at d 2 at d 3 at d 4 at d 5 at d 6 at d 7 and dac sample & hold 1 1 v dda v rl v rh sequence complete interrupt + - comparator clock prescaler bus clock atd clock at d 8 at d 9 at d 1 0 at d 1 1 at d 1 2 at d 1 3 at d 1 4 at d 1 5 an7 an6 an5 an4 an3 an2 an1 an0 an9 an10 an11 an12 an13 an14 an15 etrig0 etrig1 etrig2 etrig3 timing control atddien atdctl1 portad trigger mux (see chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for availability and connectivity) chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 207 6.2 external signal description this section lists all input s to the atd10b16c block. 6.2.1 an x ( x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) ? analog input channel x pins this pin serves as the analog input channel x . it can also be configured as general-purpose digital input and/or external trigger for the atd conversion. 6.2.2 etrig3, etrig2, etrig1, etrig0 ? external trigger pins these inputs can be configured to serve as an external trigger for the atd conversion. refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for availability and connectivity of these inputs. 6.2.3 v rh , v rl ? high reference voltage pin, low reference voltage pin v rh is the high reference voltage, v rl is the low reference voltage for atd conversion. 6.2.4 v dda , v ssa ? analog circuitry power supply pins these pins are the power supplies for the analog circuitry of the atd10b16cv4 block. 6.3 memory map and register definition this section provides a detailed description of all registers accessi ble in the atd10b16c. 6.3.1 module memory map table 6-1 gives an overview of all atd10b16c registers chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 208 freescale semiconductor . note register address = base address + a ddress offset, where the base address is defined at the mcu level and the a ddress offset is defined at the module level. table 6-1. atd10b16cv4 memory map address offset use access 0x0000 atd control register 0 (atdctl0) r/w 0x0001 atd control register 1 (atdctl1) r/w 0x0002 atd control register 2 (atdctl2) r/w 0x0003 atd control register 3 (atdctl3) r/w 0x0004 atd control register 4 (atdctl4) r/w 0x0005 atd control register 5 (atdctl5) r/w 0x0006 atd status register 0 (atdstat0) r/w 0x0007 unimplemented 0x0008 atd test register 0 (atdtest0) 1 1 atdtest0 is intended for factory test purposes only. r 0x0009 atd test register 1 (atdtest1) r/w 0x000a atd status register 2 (atdstat2) r 0x000b atd status register 1 (atdstat1) r 0x000c atd input enable register 0 (atddien0) r/w 0x000d atd input enable register 1 (atddien1) r/w 0x000e port data register 0 (portad0) r 0x000f port data register 1 (portad1) r 0x0010, 0x0011 atd result register 0 (atddr0h, atddr0l) r/w 0x0012, 0x0013 atd result register 1 (atddr1h, atddr1l) r/w 0x0014, 0x0015 atd result register 2 (atddr2h, atddr2l) r/w 0x0016, 0x0017 atd result register 3 (atddr3h, atddr3l) r/w 0x0018, 0x0019 atd result register 4 (atddr4h, atddr4l) r/w 0x001a, 0x001b atd result register 5 (atddr5h, atddr5l) r/w 0x001c, 0x001d atd result register 6 (atddr6h, atddr6l) r/w 0x001e, 0x001f atd result register 7 (atddr7h, atddr7l) r/w 0x0020, 0x0021 atd result register 8 (atddr8h, atddr8l) r/w 0x0022, 0x0023 atd result register 9 (atddr9h, atddr9l) r/w 0x0024, 0x0025 atd result register 10 (atddr10h, atddr10l) r/w 0x0026, 0x0027 atd result register 11 (atddr11h, atddr11l) r/w 0x0028, 0x0029 atd result register 12 (atddr12h, atddr12l) r/w 0x002a, 0x002b atd result register 13 (atddr13h, atddr13l) r/w 0x002c, 0x002d atd result register 14 (atddr14h, atddr14l) r/w 0x002e, 0x002f atd result register 15 (atddr15h, atddr15l) r/w chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 209 6.3.2 register descriptions this section describes in address order all th e atd10b16c registers a nd their individual bits. register name bit 7654321bit 0 0x0000 at d c t l 0 r0000 wrap3 wrap2 wrap1 wrap0 w 0x0001 at d c t l 1 r etrigsel 000 etrigch3 etrigch2 etrigch1 etrigch0 w 0x0002 at d c t l 2 r adpu affc awai etrigl e etrigp etrige ascie ascif w 0x0003 at d c t l 3 r0 s8c s4c s2c s1c fifo frz1 frz0 w 0x0004 at d c t l 4 r sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 w 0x0005 at d c t l 5 r djm dsgn scan mult cd cc cb ca w 0x0006 at d s tat 0 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w 0x0007 unimplemented r w 0x0008 atdtest0 r unimplemented w 0x0009 atdtest1 r unimplemented sc w 0x000a at d s tat 2 r ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 w 0x000b at d s tat 1 r ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 w 0x000c atddien0 r ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 w = unimplemented or reserved u = unaffected figure 6-2. atd register summary chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 210 freescale semiconductor 6.3.2.1 atd control re gister 0 (atdctl0) writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime 0x000d atddien1 r ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 w 0x000e portad0 r ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 w 0x000f portad1 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w r bit 9 msb bit 7 msb bit 8 bit 6 bit 7 bit 5 bit 6 bit 4 bit 5 bit 3 bit 4 bit 2 bit 3 bit 1 bit 2 bit 0 0x0010?0x002f atddrxh? atddrxl w r bit 1 u bit 0 u 0 0 0 0 0 0 0 0 0 0 0 0 w 76543210 r0 0 0 0 wrap3 wrap2 wrap1 wrap0 w reset00001111 = unimplemented or reserved figure 6-3. atd control register 0 (atdctl0) table 6-2. atdctl0 field descriptions field description 3:0 wrap[3:0] wrap around channel select bits ? these bits determine the channel for wrap around when doing multi-channel conversions. the coding is summarized in ta bl e 6 - 3 . register name bit 7654321bit 0 = unimplemented or reserved u = unaffected figure 6-2. atd register summary (continued) chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 211 6.3.2.2 atd control re gister 1 (atdctl1) writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime table 6-3. multi-channel wrap around coding wrap3 wrap2 wrap1 wrap0 multiple channel conversions (mult = 1) wrap around to an0 after converting 0000 reserved 0001 an1 0010 an2 0011 an3 0100 an4 0101 an5 0110 an6 0111 an7 1000 an8 1001 an9 1010 an10 1011 an11 1100 an12 1101 an13 1110 an14 1111 an15 76543210 r etrigsel 000 etrigch3 etrigch2 etrigch1 etrigch0 w reset00001111 = unimplemented or reserved figure 6-4. atd control register 1 (atdctl1) table 6-4. atdctl1 field descriptions field description 7 etrigsel external trigger source select ? this bit selects the external trigger source to be either one of the ad channels or one of the etri g[3:0] inputs. see device specificatio n for availability and connectivity of etrig[3:0] inputs. if etrig[3:0] input option is not ava ilable, writing a 1 to etrisel only sets the bit but has no effect, that means one of the ad channels (selected by etrigch[3:0]) remains the source for external trigger. the coding is summarized in ta b l e 6 - 5 . 3:0 etrigch[3:0] external trigger channel select ? these bits select one of the ad c hannels or one of the etrig[3:0] inputs as source for the external trigger. the coding is summarized in ta bl e 6 - 5 . chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 212 freescale semiconductor table 6-5. external trigger channel select coding etrigsel etrigch3 etrigc h2 etrigch1 etrigch0 external trigger source 000 0 0 an0 000 0 1 an1 000 1 0 an2 000 1 1 an3 001 0 0 an4 001 0 1 an5 001 1 0 an6 001 1 1 an7 010 0 0 an8 010 0 1 an9 010 1 0 an10 010 1 1 an11 011 0 0 an12 011 0 1 an13 011 1 0 an14 011 1 1 an15 100 0 0 etrig0 1 1 only if etrig[3:0] input option is available (see device specification), else etrisel is ignored, that means external trigger source remains on one of the ad channels selected by etrigch[3:0] 100 0 1 etrig1 1 100 1 0 etrig2 1 100 1 1 etrig3 1 1 0 1 x x reserved 11xxx reserved chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 213 6.3.2.3 atd control re gister 2 (atdctl2) this register controls power down, inte rrupt and external trigge r. writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime 76543210 r adpu affc awai etrigle etrigp etrige ascie ascif w reset00000000 = unimplemented or reserved figure 6-5. atd control register 2 (atdctl2) table 6-6. atdctl2 field descriptions field description 7 adpu atd power down ? this bit provides on/off control over the atd10b16c block allowing reduced mcu power consumption. because analog electronic is turned off when powered down, the atd requires a recovery time period after adpu bit is enabled. 0 power down atd 1 normal atd functionality 6 affc atd fast flag clear all 0 atd flag clearing operates normally (read the status regi ster atdstat1 before reading the result register to clear the associate ccf flag). 1 changes all atd conversion complete flags to a fast clear sequence. any access to a result register will cause the associate ccf fl ag to clear automatically. 5 awai atd power down in wait mode ? when entering wait mode this bi t provides on/off control over the atd10b16c block allowing reduced mcu power. because analog electronic is turned off when powered down, the atd requires a recovery time period after exit from wait mode. 0 atd continues to run in wait mode 1 halt conversion and power down atd during wait mode after exiting wait mode with an interrupt conversion wil l resume. but due to the recovery time the result of this conversion should be ignored. 4 etrigle external trigger level/edge control ? this bit controls the sensitivity of the external trigger signal. see ta b l e 6 - 7 for details. 3 etrigp external trigger polarity ? this bit controls the polarity of the external trigger signal. see ta bl e 6 - 7 for details. 2 etrige external trigger mode enable ? this bit enables the external trigger on one of the ad channels or one of the etrig[3:0] inputs as described in ta b l e 6 - 5 . if external trigger source is one of the ad channels, the digital input buffer of this channel is enabled. the external trigger allows to synchronize the start of conversion with external events. 0 disable external trigger 1 enable external trigger chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 214 freescale semiconductor 1 ascie atd sequence complete interrupt enable 0 atd sequence complete interrupt requests are disabled. 1 atd interrupt will be requested whenever ascif = 1 is set. 0 ascif atd sequence complete interrupt flag ? if ascie = 1 the ascif flag equals the scf flag (see section 6.3.2.7, ?atd status register 0 (atdstat0)? ), else ascif reads zero. writes have no effect. 0 no atd interrupt occurred 1 atd sequence complete interrupt pending table 6-7. external trigger configurations etrigle etrigp external trigger sensitivity 0 0 falling edge 0 1 ring edge 1 0 low level 1 1 high level table 6-6. atdctl2 field d escriptions (continued) field description chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 215 6.3.2.4 atd control re gister 3 (atdctl3) this register controls the conversion sequence length, fifo for results register s and behavior in freeze mode. writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime 76543210 r0 s8c s4c s2c s1c fifo frz1 frz0 w reset00100000 = unimplemented or reserved figure 6-6. atd control register 3 (atdctl3) table 6-8. atdctl3 field descriptions field description 6 s8c conversion sequence length ? this bit controls the number of conversions per sequence. ta b l e 6 - 9 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 5 s4c conversion sequence length ? this bit controls the number of conversions per sequence. ta b l e 6 - 9 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 4 s2c conversion sequence length ? this bit controls the number of conversions per sequence. ta b l e 6 - 9 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 3 s1c conversion sequence length ? this bit controls the number of conversions per sequence. ta b l e 6 - 9 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 2 fifo result register fifo mode ?if this bit is zero (non-fifo mode), the a/d conversion results map into the result registers based on the conversi on sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. if this bit is one (fifo mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion result s are placed in consecutive result re gisters. in a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register file. the conversion counter value (cc3-0 in atdstat0) can be used to determine wher e in the result register file, the current conversion result will be placed. aborting a conversion or starting a new conversion by write to an atdctl register (atdctl5-0) clears the conversion counter even if fifo=1. so the first result of a new conversion sequenc e, started by writing to atdctl5, will always be place in the first result r egister (atdddr0). intended usage of fifo mode is continuos conversion (scan=1) or triggered conversion (etrig=1). finally, which result registers hold valid data can be tr acked using the conversion complete flags. fast flag clear mode may or may not be useful in a particular application to track valid data. 0 conversion results are placed in the corresponding result register up to the selected sequence length. 1 conversion results are placed in consecutiv e result registers (wrap around at end). 1:0 frz[1:0] background debug freeze enable ? when debugging an application, it is useful in many cases to have the atd pause when a breakpoint (freeze mode) is encounter ed. these 2 bits determine how the atd will respond to a breakpoint as shown in ta bl e 6 - 1 0 . leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately fr ozen conversion depending on the length of the freeze period. chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 216 freescale semiconductor 7 table 6-9. conversion sequence length coding s8c s4c s2c s1c number of conversions per sequence 0000 16 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 table 6-10. atd behavior in freeze mode (breakpoint) frz1 frz0 behavior in freeze mode 0 0 continue conversion 01 reserved 1 0 finish current conversion, then freeze 1 1 freeze immediately chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 217 6.3.2.5 atd control re gister 4 (atdctl4) this register selects the conversion clock frequency, the lengt h of the second phase of the sample time and the resolution of the a/d conversion (i .e., 8-bits or 10-bits). writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime 76543210 r sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 w reset00000101 figure 6-7. atd control register 4 (atdctl4) table 6-11. atdctl4 field descriptions field description 7 sres8 a/d resolution select ? this bit selects the resoluti on of a/d conversion results as either 8 or 10 bits. the a/d converter has an accuracy of 10 bits. however, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10 bit resolution 1 8 bit resolution 6:5 smp[1:0] sample time select ?these two bits select the length of the seco nd phase of the sample time in units of atd conversion clock cycles. note that th e atd conversion clock period is itself a function of the prescaler value (bits prs4-0). the sample ti me consists of two phases. the first phas e is two atd conversion clock cycles long and transfers the sample quickly (via the buffer am plifier) onto the a/d machine?s storage node. the second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. ta b l e 6 - 1 2 lists the lengths available for the second sample phase. 4:0 prs[4:0] atd clock prescaler ? these 5 bits are the binary value prescaler value prs. the atd conversion clock frequency is calculated as follows: note: the maximum atd conversion clock frequency is half th e bus clock. the default (after reset) prescaler value is 5 which results in a default atd conversion clock frequency that is bus clock divided by 12. ta b l e 6 - 1 3 illustrates the divide-by operation and the appropriate range of the bus clock. table 6-12. sample time select smp1 smp0 length of 2nd phase of sample time 0 0 2 a/d conversion clock periods 0 1 4 a/d conversion clock periods 1 0 8 a/d conversion clock periods 1 1 16 a/d conversion clock periods atdclock busclock [] prs 1 + [] -------------------------------- 0.5 = chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 218 freescale semiconductor table 6-13. clock prescaler values prescale value total divisor value max. bus clock 1 1 maximum atd conversion clock frequency is 2 mh z. the maximum allowed bus clock frequency is shown in this column. min. bus clock 2 2 minimum atd conversion clock frequency is 500 khz. the minimum allowed bus clock frequency is shown in this column. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 divide by 2 divide by 4 divide by 6 divide by 8 divide by 10 divide by 12 divide by 14 divide by 16 divide by 18 divide by 20 divide by 22 divide by 24 divide by 26 divide by 28 divide by 30 divide by 32 divide by 34 divide by 36 divide by 38 divide by 40 divide by 42 divide by 44 divide by 46 divide by 48 divide by 50 divide by 52 divide by 54 divide by 56 divide by 58 divide by 60 divide by 62 divide by 64 4 mhz 8 mhz 12 mhz 16 mhz 20 mhz 24 mhz 28 mhz 32 mhz 36 mhz 40 mhz 44 mhz 48 mhz 52 mhz 56 mhz 60 mhz 64 mhz 68 mhz 72 mhz 76 mhz 80 mhz 84 mhz 88 mhz 92 mhz 96 mhz 100 mhz 104 mhz 108 mhz 112 mhz 116 mhz 120 mhz 124 mhz 128 mhz 1 mhz 2 mhz 3 mhz 4 mhz 5 mhz 6 mhz 7 mhz 8 mhz 9 mhz 10 mhz 11 mhz 12 mhz 13 mhz 14 mhz 15 mhz 16 mhz 17 mhz 18 mhz 19 mhz 20 mhz 21 mhz 22 mhz 23 mhz 24 mhz 25 mhz 26 mhz 27 mhz 28 mhz 29 mhz 30 mhz 31 mhz 32 mhz chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 219 6.3.2.6 atd control re gister 5 (atdctl5) this register selects the t ype of conversion sequence a nd the analog input channels sampled. writes to this register will abort current convers ion sequence and start a new conversi on sequence. if external trigger is enabled (etrige = 1) an initial write to atdctl5 is required to allow starti ng of a conversion sequence which will then occur on each trigger event. star t of conversion means the beginning of the sampling phase. read: anytime write: anytime 76543210 r djm dsgn scan mult cd cc cb ca w reset00000000 figure 6-8. atd control register 5 (atdctl5) table 6-14. atdctl5 field descriptions field description 7 djm result register data justification ? this bit controls justification of co nversion data in the result registers. see section 6.3.2.16, ?atd conversi on result registers (atddrx)? for details. 0 left justified data in the result registers. 1 right justified data in the result registers. 6 dsgn result register data signed or unsigned representation ? this bit selects between signed and unsigned conversion data representation in the result register s. signed data is represented as 2?s complement. signed data is not available in right justif ication. see chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 220 freescale semiconductor 3:0 c[d:a} analog input channel select code ? these bits select the analog input channel(s) whose signals are sampled and converted to digital codes. ta bl e 6 - 1 7 lists the coding used to select the various analog input channels. in the case of single channel conversions (mult = 0), this selection code specified the channel to be examined. in the case of multiple channel conversions (mult = 1), this selection code represents the first channel to be examined in the conversion sequence. subsequent channels are determined by incrementing the channel selection code or wrapping around to an0 (after converting the channel defined by the wrap around channel select bits wrap[3:0] in atdctl0). in case starting with a channel number higher than the one defined by wrap[3:0] the first wrap ar ound will be an15 to an0. table 6-15. available result data formats . sres8 djm dsgn result data formats description and bus bit mapping 1 1 1 0 0 0 0 0 1 0 0 1 0 1 x 0 1 x 8-bit / left justified / unsigned ? bits 15:8 8-bit / left justified / signed ? bits 15:8 8-bit / right justified / unsigned ? bits 7:0 10-bit / left justified / unsigned ? bits 15:6 10-bit / left justified / signed -? bits 15:6 10-bit / right justified / unsigned ? bits 9:0 table 6-16. left justified, signed and unsigned atd output codes. input signal v rl = 0 volts v rh = 5.12 volts signed 8-bit codes unsigned 8-bit codes signed 10-bit codes unsigned 10-bit codes 5.120 volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 7f 7f 7e 01 00 ff 81 80 ff ff fe 81 80 7f 01 00 7fc0 7f00 7e00 0100 0000 ff00 8100 8000 ffc0 ff00 fe00 8100 8000 7f00 0100 0000 table 6-14. atdctl5 field descriptions (continued) field description chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 221 table 6-17. analog input channel select coding cd cc cb ca analog input channel 00 0 0 an0 00 0 1 an1 00 1 0 an2 00 1 1 an3 01 0 0 an4 01 0 1 an5 01 1 0 an6 01 1 1 an7 10 0 0 an8 10 0 1 an9 10 1 0 an10 10 1 1 an11 11 0 0 an12 11 0 1 an13 11 1 0 an14 11 1 1 an15 chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 222 freescale semiconductor 6.3.2.7 atd status register 0 (atdstat0) this read-only register contains the sequence complete fl ag, overrun flags for exte rnal trigger and fifo mode, and the conversion counter. read: anytime write: anytime (no effect on cc[3:0]) 76543210 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w reset00000000 = unimplemented or reserved figure 6-9. atd status register 0 (atdstat0) table 6-18. atdstat0 field descriptions field description 7 scf sequence complete flag ? this flag is set upon completion of a conversion sequence. if conversion sequences are continuously performed (scan = 1), the flag is set after each one is completed. this flag is cleared when one of the following occurs: write ?1? to scf write to atdctl5 (a new conversion sequence is started) if affc = 1 and read of a result register 0 conversion sequence not completed 1 conversion sequence has completed 5 etorf external trigger overrun flag ?while in edge trigger mode (etrigle = 0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. th is flag is cleared when one of the following occurs: write ?1? to etorf write to atdctl0,1,2,3,4 (a conversion sequence is aborted) write to atdctl5 (a new conversion sequence is started) 0 no external trigger over run error has occurred 1 external trigger over run error has occurred chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 223 6.3.2.8 reserved register 0 (atdtest0) read: anytime, returns unpredictable values write: anytime in special modes, unimplemented in normal modes note writing to this register when in special modes can alter functionality. 4 fifor fifo over run flag ? this bit indicates that a result regist er has been written to before its associated conversion complete flag (ccf) has been cleared. this flag is most useful when using the fifo mode because the flag potentially indicates that result registers are out of sync with the input channels. however, it is also practical for non-fifo modes, and indicates that a result register has been over written before it has been read (i.e., the old data has been lost). this flag is cleared when one of the following occurs: write ?1? to fifor start a new conversion sequence (write to atdctl5 or external trigger) 0 no over run has occurred 1 overrun condition exists (result register has be en written while associated ccfx flag remained set) 3:0 cc[3:0} conversion counter ? these 4 read-only bits are the binary value of the conversion counter. the conversion counter points to the result register that will receive the result of the current conversion. for example, cc3 = 0, cc2 = 1, cc1 = 1, cc0 = 0 indicates that the result of the current conversion will be in atd result register 6. if in non-fifo mode (fifo = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. if in fifo mo de (fifo = 1) the register counter is not initialized. the conversion counters wraps around when its maximum value is reached. aborting a conversion or starting a new conversion by write to an atdctl register (atdctl5-0) clears the conversion counter even if fifo=1. 76543210 ruuuuuuuu w reset10000000 = unimplemented or reserved u = unaffected figure 6-10. reserved register 0 (atdtest0) table 6-18. atdstat0 field descriptions (continued) field description chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 224 freescale semiconductor 6.3.2.9 atd test register 1 (atdtest1) this register contains the sc bit used to enable special channel conversions. read: anytime, returns unpredictable values for bit 7 and bit 6 write: anytime note writing to this register when in special modes can alter functionality. 76543210 ruuuuuuu sc w reset00000000 = unimplemented or reserved u = unaffected figure 6-11. reserved register 1 (atdtest1) table 6-19. atdtest1 field descriptions field description 0 sc special channel conversion bit ? if this bit is set, then special channel conversion can be selected using cc, cb, and ca of atdctl5. ta bl e 6 - 2 0 lists the coding. 0 special channel conversions disabled 1 special channel conversions enabled table 6-20. special channel select coding sc cd cc cb ca analog input channel 100 x x reserved 101 0 0 v rh 101 0 1 v rl 101 1 0 (v rh +v rl ) / 2 101 1 1 reserved 11x x x reserved chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 225 6.3.2.10 atd status register 2 (atdstat2) this read-only register contains the conversion complete flags ccf15 to ccf8. read: anytime write: anytime, no effect 76543210 r ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 w reset00000000 = unimplemented or reserved figure 6-12. atd status register 2 (atdstat2) table 6-21. atdstat2 field descriptions field description 7:0 ccf[15:8] conversion complete flag bits ? a conversion complete flag is set at the end of each conversion in a conversion sequence. the flags are associated with the co nversion position in a sequence (and also the result register number). therefore, ccf8 is set when the ninth conversion in a sequence is complete and the result is available in result register atddr8; ccf9 is set when the tenth conversion in a sequence is complete and the result is available in atddr9, and so forth. a flag cc fx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when one of the following occurs: write to atdctl5 (a new conversion sequence is started) if affc = 0 and read of atdstat2 followed by read of result register atddrx if affc = 1 and read of result register atddrx in case of a concurrent set and clear on ccfx: the cl earing by method a) will overwrite the set. the clearing by methods b) or c) will be overwritten by the set. 0 conversion number x not completed 1 conversion number x has completed, result ready in atddrx chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 226 freescale semiconductor 6.3.2.11 atd status register 1 (atdstat1) this read-only register contains the conversion complete flags ccf7 to ccf0 read: anytime write: anytime, no effect 76543210 r ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 w reset00000000 = unimplemented or reserved figure 6-13. atd status register 1 (atdstat1) table 6-22. atdstat1 field descriptions field description 7:0 ccf[7:0] conversion complete flag bits ? a conversion complete flag is se t at the end of each conversion in a conversion sequence. the flags are associated with the co nversion position in a sequence (and also the result register number). therefore, ccf0 is set when the first conversion in a sequence is complete and the result is available in result register atddr0; ccf1 is set when the second conversion in a sequence is complete and the result is available in atddr1, and so forth. a ccf flag is cleared when one of the following occurs: write to atdctl5 (a new conversion sequence is started) if affc = 0 and read of atdstat1 followed by read of result register atddrx if affc = 1 and read of result register atddrx in case of a concurrent set and clear on ccfx: the cl earing by method a) will overwrite the set. the clearing by methods b) or c) will be overwritten by the set. conversion number x not completed conversion number x has completed, result ready in atddrx chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 227 6.3.2.12 atd input enable register 0 (atddien0) read: anytime write: anytime 6.3.2.13 atd input enable register 1 (atddien1) read: anytime write: anytime 76543210 r ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 w reset00000000 figure 6-14. atd input enab le register 0 (atddien0) table 6-23. atddien0 field descriptions field description 7:0 ien[15:8] atd digital input enable on channel bits ? this bit controls the digital input buffer from the analog input pin (anx) to ptadx data register. 0 disable digital input buffer to ptadx 1 enable digital input buffer to ptadx. note: setting this bit will enable the corresponding digital input buffer continuously. if this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. 76543210 r ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 w reset00000000 figure 6-15. atd input enab le register 1 (atddien1) table 6-24. atddien1 field descriptions field description 7:0 ien[7:0] atd digital input enable on channel bits ? this bit controls the digital input buffer from the analog input pin (anx) to ptadx data register. 0 disable digital input buffer to ptadx 1 enable digital input buffer to ptadx. note: setting this bit will enable the corresponding digital input buffer continuously. if this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 228 freescale semiconductor 6.3.2.14 port data register 0 (portad0) the data port associated with the atd is input-onl y. the port pins are shared with the analog a/d inputs an[15:8]. read: anytime write: anytime, no effect the a/d input channels may be used for general-purpose digital input. 76543210 r ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 w reset11111111 pin function an15 an14 an13 an12 an11 an10 an9 an8 = unimplemented or reserved figure 6-16. port data register 0 (portad0) table 6-25. portad0 field descriptions field description 7:0 ptad[15:8] a/d channel x (anx) digital input bits ? if the digital input buffer on the anx pin is enabled (ienx = 1) or channel x is enabled as external trigger (etrige = 1, etrigch[3-0] = x, etrigsel = 0) read returns the logic level on anx pin (signal potentials not meeting v il or v ih specifications will have an indeterminate value)). if the digital input buffers are disabled (ienx = 0) and channel x is not enabled as external trigger, read returns a ?1?. reset sets all portad0 bits to ?1?. chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 229 6.3.2.15 port data register 1 (portad1) the data port associated with the atd is input-onl y. the port pins are shared with the analog a/d inputs an7-0. read: anytime write: anytime, no effect the a/d input channels may be used for general-purpose digital input. 76543210 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w reset11111111 pin function an 7 an6 an5 an4 an3 an2 an1 an0 = unimplemented or reserved figure 6-17. port data register 1 (portad1) table 6-26. portad1 field descriptions field description 7:0 ptad[7:8] a/d channel x (anx) digital input bits ? if the digital input buffer on the anx pin is enabled (ienx=1) or channel x is enabled as external trigger (etrige = 1, etrigch[3-0] = x, etrigsel = 0) read returns the logic level on anx pin (signal potentials not meeting v il or v ih specifications will have an indeterminate value)). if the digital input buffers are disabled (ienx = 0) and channel x is not enabled as external trigger, read returns a ?1?. reset sets all portad1 bits to ?1?. chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 230 freescale semiconductor 6.3.2.16 atd conversion result registers (atddrx) the a/d conversion results are stored in 16 read-only resu lt registers. the result data is formatted in the result registers bases on two criteria. first there is left and right justific ation; this select ion is made using the djm control bit in atdctl5. sec ond there is signed and unsigned data ; this selection is made using the dsgn control bit in atdctl5. signed data is stored in 2?s complement format and only exists in left justified format. signed data selected for right justified format is ignored. read: anytime write: anytime in special mode , unimplemented in normal modes 6.3.2.16.1 left just ified result data 76543210 r (10-bit) r (8-bit) bit 9 msb bit 7 msb bit 8 bit 6 bit 7 bit 5 bit 6 bit 4 bit 5 bit 3 bit 4 bit 2 bit 3 bit 1 bit 2 bit 0 w reset00000000 = unimplemented or reserved figure 6-18. left justified, atd conversion result register x, high byte (atddrxh) 76543210 r (10-bit) r (8-bit) bit 1 u bit 0 u 0 0 0 0 0 0 0 0 0 0 0 0 w reset00000000 = unimplemented or reserved u = unaffected figure 6-19. left justified, atd conversion result register x, low byte (atddrxl) chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 231 6.3.2.16.2 right ju stified result data 6.4 functional description the atd10b16c is structured in an analog and a digital sub-block. 6.4.1 analog sub-block the analog sub-block contains all analog electronics required to perf orm a single conversion. separate power supplies v dda and v ssa allow to isolate noise of other mcu circuitry from the analog sub-block. 6.4.1.1 sample and hold machine the sample and hold (s/h) machine accepts analog signa ls from the external world and stores them as capacitor charge on a storage node. the sample process uses a two stage approach. during the first stage, the sample amplifier is used to quickly charge the storage node.the second stage c onnects the input directly to the storage node to complete the sample for high accuracy. when not sampling, the sample and hol d machine disables its own clocks. the analog electronics continue drawing their quiescent current. the power down (adpu) bit must be set to disable both the digital clocks and the analog power consumption. the input analog signals are unipolar and mu st fall within the potential range of v ssa to v dda . 76543210 r (10-bit) r (8-bit) 0 0 0 0 0 0 0 0 0 0 0 0 bit 9 msb 0 bit 8 0 w reset00000000 = unimplemented or reserved figure 6-20. right justified, atd conversion result register x, high byte (atddrxh) 76543210 r (10-bit) r (8-bit) bit 7 bit 7 msb bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 w reset00000000 = unimplemented or reserved figure 6-21. right justified, atd conversion result register x, low byte (atddrxl) chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 232 freescale semiconductor 6.4.1.2 analog input multiplexer the analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine. 6.4.1.3 sample buffer amplifier the sample amplifier is used to buffer the input an alog signal so that the storage node can be quickly charged to the sample potential. 6.4.1.4 analog-to-digital (a/d) machine the a/d machine perfor ms analog to digital conversi ons. the resolution is progra m selectable at either 8 or 10 bits. the a/d machine uses a successive approximation architectur e. it functions by comparing the stored analog sample potential with a series of digitally gene rated analog potentials. by following a binary search algorithm, the a/d machine locates the approxi mating potential that is nearest to the sampled potential. when not converting the a/d machine disables its ow n clocks. the analog electr onics continue drawing quiescent current. the power down (adpu) bit must be set to disable both the digi tal clocks and the analog power consumption. only analog input signals within the potential range of v rl to v rh (a/d reference poten tials) will result in a non-railed digital output codes. 6.4.2 digital sub-block this subsection explains some of the digital features in more detail. see register descriptions for all details. 6.4.2.1 external trigger input the external trigger featur e allows the user to synchronize atd c onversions to the external environment events rather than relying on software to signal the atd module when atd conversions are to take place. the external trigger signal (out of reset atd channel 15, configurable in atdctl1) is programmable to be edge or level sensitiv e with polarity control. table 6-27 gives a brief description of the different combinations of control bi ts and their effect on the external trigger function. during a conversion, if additional active edges ar e detected the overrun error flag etorf is set. table 6-27. external trigger control bits etrigle etrigp etrige scan description x x 0 0 ignores external trigger. performs one conversion sequence and stops. x x 0 1 ignores external trigger. performs continuous conversion sequences. 0 0 1 x falling edge triggered. performs one conversion sequence per trigger. 0 1 1 x rising edge triggered. performs one conversion sequence per trigger. 1 0 1 x trigger active low. performs continuous conversions while trigger is active. 1 1 1 x trigger active high. performs continuous conversions while trigger is active. chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 233 in either level or edge triggered modes, the first conversion begins wh en the trigger is received. in both cases, the maximum latency time is one bus clock cycle plus any skew or delay in troduced by the trigger circuitry. after etrige is enabled, conversions cannot be star ted by a write to atdctl5, but rather must be triggered externally. if the level mode is activ e and the external trigger both de-asserts and re-assert s itself during a conversion sequence, this does not constitute an overrun. therefore, the flag is not set. if th e trigger remains asserted in level mode while a sequence is completing, another sequence wi ll be triggered immediately. 6.4.2.2 general-purpose digital input port operation the input channel pins can be multiplexed between analog and digital data. as analog inputs, they are multiplexed and sampled to supply signals to the a/d converter. as digital input s, they supply external input data that can be accessed through the digita l port registers (portad0 & portad1) (input-only). the analog/digital multiplex operation is performed in the input pads. th e input pad is always connected to the analog inputs of the atd10b16c. the input pad si gnal is buffered to the dig ital port registers. this buffer can be turned on or off with the atddien0 & atddien1 register. this is important so that the buffer does not draw excess current when an alog potentials are presented at its input. 6.4.3 operation in low power modes the atd10b16c can be configured for lower mc u power consumption in three different ways: ? stop mode stop mode: this halts a/d conversion. exit from stop mode will resume a/d conversion, but due to the recovery time the result of this conversion should be ignored. entering stop mode causes all clocks to halt a nd thus the system is placed in a minimum power standby mode. this halts any conve rsion sequence in progress. du ring recovery from stop mode, there must be a minimum delay for the stop recovery time t sr before initiating a new atd conversion sequence. ? wait mode wait mode with awai = 1: this halts a/d c onversion. exit from wait mode will resume a/d conversion, but due to the recovery time the result of this conversion should be ignored. entering wait mode, the atd convers ion either continues or halt s for low power depending on the logical value of the await bit. ? freeze mode writing adpu = 0 (note that all atd registers remain accessible.): this aborts any a/d conversion in progress. in freeze mode, the atd10b16c will behave acco rding to the logical values of the frz1 and frz0 bits. this is useful for debugging and emulation. note the reset value for the adpu bit is ze ro. therefore, when this module is reset, it is reset into the power down state. chapter 6 analog-to-digital converter (atd10b16cv4) mc9s12e256 data sheet, rev. 1.08 234 freescale semiconductor 6.5 resets at reset the atd10b16c is in a power down state. the reset state of each indivi dual bit is listed within section 6.3, ?memory map and register definition , ? which details the regist ers and their bit fields. 6.6 interrupts the interrupt requested by th e atd10b16c is listed in table 6-28 . refer to mcu specification for related vector address and priority. see section 6.3.2, ?register descriptions , ? for further details. table 6-28. atd interrupt vectors interrupt source ccr mask local enable sequence complete interrupt i bit ascie in atdctl2 mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 235 chapter 7 digital-to-analog converter (dac8b1cv1) 7.1 introduction the dac8b1c is a 8-bit, 1-channel digital-to-analog converter module. 7.1.1 features the dac8b1c includes these features: ? 8-bit resolution. ? one output independent monotonic channel. 7.1.2 modes of operation the dac8b1c functions the same in normal, special, and emulation modes. it has two low-power modes, wait and stop modes. 7.1.2.1 run mode normal mode of operation. 7.1.2.2 wait mode entering wait mode, the dac conversion either c ontinues or aborts for low power, depending on the logical state of the dacwai bit. 7.1.2.3 stop mode the dac8b1c module is disabled in stop mode fo r reduced power consumption. the stop instruction does not affect dac register states. 7.1.3 block diagram figure 7-1 illustrates the functional bloc k diagram of the dac8b1c module. chapter 7 digital-to-analog converter (dac8b1cv1) mc9s12e256 data sheet, rev. 1.08 236 freescale semiconductor figure 7-1. dac8b1c functional block diagram 7.2 external signal description the dac8b1c module requires four extern al pins. these pins are listed in table 7-1 below. table 7-1. dac8b1c exte rnal pin descriptions name function dao dac channel output v dda dac power supply v ssa dac ground supply v ref reference voltage for dac conversion v rl reference ground voltage connected to v ssa outside the dac boundary v dda v ref v rl v ssa control circuit analog sub-block o/p voltage dao dac channel dacc dacd chapter 7 digital-to-analog converter (dac8b1cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 237 7.2.1 dao ? dac channel output this pin is used as the analog out put pin of the dac8b1c module. the value repres ents the analog voltage level between v ssa and v ref . 7.2.2 v dda ? dac power supply this pin serves as the power supply pin.l 7.2.3 v ssa ? dac ground supply this pin serves as an analog ground reference to the dac. 7.2.4 v ref ? dac reference supply this pin serves as the source for the high referen ce potential. separation from the power supply pins accommodates the filtering necessary to achieve the accuracy of which the system is capable. 7.2.5 v rl ? dac reference ground supply this pin serves as the ground for the low refe rence potential. this pin is connected to v ssa outside the dac module boundary to accommodate the filtering n ecessary to achieve the accuracy of which the system is capable. 7.3 memory map and registers this section provides a detailed description of al l memory and registers accessible to the end user. 7.3.1 module memory map figure 7-2 summarizes the dac8b1c memory map. the base address is defined at the chip level and the address offset is define d at the module level. addressname bit 765432 1bit 0 0x0000 dacc0 r dace dacte 0 0 djm dsgn dacwai dacoe w 0x0001 dacc1 r0 00000 0 0 w 0x0002 dacd (left justified) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0003 dacd (right justified) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w = unimplemented or reserved figure 7-2. dac8b1c register summary chapter 7 digital-to-analog converter (dac8b1cv1) mc9s12e256 data sheet, rev. 1.08 238 freescale semiconductor 7.3.2 register descriptions this section consists of register descriptions arranged in address order. each description includes a standard register diagram with an a ssociated figure number. de tails of register bit and field function follow the register diagrams, in descending bit order. 7.3.2.1 dac control register 0 (dacc0) read: anytime (reserved locations read zero) write: anytime except dacte is available only in special modes module base + 0x0000 76543210 r dace dacte 0 0 djm dsgn dacwai dacoe w reset00000000 = unimplemented or reserved figure 7-3. dac control register 0 (dacc0) table 7-2. dacc0 field descriptions field description 7 dace dac enable ? this bit enables digital-to-analog converter func tionality. when enabled, an analog voltage based on the digital value in the dac data register will be output. when disabled, dao pin is high-impedance. 0 dac is disabled and powered down 1 dac is enabled for conversion 6 dacte dac test enable ? this reserved bit is designed for factory test purposes only and is not intended for general user access. writing to this bit when in s pecial test modes can alter dac functionality. 3 djm data register data justification ? this bit controls the justification of the data in the dac data register (dacd). if djm is clear (left-justified) , the data to be converted must be writ ten to left justified dacd and the right justified dacd register will read zeroes. if djm is set (right-j ustified), the data to be converted is written to right justified dacd register and left just ified dacd register reads zeroes. data is preserved if djm bit is changed after data is written. 0 left justified data in dac data register 1 right justified data in dac data register 2 dsgn data register signed ? this bit selects between signed and unsigned conversion data representation in the dac data register. signed data is represented as 2?s complement. 0 unsigned data representation in dac data register 1 signed data representation in dac data register 1 dacwai dac stop in wait mode ? dacwai disables the dac8b1c module (no new conversion is done) during wait mode. 0 dac is enabled during wait mode 1 dac is disabled and powered down during wait mode 0 dacoe dac output enable ? this bit enables the output on the dao pin. to output the dac voltage, the dacoe bit and the dace bit must be set. when disabled, dao pin is high-impedance. 0 output is not available for external use 1 output on dao pin enabled. chapter 7 digital-to-analog converter (dac8b1cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 239 7.3.2.2 reserved register (dacc1) this register is reserved. read: always read $00 write: unimplemented 7.3.2.3 dac data register ? left justified (dacd) read: read zeroes when djm is set write: unimplemented when djm is set the dac data register is an 8-bit re adable/writable register that stores the data to be converted when djm bit is clear. when the dace bit is set, the value in th is register is converted in to an analog voltage such that values from $00 to $ff result in equal voltage increments from v ssa to v ref . when djm bit is set, this register reads zero es and cannot be written. module base + 0x0000 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 7-4. reserved register (dacc1) module base + 0x0002 76543210 r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000 figure 7-5. dac data register ? left justified (dacd) chapter 7 digital-to-analog converter (dac8b1cv1) mc9s12e256 data sheet, rev. 1.08 240 freescale semiconductor 7.3.2.4 dac data register ? right justified (dacd) read: read zeroes when djm is clear write: unimplemented when djm is clear the dac data register is an 8-bit re adable/writable register that stores the data to be converted when djm bit is set. when the dace bit is set, the value in this register is convert ed into an analog voltage such that values from $00 to $f f result in equal voltage increments from v ssa to v ref . when djm bit is clear, this register reads zeroes and cannot be written. module base + 0x0003 76543210 r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000 figure 7-6. dac data register ? right justified (dacd) chapter 7 digital-to-analog converter (dac8b1cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 241 7.4 functional description the dac8b1c module consists of analog and digital sub-blocks. 7.4.1 functional description data to be converted is written to dacd register. the data can be mapped either to left end or right end of dacd register by cleari ng or setting djm bit of dac c0 register. also, the data written to dacd can be a signed or unsigned data dependi ng on dsgn bit of dacc0 register. see table 7-3 below for data formats. the maximum unsigned data that can be wr itten to dacd register is $ff while the minimum value is $00. if the data is signed, the maximum valu e that can be written to dacd is $7f while the minimum value is $80, where $7f (s igned) corresponds to $ff (unsi gned) and $80 (signed) corresponds to $00 (unsigned). table 7-4 shows this characteristic between si gned, unsigned data values and their corresponding voltage output. see table 7-4 for dac signed and un-signe d data and dac output codes. table 7-3. data formats djm dsgn description and bus bit mapping 0 0 8 bit/left justified/unsigned ? bits 15?8 0 1 8 bit/left justified/signed ? bits 15?8 1 0 8 bit/right justified/unsigned ? bits 7?0 1 1 8 bit/right justified/signed bits ? 7?0 table 7-4. signed and unsigned data and dac output codes input signal v rl = 0 v ref /v rh = 5.12volts signed 8-bit codes unsigned 8-bit codes 5.12 7f ff 5.08 7e fe 5.07 7d fd 2.580 01 81 2.56 00 80 2.54 ff 7f 2.52 fe 7e 0.020 81 01 0.000 80 00 chapter 7 digital-to-analog converter (dac8b1cv1) mc9s12e256 data sheet, rev. 1.08 242 freescale semiconductor conversion of the data in dacd regi ster takes place as soon as dace bi t of dacc0 is se t. the transfer characteristic of the day module is shown in figure 7-7 . figure 7-7. dac8b1c transfer function 7.5 resets 7.5.1 general the dac8b1c module is reset on a system reset. if the system reset signal is act ivated, the dac registers are initialized to their reset state and the dac8b1 c module is powered down. this occurs as a function of the register file in itialization. if the module is performing a conversion, the current conversion is terminated. analog output voltage digital input 1 lsb = 21.5 mv when v dda = 5.5 v 1 lsb = 11.5 mv when v dda = 3.0 v $00 $01 $02 $fe $ff 1 lsb 2 lsb 3 lsb 255 lsb 256 lsb mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 243 chapter 8 serial communication interface (sciv4) 8.1 introduction this block description chapter provides an overvie w of serial communication interface (sci) module. the sci allows full duplex, async hronous, serial communication betwee n the cpu and remote devices, including other cpus. the sci transm itter and receiver operate independe ntly, although they use the same baud rate generator. the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. 8.1.1 glossary ir: infrared irda: infrared design association irq: interrupt request lsb: least significant bit msb: most significant bit nrz: non-return-to-zero rzi: return-to-zero-inverted rxd: receive pin sci: serial communication interface txd: transmit pin 8.1.2 features the sci includes these distinctive features: ? full-duplex or single-wire operation ? standard mark/space non-return-to-zero (nrz) format ? selectable irda 1.4 retu rn-to-zero-inverted (rzi) format with programmable pulse widths ? 13-bit baud rate selection ? programmable 8-bit or 9-bit data format ? separately enabled tr ansmitter and receiver ? programmable polarity for transmitter and receiver chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 244 freescale semiconductor ? programmable transmitter output parity ? two receiver wakeup methods: ? idle line wakeup ? address mark wakeup ? interrupt-driven operation with eight flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection 8.1.3 modes of operation the sci functions the same in normal, special, and em ulation modes. it has two low-power modes, wait and stop modes. 8.1.3.1 run mode normal mode of operation. 8.1.3.2 wait mode sci operation in wait mode depends on the state of the sciswai bit in the sci control register 1 (scicr1). ? if sciswai is clear, the sci operates nor mally when the cpu is in wait mode. ? if sciswai is set, sci clock generation ceases and the sci module enters a power-conservation state when the cpu is in wait mode. setting sciswai does not af fect the state of the receiver enable bit, re, or the transmitter enable bit, te. if sciswai is set, any transm ission or reception in progress stops at wait mode entry. the transmission or rece ption resumes when either an internal or external interrupt brings the cpu out of wait mode. exiting wa it mode by reset aborts any transmission or rece ption in progress and resets the sci. chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 245 8.1.3.3 stop mode the sci is inactive during stop mode for reduced power consumption. the st op instruction does not affect the sci register st ates, but the sci bus clock will be disa bled. the sci operation resumes after an external interrupt brings the cpu out of stop mode. exiting stop mode by reset aborts any transmission or reception in progress and resets the sci. 8.1.4 block diagram figure 8-1 is a high level block diagram of the sci modu le, showing the interaction of various function blocks. figure 8-1. sci block diagram sci data register receive shift register receive & wakeup control data format control transmit control transmit shift register sci data register baud generator irq generation irq generation rxd data in 16 bus clk encoder infrared data out txd decoder infrared tc interrupt request idle interrupt request sci interrupt request rdrf/or interrupt request tdre interrupt request chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 246 freescale semiconductor 8.2 external signal description the sci module has a total of two external pins. 8.2.1 txd ? sci transmit pin the txd pin transmits sci (standard or infrared) data . it will idle high in either mode and is high impedance anytime the tr ansmitter is disabled. 8.2.2 rxd ? sci receive pin the rxd pin receives sci (standard or in frared) data. an idle li ne is detected as a li ne high. this input is ignored when the receiver is disabled and should be terminated to a known voltage. 8.3 memory map and register definition this subsection provides a detailed de scription of all the sci registers. 8.3.1 module memory map the memory map for the sci module is given in figure 8-2 . the address listed for each register is the address offset. the total a ddress for each register is the sum of the base address for the sci module and the address offset for each register. 8.3.2 register descriptions this subsection consists of register descriptions in address order. each desc ription includes a standard register diagram with an associated figure number. writes to reserved register locations do not have any effect and reads of these locations return a 0. details of register bit and field f unction follow the register diagrams, in bit order. chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 247 register name bit 7654321bit 0 scibdh r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w scibdl r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w scicr1 r loops sciswai rsrc m wake ilt pe pt w scicr2 r tie tcie rie ilie te re rwu sbk w scisr1 r tdre tc rdrf idle or nf fe pf w scisr2 r 0 0 0 txpol rxpol brk13 txdir raf w scidrh r r8 t8 000000 w scidrlrr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 = unimplemented or reserved figure 8-2. sci registers summary chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 248 freescale semiconductor 8.3.2.1 sci baud rate regi sters (scibdh and scibdl) 76543210 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset00000000 figure 8-3. sci baud rate register high (scibdh) table 8-1. scibdh field descriptions field description 7 iren infrared enable bit ? this bit enables/disables the infr ared modulation/demo dulation submodule. 0ir disabled 1 ir enabled 6:5 tnp[1:0] transmitter narrow pulse bits ? these bits determine if the sci will transmit a 1/16, 3/16, 1/32, or 1/4 narrow pulse. refer to ta b l e 8 - 3 . 4:0 sbr[11:8] sci baud rate bits ? the baud rate for the sci is determined by the bits in this register. the baud rate is calculated two different ways depending on the state of the iren bit. the formulas for calculating the baud rate are: when iren = 0 then, sci baud rate = sci module clock / (16 x sbr[12:0]) when iren = 1 then, sci baud rate = sci module clock / (32 x sbr[12:1]) 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset00000100 figure 8-4. sci baud rate register low (scibdl) table 8-2. scibdl field descriptions field description 7:0 sbr[7:0] sci baud rate bits ? the baud rate for the sci is determined by the bits in this register. the baud rate is calculated two different ways depending on the state of the iren bit. the formulas for calculating the baud rate are: when iren = 0 then, sci baud rate = sci module clock / (16 x sbr[12:0]) when iren = 1 then, sci baud rate = sci module clock / (32 x sbr[12:1]) chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 249 read: anytime note if only scibdh is written to, a read w ill not return the correct data until scibdl is written to as well , following a write to scibdh. write: anytime the sci baud rate register is used to determine th e baud rate of the sci and to control the infrared modulation/demodul ation submodule. note the baud rate generator is disabled af ter reset and not started until the te bit or the re bit is set for the first ti me. the baud rate generator is disabled when (sbr[12:0] = 0 and iren = 0) or (sbr[12:1] = 0 and iren = 1). writing to scibdh has no effect wi thout writing to scibdl, because writing to scibdh puts the data in a temporary location until scibdl is written to. 8.3.2.2 sci control register 1 (scicr1) read: anytime write: anytime table 8-3. irsci transmit pulse width tnp[1:0] narrow pulse width 11 1/4 10 1/32 01 1/16 00 3/16 76543210 r loops sciswai rsrc m wake ilt pe pt w reset00000000 figure 8-5. sci control register 1 (scicr1) chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 250 freescale semiconductor table 8-4. scicr1 field descriptions field description 7 loops loop select bit ? loops enables loop operation. in loop opera tion, the rxd pin is disconnected from the sci and the transmitter output is internally connected to the re ceiver input. both the transmitter and the receiver must be enabled to use the loop function. 0 normal operation enabled 1 loop operation enabled the receiver input is determined by the rsrc bit. 6 sciswai sci stop in wait mode bit ? sciswai disables the sci in wait mode. 0 sci enabled in wait mode 1 sci disabled in wait mode 5 rsrc receiver source bit ? when loops = 1, the rsrc bit determines the source for the receiver shift register input. 0 receiver input internally connected to transmitter output 1 receiver input connected externally to transmitter refer to ta b l e 8 - 5 . 4 m data format mode bit ? mode determines whether data charac ters are eight or nine bits long. 0 one start bit, eight data bits, one stop bit 1 one start bit, nine data bits, one stop bit 3 wake wakeup condition bit ? wake determines whic h condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received data c haracter or an idle condition on the rxd pin. 0 idle line wakeup 1 address mark wakeup 2 ilt idle line type bit ? ilt determines when the receiver starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after th e start bit, then a string of logic 1s preceding the stop bit may cause false recognit ion of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 idle character bit count begins after start bit 1 idle character bit count begins after stop bit 1 pe parity enable bit ? pe enables the parity function. when enabled, the parity function inserts a parity bit in the most significant bit position. 0 parity function disabled 1 parity function enabled 0 pt parity type bit ? pt determines whether the sci generates and ch ecks for even parity or odd parity. with even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. with odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 0 even parity 1 odd parity table 8-5. loop functions loops rsrc function 0 x normal operation 1 0 loop mode with transmitter output internally connected to receiver input 1 1 single-wire mode with txd pin connected to receiver input chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 251 8.3.2.3 sci control register 2 (scicr2) read: anytime write: anytime 76543210 r tie tcie rie ilie te re rwu sbk w reset00000000 figure 8-6. sci control register 2 (scicr2) table 8-6. scicr2 field descriptions field description 7 tie transmitter interrupt enable bit ?tie enables the transmit data register empty flag, tdre, to generate interrupt requests. 0 tdre interrupt requests disabled 1 tdre interrupt requests enabled 6 tcie transmission complete interrupt enable bit ? tcie enables the transmission complete flag, tc, to generate interrupt requests. 0 tc interrupt requests disabled 1 tc interrupt requests enabled 5 rie receiver full interrupt enable bit ? rie enables the receive data register full flag, rdrf, or the overrun flag, or, to generate interrupt requests. 0 rdrf and or interrupt requests disabled 1 rdrf and or interrupt requests enabled 4 ilie idle line interrupt enable bit ? ilie enables the idle line flag, idle, to generate interrupt requests. 0 idle interrupt requests disabled 1 idle interrupt requests enabled 3 te transmitter enable bit ? te enables the sci transmitter and configures the txd pin as being controlled by the sci. the te bit can be used to queue an idle preamble. 0 transmitter disabled 1 transmitter enabled 2 re receiver enable bit ? re enables the sci receiver. 0 receiver disabled 1 receiver enabled 1 rwu receiver wakeup bit ? standby state 0 normal operation. 1 rwu enables the wakeup function and inhibits further receiver interrupt requests. normally, hardware wakes the receiver by automatically clearing rwu. 0 sbk send break bit ? toggling sbk sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if brk13 is set). togg ling implies clearing the sbk bit before the br eak character has fini shed transmitting. as long as sbk is set, the transmitter cont inues to send complete br eak characters (10 or 11 bits, respectively 13 or 14 bits). 0 no break characters 1 transmit break characters chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 252 freescale semiconductor 8.3.2.4 sci status register 1 (scisr1) the scisr1 and scisr2 registers provide inputs to th e mcu for generation of sci interrupts. also, these registers can be polled by the mcu to check the status of these bits. the flag-cle aring procedures require that the status register be read followed by a read or write to the sci data regi ster. it is permissible to execute other instructions between the two steps as long as it does not compromise the handling of i/o. note that the order of operations is important for flag clearing. read: anytime write: has no meaning or effect 76543210 r tdre tc rdrf idle or nf fe pf w reset11000000 = unimplemented or reserved figure 8-7. sci status register 1 (scisr1) table 8-7. scisr1 field descriptions field description 7 tdre transmit data register empty flag ? tdre is set when the transmit shif t register receives a byte from the sci data register. when tdre is 1, the transmit data re gister (scidrh/l) is empty and can receive a new value to transmit.clear tdre by reading sc i status register 1 (sci sr1), with tdre set and then writing to sci data register low (scidrl). 0 no byte transferred to transmit shift register 1 byte transferred to transmit shift regi ster; transmit data register empty 6 tc transmit complete flag ? tc is set low when there is a transmission in progress or when a preamble or break character is loaded. tc is set high when the tdre flag is set and no data, preamble, or break character is being transmitted.when tc is set, the txd pin becomes idle (l ogic 1). clear tc by reading sci status register 1 (scisr1) with tc set and then writing to sci data regist er low (scidrl). tc is clear ed automatically when data, preamble, or break is queued and ready to be sent. tc is cleared in the event of a simultaneous set and clear of the tc flag (transmission not complete). 0 transmission in progress 1 no transmission in progress 5 rdrf receive data register full flag ? rdrf is set when the data in the rece ive shift register transfers to the sci data register. clear rdrf by reading sc i status register 1 (scisr1) with rdrf set and then reading sci data register low (scidrl). 0 data not available in sci data register 1 received data available in sci data register 4 idle idle line flag 1 ? idle is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m = 1) appear on the receiver input. after the idle flag is cleared, a valid frame must again set the rdrf flag before an idle condition can set the idle flag.clear idle by reading sci status register 1 (scisr1) with idle set and then reading sci data register low (scidrl). 0 receiver input is either active now or has never become active since the idle flag was last cleared 1 receiver input has become idle chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 253 3 or overrun flag 2 ? or is set when software fails to read the sc i data register before the receive shift register receives the next frame. the or bit is set immediatel y after the stop bit has been completely received for the second frame. the data in the shift regi ster is lost, but the data already in the sci data register s is not affected. clear or by reading sci status regi ster 1 (scisr1) with or set and t hen reading sci data register low (scidrl). 0 no overrun 1overrun 2 nf noise flag ? nf is set when the sci detects noise on the rece iver input. nf bit is set during the same cycle as the rdrf flag but does not get set in the case of an over run. clear nf by reading sci status register 1(scisr1), and then reading sci data register low (scidrl). 0 no noise 1noise 1 fe framing error flag ? fe is set when a logic 0 is accepted as t he stop bit. fe bit is set during the same cycle as the rdrf flag but does not get set in the case of an overrun. fe inhibits further data reception until it is cleared. clear fe by reading sci stat us register 1 (scisr1) with fe set and then reading the sci data register low (scidrl). 0 no framing error 1 framing error 0 pf parity error flag ? pf is set when the parity enable bit (pe) is set and the parity of the received data does not match the parity type bit (pt). pf bit is set during the same cycle as the rdrf flag but does not get set in the case of an overrun. clear pf by reading sci status regi ster 1 (scisr1), and then readi ng sci data register low (scidrl). 0 no parity error 1 parity error 1 when the receiver wakeup bit (rwu) is set, an idle line condition does not set the idle flag. 2 the or flag may read back as set when rdrf flag is clear. this may happen if the following sequence of events occurs: 1. after the first frame is received, read status re gister scisr1 (returns rdrf set and or flag clear); 2. receive second frame without reading the first frame in t he data register (the second frame is not received and or flag is set); 3. read data register scidrl (returns first fram e and clears rdrf flag in the status register); 4. read status register scisr1 (returns rdrf clear and or set). event 3 may be at exactly the same time as event 2 or any time after. when this happens, a dummy scidrl read following event 4 will be required to clear the or flag if further frames are to be received. table 8-7. scisr1 field d escriptions (continued) field description chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 254 freescale semiconductor 8.3.2.5 sci status register 2 (scisr2) read: anytime write: anytime 76543210 r0 0 0 txpol rxpol brk13 txdir raf w reset00000000 = unimplemented or reserved figure 8-8. sci status register 2 (scisr2) table 8-8. scisr2 field descriptions field description 4 txpol transmit polarity ? this bit control the polarity of the transmit ted data. in nrz format, a 1 is represented by a mark and a 0 is represented by a space for normal polarity, and the opposite for inverted polarity. in irda format, a 0 is represented by short high pulse in the middle of a bit time remaining idle low for a 1 for normal polarity, and a 0 is represented by short low pulse in the middle of a bit time remaining idle high for a 1 for inverted polarity. 0 normal polarity 1 inverted polarity 3 rxpol receive polarity ? this bit control the polarity of the received da ta. in nrz format, a 1 is represented by a mark and a 0 is represented by a space for normal polarity, and the opposite for inverted polarity. in irda format, a 0 is represented by short high pulse in the middle of a bit time remaining idle low for a 1 for normal polarity, and a 0 is represented by short low pulse in the middle of a bi t time remaining idle high for a 1 for inverted polarity. 0 normal polarity 1 inverted polarity 2 brk13 break transmit character length ? this bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. the detection of a framing error is not affected by this bit. 0 break character is 10 or 11 bit long 1 break character is 13 or 14 bit long 1 txdir transmitter pin data direction in single-wire mode ? this bit determines whether the txd pin is going to be used as an input or output, in the single-wire mode of ope ration. this bit is only relevant in the single-wire mode of operation. 0 txd pin to be used as an input in single-wire mode 1 txd pin to be used as an output in single-wire mode 0 raf receiver active flag ? raf is set when the receiver detects a logi c 0 during the rt1 time period of the start bit search. raf is cleared when the receiver detects an idle character. 0 no reception in progress 1 reception in progress chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 255 8.3.2.6 sci data regist ers (scidrh and scidrl) read: anytime; reading accesse s sci receive data register write: anytime; writing accesses sci transmit data register; writing to r8 has no effect note if the value of t8 is the same as in the previous transmission, t8 does not have to be rewritten.the same value is transmitted until t8 is rewritten in 8-bit data format, only sci data register low (scidrl) needs to be accessed. when transmitting in 9-bit data format and using 8-bit write instructions, write first to sci data register high (scidrh) then to scidrl. 76543210 rr8 t8 000000 w reset00000000 = unimplemented or reserved figure 8-9. sci data register high (scidrh) table 8-9. scidrh field descriptions field description 7 r8 received bit 8 ? r8 is the ninth data bit received when the sci is configured for 9-bit data format (m = 1). 6 t8 transmit bit 8 ? t8 is the ninth data bit transmitted when the sci is configured for 9-bit data format (m = 1). 76543210 rr7r6r5r4r3r2r1r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset00000000 figure 8-10. sci data register low (scidrl) table 8-10. scidrl field descriptions field description 7:0 r[7:0] t[7:0} received bits 7 through 0 ? for 9-bit or 8-bit data formats transmit bits 7 through 0 ? for 9-bit or 8-bit formats chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 256 freescale semiconductor 8.4 functional description this subsection provides a complete functional description of the sci bl ock, detailing the operation of the design from the end user ?s perspective in a num ber of descriptions. figure 8-11 shows the structure of the sci module. th e sci allows full dupl ex, asynchronous, serial communication between the cpu and remote devices, including other cpus. the sci transmitter and receiver operate independently, alt hough they use the same baud rate ge nerator. the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. figure 8-11. detailed sci block diagram sci data receive shift register sci data register transmit shift register register baud rate generator sbr12?sbr0 bus transmit control 16 receive and wakeup data format control control t8 pf fe nf rdrf idle tie or tcie tdre tc r8 raf loops rwu re pe ilt pt wake m clock ilie rie rxd rsrc sbk loops te rsrc iren r16xclk ir_rxd txd ir_txd r16xclk r32xclk tnp[1:0] iren transmit encoder receive decoder scrxd sctxd infrared infrared tc tdre rdrf/or idle sci interrupt request chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 257 8.4.1 infrared interface submodule this module provides the capability of transmitting narrow pulses to an ir led and receiving narrow pulses and transforming them to serial bits, whic h are sent to the sci. the irda physical layer specification defines a half-duplex infrared communication link for exch ange data. the full standard includes data rates up to 16 mbits/s. this design covers only data rates between 2.4 kbits/s and 115.2 kbits/s. the infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. the sci transmits serial bits of data which are encoded by the infrared submodule to transm it a narrow pulse for every 0 bit. no pulse is transmitted for every 1 bit. when receiving data, the ir pulses should be detected using an ir photo diode and transformed to cmos levels by the ir receive decoder (external from the mcu). the narrow pulses are then stretched by the infrared subm odule to get back to a serial bit stream to be received by the sci. the polarity of transmitted pulses a nd expected receive pulses can be inverted so that a direct connection can be made to external irda transceiver modules that uses active low pulses. the infrared submodule receiv es its clock sources from the sci. one of these two clocks are selected in the infrared submodule in order to generate ei ther 3/16, 1/16, 1/32, or 1/4 narrow pulses during transmission. the infrared block receives two cloc k sources from the sci, r16xclk, and r32xclk, which are configured to generate the narrow pulse width during transmission. the r16xclk and r32xclk are internal clocks with frequencies 16 and 32 times the baud rate respectively. both r16xclk and r32xclk clocks are used for transm itting data. the receive decoder uses only the r16xclk clock. 8.4.1.1 infrared transmit encoder the infrared transmit encoder converts serial bits of data from transmit shift register to the txd pin. a narrow pulse is transmitted for a 0 bit and no pulse for a 1 bit. the narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/ 16, or 1/4 of a bit time. a narrow high pulse is transmitted for a 0 bit when txpol is cleared, while a narrow low pulse is transmitted for a 0 bit when txpol is set. 8.4.1.2 infrared receive decoder the infrared receive block converts da ta from the rxd pin to the receive shift register. a narrow pulse is expected for each 0 received and no pulse is expected for each 1 received. a narrow high pulse is expected for a 0 bit when rxpol is cleared, while a narrow low pulse is expected for a 0 bit when rxpol is set. this receive decoder meets the edge jitter requirement as defined by the irda serial infrar ed physical layer specification. 8.4.2 data format the sci uses the standard nrz mark/s pace data format. when infrared is enabled, the sci uses rzi data format where 0s are represented by light pulses and 1s remain low. see figure 8-12 . chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 258 freescale semiconductor figure 8-12. sci data formats each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. clearing the m bit in sci control regi ster 1 configures the sc i for 8-bit data characte rs. a frame with eight data bits has a total of 10 bits. se tting the m bit configures the sci fo r nine-bit data characters. a frame with nine data bits has a total of 11 bits when the sci is configured for 9-bit data characters, th e ninth data bit is the t8 bit in sci data register high (scidrh). it remains unchanged af ter transmission and can be used repeatedly without rewriting it. a frame with nine data bi ts has a total of 11 bits. table 8-12. example of 9-bit data formats table 8-11. example of 8-bit data formats start bit data bits address bits parity bits stop bit 18001 17011 17 1 1 1 the address bit identifies the frame as an address character. see section 8.4.5.6, ?receiver wakeup? . 01 start bit data bits address bits parity bits stop bit 19001 18011 18 1 1 1 the address bit identifies the frame as an address character. see section 8.4.5.6, ?receiver wakeup? . 01 bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scicr1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scicr1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit standard sci data infrared sci data standard sci data infrared sci data chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 259 8.4.3 baud rate generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. the value from 0 to 8191 written to the sbr[12:0] bits determines the module clock divisor. the sbr bits are in the sci baud rate registers (scibdh and scibdl). the baud rate clock is synchronized with the bus clock and drives the receiver. the baud rate clock divided by 16 drives the transmitter. the receiver has an acquisi tion rate of 16 samples per bit time. baud rate generation is subject to one source of error: ? integer division of the module clock ma y not give the exact target frequency. table 8-13 lists some examples of achie ving target baud rates with a mo dule clock frequency of 10.2 mhz. when iren = 0 then, sci baud rate = sci module clock / (16 * scibr[12:0]) table 8-13. baud rates (example: module clock = 10.2 mhz) bits sbr[12?0] receiver clock (hz) transmitter clock (hz) target baud rate error (%) 17 600,000.0 37,500.0 38,400 2.3 33 309,090.9 19,318.2 19,200 .62 66 154,545.5 9659.1 9600 .62 133 76,691.7 4793.2 4800 .14 266 38,345.9 2396.6 2400 .14 531 19,209.0 1200.6 1200 .11 1062 9604.5 600.3 600 .05 2125 4800.0 300.0 300 .00 4250 2400.0 150.0 150 .00 5795 1760.1 110.0 110 .00 chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 260 freescale semiconductor 8.4.4 transmitter figure 8-13. transmitter block diagram 8.4.4.1 transmitter character length the sci transmitter can accommodate ei ther 8-bit or 9-bit data character s. the state of the m bit in sci control register 1 (scicr1) determin es the length of data characters. wh en transmitting 9-bit data, bit t8 in sci data register high (sci drh) is the ninth bit (bit 8). 8.4.4.2 character transmission to transmit data, the mcu writes th e data bits to the sci data regist ers (scidrh/scidrl), which in turn are transferred to the transmitter sh ift register. the transmit shift regi ster then shifts a frame out through the txd pin, after it has prefaced them with a start bit and appended them with a stop bit. the sci data registers (scidrh and scidrl) are th e write-only buffers betw een the internal data bus and the transmit shift register. the sci also sets a flag, the transm it data register empty flag (tdre) , every time it tran sfers data from the buffer (scidrh/l) to the transm itter shift register. the transmit driver routine may respond to this pe pt h876543210l 11-bit transmit shift register stop start t8 tdre tie tcie sbk tc parity generation msb sci data registers load from scidr shift enable preamble (all ones) break (all 0s) transmitter control m internal bus sbr12?sbr0 baud divider 16 tdre interrupt request tc interrupt request bus clock te sctxd txpol loops loop rsrc control to receiver chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 261 flag by writing another byte to the transmitter buffe r (scidrh/scidrl), while the shift register is shifting out the first byte. to initiate an sci transmission: 1. configure the sci: a) select a baud rate. write this value to the sci baud registers (scib dh/l) to begin the baud rate generator. remember that the baud rate ge nerator is disabled when the baud rate is 0. writing to the scibdh has no effect without also writing to scibdl. b) write to scicr1 to configure word length, parity, and other configuration bits (loops, rsrc, m, wake, ilt, pe, and pt). c) enable the transmitter, interrupts, receive, a nd wake up as required, by writing to the scicr2 register bits (tie, tcie, rie, ilie, te, re, rwu, and sbk). a preamble or idle character will now be shifted out of th e transmitter shift register. 2. transmit procedure for each byte: a) poll the tdre flag by reading the scisr1 or responding to th e tdre interrupt. keep in mind that the tdre bit resets to 1. b) if the tdre flag is set, write the data to be transmitted to scidrh/l, where the ninth bit is written to the t8 bit in scidrh if the sci is in 9-bit data format. a new transmission will not result until the tdre flag has been cleared. 3. repeat step 2 for each subsequent transmission. note the tdre flag is set when the shift register is loaded with the next data to be transmitted from scidrh/l, which happens, generally speaking, a little over half-way through the stop bit of th e previous frame. specifically, this transfer occurs 9/16ths of a bit time after the start of the stop bit of the previous frame. writing the te bit from 0 to a 1 automatically load s the transmit shift register with a preamble of 10 logic 1s (if m = 0) or 11 logic 1s (if m = 1). after th e preamble shifts out, contro l logic transfers the data from the sci data register into the transmit shift re gister. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift regi ster. a logic 1 stop bit goes into the most significant bit position. hardware supports odd or even parity. when parity is enabled, the most significant bit (msb) of the data character is the parity bit. the transmit data register empty flag, tdre, in sci st atus register 1 (scisr1) becomes set when the sci data register transfers a byte to the transmit shift register. the tdre flag i ndicates that the sci data register can accept new data from the internal data bus . if the transmit interrupt enable bit, tie, in sci control register 2 (scicr2) is also set, the td re flag generates a transmitter interrupt request. when the transmit shift register is not transmitting a frame, the txd pin goes to th e idle condition, logic 1. if at any time software clears the te bit in sci control register 2 (sci cr2), the transmitter enable signal goes low and the transmit signal goes idle. chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 262 freescale semiconductor if software clears te while a transm ission is in progress (tc = 0), the frame in the tr ansmit shift register continues to shift out. to a void accidentally cut ting off the last frame in a me ssage, always wait for tdre to go high after the last frame before clearing te. to separate messages with preambles with minimum id le line time, use this sequence between messages: 1. write the last byte of the first message to scidrh/l. 2. wait for the tdre flag to go high, indicating the tr ansfer of the last frame to the transmit shift register. 3. queue a preamble by clearing and then setting the te bit. 4. write the first byte of the second message to scidrh/l. 8.4.4.3 break characters writing a logic 1 to the send break bit, sbk, in sci control register 2 (scicr2) loads the transmit shift register with a break character. a brea k character contains all logic 0s a nd has no start, stop, or parity bit. break character length depends on the m bit in sci c ontrol register 1 (scicr1). as long as sbk is at logic 1, transmitter logic c ontinuously loads break characters into th e transmit shift regist er. after software clears the sbk bit, the shift register finishes transmitting the last break ch aracter and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarant ees the recognition of the start bit of the next frame. the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a br eak character has these effects on sci registers: ? sets the framing error flag, fe ? sets the receive data register full flag, rdrf ? clears the sci data registers (scidrh/l) ? may set the overrun flag, or, noise flag, nf, parity error flag, pe, or the receiver active flag, raf (see section 8.3.2.4, ?sci status register 1 (scisr1)? and section 8.3.2.5, ?sci status register 2 (scisr2)? ). 8.4.4.4 idle characters an idle character (or preamble) cont ains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit in sci control register 1 (scicr1). the preamble is a synchronizing idle character that begins the first transmission in itiated after writing the te bit from 0 to 1. if the te bit is cleared during a transmission, th e txd pin becomes idle after completion of the transmission in progress. cleari ng and then setting the te bit during a transmission queues an idle character to be sent after the frame currently being transmitted. note when queueing an idle character, return the te bit to logic 1 before the stop bit of the current frame shifts out through the txd pin. se tting te after the stop bit appears on txd causes data previously written to the sci data register to be lost. toggle the te bit for a queued idle character while the chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 263 tdre flag is set and immediately be fore writing the next byte to the sci data register. if the te bit is clear and the transmis sion is complete, the sci is not the master of the txd pin 8.4.5 receiver figure 8-14. sci receiver block diagram 8.4.5.1 receiver character length the sci receiver can accommodate ei ther 8-bit or 9-bit data characte rs. the state of the m bit in sci control register 1 (scicr1) determines the length of data characters. when recei ving 9-bit data, bit r8 in sci data register high (scidrh) is the ninth bit (bit 8). 8.4.5.2 character reception during an sci reception, the receive shift register sh ifts a frame in from the rxd pin. the sci data register is the read-only buffer between the inte rnal data bus and the receive shift register. after a complete frame shifts into the receive shift re gister, the data portion of the frame transfers to the sci data register. the receive data register full fl ag, rdrf, in sci stat us register 1 (scisr1) becomes set, all ones m wake ilt pe pt re h876543210l 11-bit receive shift register stop start data wakeup parity checking msb sci data register r8 rie ilie rwu rdrf or nf fe pe internal bus bus idle interrupt request rdrf/or interrupt request sbr12?sbr0 baud clock idle raf recovery logic rxpol loops loop rsrc control scrxd from txd pin or transmitter divider chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 264 freescale semiconductor indicating that the received byt e can be read. if the receive interrupt en able bit, rie, in sci control register 2 (scicr2) is also set, the rdrf flag generates an rdrf interrupt request. 8.4.5.3 data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for ba ud rate mismatch, the rt clock (see figure 8-15 ) is re-synchronized: ? after every start bit ? after the receiver detects a data bit change from lo gic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data rec overy logic does an asynchronous sear ch for a logic 0 preceded by three logic 1s. when the falling edge of a possible star t bit occurs, the rt clock begins to count to 16. figure 8-15. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 8-14 summarizes the results of th e start bit verification samples. if start bit verification is not succe ssful, the rt clock is reset and a new search for a start bit begins. table 8-14. start bit verification rt3, rt5, and rt7 samples sta rt bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 samples rt clock rt clock count start bit rxd start bit qualification start bit data sampling 11 1 1 1 1 110000 0 00 lsb verification chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 265 to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 8-15 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not af fect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit (logic 0). to verify a stop bit and to de tect noise, recovery logic take s samples at rt8, rt9, and rt10. table 8-16 summarizes the results of the stop bit samples. table 8-15. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 8-16. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 266 freescale semiconductor in figure 8-16 the verification samples rt3 and rt5 determine that the first low detected was noise and not the beginning of a start bit. the rt clock is reset and the start bit search begins again. the noise flag is not set because the noise occurred before the start bit was found. figure 8-16. start bit search example 1 in figure 8-17 , verification sample at rt3 is high. the rt 3 sample sets the noise flag. although the perceived bit time is misaligned, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 8-17. start bit search example 2 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 0 1 111000 00 lsb 0 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt11 rt10 rt9 rt14 rt13 rt12 rt2 rt1 rt16 rt15 rt3 rt4 rt5 rt6 rt7 samples rt clock rt clock count actual start bit rxd 11 1 1 11000 0 lsb 0 0 perceived start bit chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 267 in figure 8-18 , a large burst of noise is perceived as the be ginning of a start bit, although the test sample at rt5 is high. the rt5 sample sets the noise fl ag. although this is a wo rst-case misalignment of perceived bit time, the data samples rt8, rt9, and rt 10 are within the bit time and data recovery is successful. figure 8-18. start bit search example 3 figure 8-19 shows the effect of noise earl y in the start bit time. although th is noise does not affect proper synchronization with the start bit time, it does set the noise flag. figure 8-19. start bit search example 4 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt13 rt12 rt11 rt16 rt15 rt14 rt4 rt3 rt2 rt1 rt5 rt6 rt7 rt8 rt9 samples rt clock rt clock count actual start bit rxd 10 1 11000 0 lsb 0 perceived start bit reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count perceived and actual start bit rxd 11 1 1100 1 lsb 1 1 1 1 chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 268 freescale semiconductor figure 8-20 shows a burst of noise near th e beginning of the start bit that resets the rt clock. the sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. depending on the timing of th e start bit search and on th e data, the frame may be missed entirely or it may set the framing error flag. figure 8-20. start bit search example 5 in figure 8-21 , a noise burst makes the majo rity of data samples rt8, rt 9, and rt10 high. this sets the noise flag but does not reset the rt clock. in star t bits only, the rt8, rt9, and rt10 data samples are ignored. figure 8-21. start bit search example 6 8.4.5.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, fe, in sc i status register 1 (scisr1). a brea k character also sets the fe flag because a break character has no stop bit. the fe flag is set at the same time that the rdrf flag is set. reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 samples rt clock rt clock count start bit rxd 11 1 1101 0 lsb 1 1 1 1 1 00 0 00 0 0 0 no start bit found reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 1 1100 0 lsb 1 1 1 1 0 11 0 chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 269 8.4.5.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiv er baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples (r t8, rt9, and rt10) to fall outside the actual stop bit. a noise error wi ll occur if the rt8, rt9, and rt10 sa mples are not all the same logical values. a framing error will oc cur if the receiver clock is misaligned in such a way that the majority of the rt8, rt9, and rt10 stop bit samples are a logic 0. as the receiver samples an incoming frame, it re-s ynchronizes the rt clock on any valid falling edge within the frame. re synchronizati on within frames will correct a mis alignment between transmitter bit times and receiver bit times. 8.4.5.5.1 slow data tolerance figure 8-22 shows how much a slow received frame can be misaligned without caus ing a noise error or a framing error. the slow st op bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 8-22. slow data let?s take rtr as receiver rt clock and rt t as transmitter rt clock. for an 8-bit data character, it take s the receiver 9 bit times x 16 rtr cy cles +7 rtr cycles =151 rtr cycles to start data sampli ng of the stop bit. with the misaligned character shown in figure 8-22 , the receiver counts 151 rtr cycles at the point when the count of the transmitting device is 9 bit times x 16 rtt cycles = 144 rtt cycles. the maximum percent difference between the receiver count a nd the transmitter count of a slow 8-bit data character with no errors is: ((151 ? 144) / 151) x 100 = 4.63% for a 9-bit data character, it takes the receiver 10 bit times x 16 rtr cycles + 7 rtr cy cles = 167 rtr cycles to start data sampli ng of the stop bit. with the misaligned character shown in figure 8-22 , the receiver counts 167 rtr cycles at the point when the count of the transmitting device is 10 bit times x 16 rtt cycles = 160 rtt cycles. the maximum percent difference betw een the receiver count and the tran smitter count of a slow 9-bit character with no errors is: ((167 ? 160) / 167) x 100 = 4.19% msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 270 freescale semiconductor 8.4.5.5.2 fast data tolerance figure 8-23 shows how much a fast received frame can be misaligned. the fast stop bit ends at rt10 instead of rt16 but continues to be sampled at rt8, rt9, and rt10. figure 8-23. fast data for an 8-bit data character, it takes the receiver 9 bit times x 16 rtr cycles + 10 rtr cycles = 154 rtr cycles to finish data sampling of the stop bit. with the misaligned character shown in figure 8-23 , the receiver counts 154 rtr cycles at the point when the count of the transmitting device is 10 bit times x 16 rtt cycles = 160 rtt cycles. the maximum percent difference betw een the receiver count and the tran smitter count of a fast 8-bit character with no errors is: ((160 ? 154) / 160) x 100 = 3.75% for a 9-bit data character, it takes the receiver 10 bit times x 16 rtr cycles + 10 rtr cycles = 170 rtr cycles to finish data sampling of the stop bit. with the misaligned character shown in figure 8-23 , the receiver counts 170 rtr cycles at the point when the count of the transmitting device is 11 bit times x 16 rtt cycles = 176 rtt cycles. the maximum percent difference betw een the receiver count and the tran smitter count of a fast 9-bit character with no errors is: ((176 ? 170) / 176) x 100 = 3.40% 8.4.5.6 receiver wakeup to enable the sci to ignore transm issions intended only for other receivers in mult iple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bi t, rwu, in sci control register 2 (scicr2) puts the receiver into standby state during wh ich receiver interrupts ar e disabled.the sci will continue to load the receive data into the scidrh /l registers, but it will not set the rdrf flag. the transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. the wake bit in sci control regist er 1 (scicr1) determines how the sci is brought out of the standby state to process an incoming message . the wake bit enables either id le line wakeup or address mark wakeup. idle or next frame stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 271 8.4.5.6.1 idle input line wakeup (wake = 0) in this wakeup method, an idle condition on the rxd pin clears the rwu bit a nd wakes up the sci. the initial frame or frames of every message contain addressing information. all receivers evaluate the addressing information, and receivers for which the me ssage is addressed proce ss the frames that follow. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on sta ndby until another idle char acter appears on the rxd pin. idle line wakeup requires that messa ges be separated by at least one id le character and that no message contains idle characters. the idle character that wakes a receive r does not set the receiver idle bit, idle, or the receive data register full flag, rdrf. the idle line type bit, ilt, determ ines whether the receiver begins counti ng logic 1s as idle character bits after the start bit or after the stop bit. il t is in sci control register 1 (scicr1). 8.4.5.6.2 address mark wakeup (wake = 1) in this wakeup method, a logic 1 in the most significa nt bit (msb) position of a frame clears the rwu bit and wakes up the sci. the logic 1 in the msb position marks a frame as an address frame that contains addressing information. all receivers evaluate the addressing informati on, and the receivers for which the message is addressed proce ss the frames that follow. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit rema ins set and the receiver remains on standby until another address frame appears on the rxd pin. the logic 1 msb of an addr ess frame clears the receiv er?s rwu bit before the stop bit is received and sets the rdrf flag. address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle can cause the receiver to wake up immediately. 8.4.6 single-wire operation normally, the sci uses two pins fo r transmitting and receiving. in si ngle-wire operation, the rxd pin is disconnected from the sci. the sci uses the txd pin for both receiving and transmitting. figure 8-24. single-wire operation (loops = 1, rsrc = 1) rxd transmitter receiver txd chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 272 freescale semiconductor enable single-wire operation by setting the loops bit a nd the receiver source bit, rsrc, in sci control register 1 (scicr1). setting the l oops bit disables the path from th e rxd pin to the receiver. setting the rsrc bit connects the txd pin to the receiver. bo th the transmitter and receiver must be enabled (te = 1 and re = 1).the txdir bit (scisr2[1]) determin es whether the txd pin is going to be used as an input (txdir = 0) or an output (t xdir = 1) in this mode of operation. note in single-wire operation data from the txd pin is in verted if rxpol is set. 8.4.7 loop operation in loop operation the transmitter out put goes to the receiver input. the rxd pin is disconnected from the sci . figure 8-25. loop operation (loops = 1, rsrc = 0) enable loop operation by setting th e loops bit and clearing the rsrc bit in sci control register 1 (scicr1). setting the loops bit disa bles the path from the rxd pin to the receiver. clearing the rsrc bit connects the transmitter output to the receiver input. both the tr ansmitter and receiver must be enabled (te = 1 and re = 1). note in loop operation data from the transmitter is not recognized by the receiver if rxpol and txpol are not the same. 8.5 interrupts this section describes the interr upt originated by the sci block.the mcu must service the interrupt requests. table 8-17 lists the five interrupt sources of the sci. table 8-17. sci interrupt sources interrupt source local enable description tdre scisr1[7] tie active high le vel. indicates that a byte was transferred from scidrh/l to the transmit shift register. tc scisr1[6] tcie active high level. indi cates that a transmit is complete. rdrf scisr1[5] rie active high level. the rdrf interrupt indicates that received data is available in the sci data register. or scisr1[3] active high level. this interr upt indicates that an overrun condition has occurred. idle scisr1[4] ilie active high level. indica tes that receiver in put has become idle. rxd transmitter receiver txd chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 273 8.5.1 description of interrupt operation the sci only originates interrupt re quests. the following is a descript ion of how the sc i makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt number are chip dependent. the sci only has a single interrupt li ne (sci interrupt signal, active high operation) and all the following interrupts, when generated, ar e ored together and i ssued through that port. 8.5.1.1 tdre description the tdre interrupt is set high by the sci when the tr ansmit shift register re ceives a byte from the sci data register. a tdre interrupt indi cates that the transmit data regist er (scidrh/l) is empty and that a new byte can be written to the scid rh/l for transmission.clear tdre by reading sci status register 1 with tdre set and then writing to sci data register low (scidrl). 8.5.1.2 tc description the tc interrupt is set by the sci when a transmission has been comple ted.a tc interrupt indicates that there is no transmission in progress. tc is set high wh en the tdre flag is set and no data, preamble, or break character is being transmitted. when tc is se t, the txd pin becomes id le (logic 1). clear tc by reading sci status register 1 (scisr1) with tc set a nd then writing to sci data register low (scidrl).tc is cleared automatically when data, preamble , or break is queued and ready to be sent. 8.5.1.3 rdrf description the rdrf interrupt is set when the data in the receiv e shift register transfers to the sci data register. a rdrf interrupt indicates that the re ceived data has been transferred to the sci data register and that the byte can now be read by the mcu. the rdrf interrupt is cleared by reading the sci status register one (scisr1) and then reading sci data register low (scidrl). 8.5.1.4 or description the or interrupt is set when software fails to read th e sci data register before the receive shift register receives the next frame. the newly acqui red data in the shift regi ster will be lost in this case, but the data already in the sci data registers is not affected. the or interrupt is cleared by reading the sci status register one (scisr1) and then read ing sci data register low (scidrl). 8.5.1.5 idle description the idle interrupt is set when 10 c onsecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m = 1) appear on the receiver input. after th e idle is cleared, a valid frame must again set the rdrf flag before an idle condition can set the idle flag. clear idle by reading sc i status register 1 (scisr1) with idle set and then reading sci da ta register low (scidrl). 8.5.2 recovery from wait mode the sci interrupt request can be used to bring the cpu out of wait mode. chapter 8 serial communication interface (sciv4) mc9s12e256 data sheet, rev. 1.08 274 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 275 chapter 9 serial peripheral interface (spiv3) 9.1 introduction the spi module allows a duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status flags or the spi operation can be interrupt driven. 9.1.1 features the spiv3 includes these distinctive features: ? master mode and slave mode ? bidirectional mode ? slave select output ? mode fault error flag with cpu interrupt capability ? double-buffered data register ? serial clock with progr ammable polarity and phase ? control of spi operation during wait mode 9.1.2 modes of operation the spi functions in three modes, run, wait, and stop. ? run mode this is the basic mode of operation. ? wait mode spi operation in wait mode is a configurable low power mode, controlled by the spiswai bit located in the spicr2 register. in wait mode, if th e spiswai bit is clear, the spi operates like in run mode. if the spiswai bit is se t, the spi goes into a power c onservative state, with the spi clock generation turned off. if the spi is configured as a master, a ny transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is configured as a slave, reception and transmission of a byte conti nues, so that the slave stays synchronized to the master. ? stop mode the spi is inactive in stop mode for reduced power consumption. if the spi is configured as a master, any transmission in progre ss stops, but is resumed after cp u goes into run mode. if the spi is configured as a slave, reception and transmissi on of a byte continues, so that the slave stays synchronized to the master. this is a high level description only, detailed descriptions of operating modes are contained in section 9.4, ?functional description . ? chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 276 freescale semiconductor 9.1.3 block diagram figure 9-1 gives an overview on the spi architecture. the main parts of the spi are status, control, and data registers, shifter logic, ba ud rate generator, master/slave c ontrol logic, and port control logic. figure 9-1. spi block diagram 9.2 external signal description this section lists the name and desc ription of all ports incl uding inputs and outputs th at do, or may, connect off chip. the spiv3 module has a total of four external pins. 9.2.1 mosi ? master out/slave in pin this pin is used to transm it data out of the spi modul e when it is configured as a master and receive data when it is configured as slave. spi control register 1 spi control register 2 spi baud rate register spi status register spi data register shifter port control logic mosi sck interrupt control spi msb lsb lsbfe=1 lsbfe=0 lsbfe=0 lsbfe=1 data in lsbfe=1 lsbfe=0 data out 8 8 baud rate generator prescaler bus clock counter clock select sppr 3 3 spr baud rate phase + polarity control master slave sck in sck out master baud rate slave baud rate phase + polarity control control control cpol cpha 2 bidiroe spc0 2 modf spif sptef spi request interrupt ss shift clock sample clock chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 277 9.2.2 miso ? master in/slave out pin this pin is used to transmit data out of the spi module when it is c onfigured as a slave and receive data when it is configured as master. 9.2.3 ss ? slave select pin this pin is used to output the select signal from th e spi module to another peri pheral with which a data transfer is to take place when its c onfigured as a master and its used as an input to receive the slave select signal when the spi is configured as slave. 9.2.4 sck ? serial clock pin this pin is used to output the clock with respect to which the spi transfer s data or receive clock in case of slave. 9.3 memory map and register definition this section provides a detailed description of address space and registers used by the spi. the memory map for the spiv3 is given below in table 9-1 . the address listed for each register is the sum of a base address and an a ddress offset. the base addres s is defined at the soc le vel and the address offset is defined at the module level. reads from the reserved bits return zeros and writ es to the reserved bits have no effect. 9.3.1 module memory map table 9-1. spiv3 memory map address use access 0x0000 spi control register 1 (spicr1) r/w 0x0001 spi control register 2 (spicr2) r/w 1 1 certain bits are non-writable. 0x0002 spi baud rate register (spibr) r/w 1 0x0003 spi status register (spisr) r 2 2 writes to this register are ignored. 0x0004 reserved ? 2,3 3 reading from this register returns all zeros. 0x0005 spi data register (spidr) r/w 0x0006 reserved ? 2,3 0x0007 reserved ? 2,3 chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 278 freescale semiconductor 9.3.2 register descriptions this section consists of register de scriptions in address order. each de scription includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. 9.3.2.1 spi control register 1 (spicr1) read: anytime write: anytime name 76543210 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w spicr2 r0 0 0 modfen bidiroe 0 spiswai spc0 w spibr r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w spisr r spif 0 sptef modf 0 0 0 0 w reserved r w spidr r bit 7654322bit 0 w reserved r w reserved r w = unimplemented or reserved figure 9-2. spi register summary 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset00000100 figure 9-3. spi control register 1 (spicr1) chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 279 table 9-2. spicr1 field descriptions field description 7 spie spi interrupt enable bit ? this bit enables spi interrupt requests, if spif or modf status flag is set. 0 spi interrupts disabled. 1 spi interrupts enabled. 6 spe spi system enable bit ? this bit enables the spi system and dedicates the spi port pins to spi system functions. if spe is cleared, spi is disabled and forced into idle state, status bits in spisr register are reset. 0 spi disabled (lower power consumption). 1 spi enabled, port pins are dedicated to spi functions. 5 sptie spi transmit interrupt enable ? this bit enables spi interrupt requests, if sptef flag is set. 0 sptef interrupt disabled. 1 sptef interrupt enabled. 4 mstr spi master/slave mode select bit ? this bit selects, if the spi operates in master or slave mode. switching the spi from master to slave or vice vers a forces the spi system into idle state. 0 spi is in slave mode 1 spi is in master mode 3 cpol spi clock polarity bit ? this bit selects an inverted or non-inve rted spi clock. to transmit data between spi modules, the spi modules must have identical cpol valu es. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 active-high clocks selected. in idle state sck is low. 1 active-low clocks selected. in idle state sck is high. 2 cpha spi clock phase bit ? this bit is used to select the spi clock format. in master mode, a change of this bit will abort a transmission in progress and fo rce the spi system into idle state. 0 sampling of data occurs at odd edges (1,3,5,...,15) of the sck clock 1 sampling of data occurs at even edges (2,4,6,...,16) of the sck clock 1 ssoe slave select output enable ? the ss output feature is enabled only in master mode, if modfen is set, by asserting the ssoe as shown in ta bl e 9 - 3 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 lsbfe lsb-first enable ? this bit does not affect the position of th e msb and lsb in the data register. reads and writes of the data register always have the msb in bi t 7. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 data is transferred most significant bit first. 1 data is transferred least significant bit first. table 9-3. ss input / output selection modfen ssoe master mode slave mode 00 ss not used by spi ss input 01 ss not used by spi ss input 10ss input with modf feature ss input 11 ss is slave select output ss input chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 280 freescale semiconductor 9.3.2.2 spi control register 2 (spicr2) read: anytime write: anytime; writes to the reserved bits have no effect 76543210 r0 0 0 modfen bidiroe 0 spiswai spc0 w reset00000000 = unimplemented or reserved figure 9-4. spi control register 2 (spicr2) table 9-4. spicr2 field descriptions field description 4 modfen mode fault enable bit ? this bit allows the modf failure being det ected. if the spi is in master mode and modfen is cleared, then the ss port pin is not used by the spi. in slave mode, the ss is available only as an input regardless of the value of modfen. for an ov erview on the impact of the modfen bit on the ss port pin configuration refer to ta bl e 9 - 3 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0ss port pin is not used by the spi 1ss port pin with modf feature 3 bidiroe output enable in the bidirectional mode of operation ? this bit controls the mo si and miso output buffer of the spi, when in bidirectional mo de of operation (spc0 is set). in mast er mode this bit controls the output buffer of the mosi port, in slave mode it controls the ou tput buffer of the miso por t. in master mode, with spc0 set, a change of this bit will abort a transmission in progress and force the spi into idle state. 0 output buffer disabled 1 output buffer enabled 1 spiswai spi stop in wait mode bit ? this bit is used for power conservation while in wait mode. 0 spi clock operates normally in wait mode 1 stop spi clock generation when in wait mode 0 spc0 serial pin control bit 0 ? this bit enables bidirectional pin configurations as shown in ta bl e 9 - 5 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state table 9-5. bidirectional pin configurations pin mode spc0 bidiroe miso mosi master mode of operation normal 0 x master in master out bidirectional 1 0 miso not used by spi master in 1 master i/o slave mode of operation normal 0 x slave out slave in bidirectional 1 0 slave in mosi not used by spi 1 slave i/o chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 281 9.3.2.3 spi baud rate register (spibr) read: anytime write: anytime; writes to the reserved bits have no effect the baud rate divisor equation is as follows: the baud rate can be calculated with the following equation: 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset00000000 = unimplemented or reserved figure 9-5. spi baud rate register (spibr) table 9-6. spibr field descriptions field description 6:4 sppr[2:0] spi baud rate preselection bits ? these bits specify the spi baud rates as shown in ta b l e 9 - 7 . in master mode, a change of these bits will abort a transmission in progress and force the sp i system into idle state. 2:0 spr[2:0} spi baud rate selection bits ? these bits specify the spi baud rates as shown in ta b l e 9 - 7 . in master mode, a change of these bits will abort a transmission in progress and forc e the spi system into idle state. baudratedivisor sppr 1 + () 2 ? spr 1 + () = baud rate busclock baudratedivisor ? = chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 282 freescale semiconductor table 9-7. example spi baud rate selection (25 mhz bus clock) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate 000000212.5 mhz 00000146.25 mhz 00001083.125 mhz 000011161.5 625 mhz 00010032781.25 khz 00010164390.63 khz 000110128195.31 khz 00011125697.66 khz 00100046.25 mhz 00100183.125 mhz 001010161.5 625 mhz 00101132781.25 khz 00110064390.63 khz 001101128195.31 khz 00111025697.66 khz 00111151248.83 khz 01000064. 16667 mhz 010001122. 08333 mhz 010010241. 04167 mhz 01001148520.83 khz 01010096260.42 khz 010101192130.21 khz 01011038465.10 khz 01011176832.55 khz 01100083.125 mhz 011001161.5 625 mhz 01101032781.25 khz 01101164390.63 khz 011100128195.31 khz 01110125697.66 khz 01111051248.83 khz 011111102424.41 khz 100000102.5 mhz 100001201.25 mhz chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 283 note in slave mode of spi s-cloc k speed div2 is not supported. 10001040625 khz 10001180312.5 khz 100100160156.25 khz 10010132078.13 khz 10011064039.06 khz 100111128019.53 khz 101000122. 08333 mhz 101001241. 04167 mhz 10101048520.83 khz 10101196260.42 khz 101100192130.21 khz 10110138465.10 khz 10111076832.55 khz 101111153616.28 khz 110000141. 78571 mhz 11000128892.86 khz 11001056446.43 khz 110011112223.21 khz 110100224111.61 khz 11010144855.80 khz 11011089627.90 khz 110111179213.95 khz 111000161.5 625 mhz 11100132781.25 khz 11101064390.63 khz 111011128195.31 khz 11110025697.66 khz 11110151248.83 khz 111110102424.41 khz 111111204812.21 khz table 9-7. example spi baud rate selection (25 mhz bus clock) (continued) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 284 freescale semiconductor 9.3.2.4 spi status register (spisr) read: anytime write: has no effect 9.3.2.5 spi data register (spidr) read: anytime; normally read only after spif is set write: anytime the spi data register is both the input and output regi ster for spi data. a write to this register allows a data byte to be queued and transmitted. for a spi configured as a master, a queued data byte is transmitted 76543210 r spif 0 sptef modf 0 0 0 0 w reset00100000 = unimplemented or reserved figure 9-6. spi status register (spisr) table 9-8. spisr field descriptions field description 7 spif spif interrupt flag ? this bit is set after a received data byte has been transferred into the spi data register. this bit is cleared by reading the spisr register (wit h spif set) followed by a read access to the spi data register. 0 transfer not yet complete 1 new data copied to spidr 5 sptef spi transmit empty interrupt flag ? if set, this bit indicates that the tran smit data register is empty. to clear this bit and place data into the transmit data register, spisr has to be read with sptef = 1, followed by a write to spidr. any write to the spi data register wit hout reading sptef = 1, is effectively ignored. 0 spi data register not empty 1 spi data register empty 4 modf mode fault flag ? this bit is set if the ss input becomes low while the spi is configured as a master and mode fault detection is enabled, modfen bit of spicr2 regi ster is set. refer to modfen bit description in section 9.3.2.2, ?spi control register 2 (spicr2) . ? the flag is cleared automatically by a read of the spi status register (with modf set) followed by a write to the spi control register 1. 0 mode fault has not occurred. 1 mode fault has occurred. 76543210 r bit 7654322bit 0 w reset00000000 figure 9-7. spi data register (spidr) chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 285 immediately after the previous tran smission has completed. the spi tran smitter empty flag sptef in the spisr register indicates when the spi data register is ready to accept new data. reading the data can oc cur anytime from after the spif is set to before the end of the next transfer. if the spif is not serviced by the en d of the successive transfers, those data bytes are lost and the data within the spidr retains the first byte until spif is serviced. 9.4 functional description the spi module allows a duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status flag s or spi operation can be interrupt driven. the spi system is enabled by setting the spi enable (spe) bit in spi control register 1. while spe bit is set, the four associated spi port pins are dedicated to the spi function as: ? slave select (ss ) ? serial clock (sck) ? master out/slave in (mosi) ? master in/slave out (miso) the main element of the spi system is the spi data register. the 8-bit data register in the master and the 8-bit data register in the slave are linked by the mosi and miso pins to form a distri buted 16-bit register. when a data transfer operation is perfo rmed, this 16-bit register is serially shifted ei ght bit positions by the s-clock from the master, so data is exchanged between th e master and the slave. da ta written to the master spi data register becomes the output data for the slave, and data read from the master spi data register after a transfer operation is th e input data from the slave. a read of spisr with sptef = 1 followed by a write to spidr puts data into th e transmit data register. when a transfer is complete, received data is moved into th e receive data register. data may be read from this double-buffered system any time before the next transfer has comp leted. this 8-bit data register acts as the spi receive data register fo r reads and as the spi transmit data register for writes. a single spi register address is used for reading data from the read data buffer and fo r writing data to the transmit data register. the clock phase control bit (cpha) and a clock polarity control bit (cpo l) in the spi control register 1 (spicr1) select one of four possi ble clock formats to be used by th e spi system. the cpol bit simply selects a non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered sck edges or on even numbered sck edges (see section 9.4.3, ?transmission formats? ). the spi can be configured to opera te as a master or as a slave. when the mstr bit in spi control register1 is set, master mode is selected, when the mstr bit is clear, slave mode is selected. chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 286 freescale semiconductor 9.4.1 master mode the spi operates in master mode when the mstr b it is set. only a master spi module can initiate transmissions. a transmission begins by writing to the master spi data register. if the shift register is empty, the byte immedi ately transfers to the shift register. th e byte begins shifting out on the mosi pin under the control of the serial clock. ?s-clock the spr2, spr1, and spr0 baud rate selection bi ts in conjunction with the sppr2, sppr1, and sppr0 baud rate preselection bits in the spi baud rate re gister control the ba ud rate generator and determine the speed of the transmission. the sc k pin is the spi clock output. through the sck pin, the baud rate generator of th e master controls the shift re gister of the slave peripheral. ? mosi and miso pins in master mode, the function of the serial data output pin (mosi) and th e serial data input pin (miso) is determined by the spc0 and bidiroe control bits. ?ss pin if modfen and ssoe bit are set, the ss pin is configured as slave select output. the ss output becomes low during each transmission and is high when the spi is in idle state. if modfen is set and ssoe is cleared, the ss pin is configured as input for detecting mode fault error. if the ss input becomes low this indicates a mode fault error where another master tries to drive the mosi and sck lines. in this case, the spi immediately switches to slave mode, by clearing the mstr bit and also disables the slav e output buffer miso (or siso in bidirectional mode). so the result is that all outputs are disa bled and sck, mosi and miso are inputs. if a transmission is in progress when the mode fault occurs, the transm ission is aborted and the spi is forced into idle state. this mode fault error also sets the mode fault (modf) flag in the spi status register (spisr). if the spi interrupt enable bit (spie) is set when the modf flag gets set, then an spi interrupt sequence is also requested. when a write to the spi data register in the master oc curs, there is a half sck-cy cle delay. after the delay, sck is started within the master. th e rest of the transfer operation di ffers slightly, depending on the clock format specified by the spi clock phase bi t, cpha, in spi control register 1 (see section 9.4.3, ?transmission formats? ). note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0, bidiroe with spc0 set, sppr2?sppr0 and spr2?spr0 in master mode will abort a transmission in progress a nd force the spi into idle state. the remote slave cannot detect this, therefor e the master has to ensure that the remote slave is set back to idle state. chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 287 9.4.2 slave mode the spi operates in slave mode when the ms tr bit in spi control register1 is clear. ? sck clock in slave mode, sck is the spi clock input from the master. ? miso and mosi pins in slave mode, the function of the serial data output pin (miso) and serial da ta input pin (mosi) is determined by the spc0 bit and bidi roe bit in spi control register 2. ?ss pin the ss pin is the slave select input. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. if ss goes high, the spi is forced into idle state. the ss input also controls the serial data output pin, if ss is high (not selected), the serial data output pin is high impedance, and, if ss is low the first bit in the spi data register is driven out of the serial data output pin. also , if the slave is not selected (ss is high), then the sck input is ignored and no internal shifting of the spi shift register takes place. although the spi is capable of duplex operation, some spi peripherals are capable of only receiving spi data in a slave mode. for these simpler devices, there is no serial data out pin. note when peripherals with duplex capabi lity are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave?s serial data output line. as long as no more than one slave devi ce drives the system slave?s serial data output line, it is possible for several slaves to receive the same transmission from a mast er, although the master wo uld not receive return information from all of the receiving slaves. if the cpha bit in spi control register 1 is clear , odd numbered edges on the sck input cause the data at the serial data input pin to be latched. even numbered e dges cause the value previ ously latched from the serial data input pin to shift in to the lsb or msb of the spi shif t register, depending on the lsbfe bit. if the cpha bit is set, even numbere d edges on the sck input cause the data at the serial da ta input pin to be latched. odd numbered edge s cause the value previously latched from th e serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. when cpha is set, the first edge is used to get the first data bit onto the serial data output pin. when cpha is clear and the ss input is low (slave selected), the first bit of the spi data is driven out of the serial data output pin. after the eighth shift, the transfer is cons idered complete and the received data is transferred into the spi data register. to indicate transfer is comp lete, the spif flag in the spi status register is set. note a change of the bits cpol, cpha , ssoe, lsbfe, modfen, spc0 and bidiroe with spc0 set in slave mode will corrupt a transmission in progress and has to be avoided. chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 288 freescale semiconductor 9.4.3 transmission formats during an spi transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. the serial clock (sck) synchronizes shifting and samp ling of the information on the two serial data lines. a slave select li ne allows selection of an individual slave spi device, slave devices that are not selected do not interfere with spi bus activities. optionally, on a master spi device, the slave select line can be used to indicate multiple-master bus contention. figure 9-8. master/slave transfer block diagram 9.4.3.1 clock phase and polarity controls using two bits in the spi control regi ster1, software selects one of four combinations of se rial clock phase and polarity. the cpol clock polarity control bit specifies an acti ve high or low clock and ha s no significant effect on the transmission format. the cpha clock phase control bit selects one of two fundamentally different transmission formats. clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are change d between transmi ssions to allow a master device to communicate with peripheral sl aves having different requirements. 9.4.3.2 cpha = 0 transfer format the first edge on the sck line is used to clock the firs t data bit of the slave into the master and the first data bit of the master into the slave. in some peripherals, the first bit of the slave?s data is available at the slave?s data out pin as soon as the slav e is selected. in this fo rmat, the first sck edge is issued a half cycle after ss has become low. a half sck cycle later, the second edge appears on th e sck line. when this second edge occurs, the value previously latched from the serial data input pin is shifted into the lsb or msb of the shift register, depending on lsbfe bit. after this second edge, the ne xt bit of the spi master data is transmit ted out of the serial data output pin of the master to the serial input pin on the slave. this process continues for a total of 16 edges on the sck line, with data being latched on odd numbered edges and shifted on ev en numbered edges. shift register shift register baud rate generator master spi slave spi mosi mosi miso miso sck sck ss ss v dd chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 289 data reception is double buffered. data is shifted serially into the spi shif t register during the transfer and is transferred to the parallel spi data re gister after the last bit is shifted in. after the 16th (last) sck edge: ? data that was previously in the master spi data regist er should now be in th e slave data register and the data that was in the slave da ta register should be in the master. ? the spif flag in the spi status register is set indicating that the transfer is complete. figure 9-9 is a timing diagram of an spi transfer where cpha = 0. sck waveforms are shown for cpol = 0 and cpol = 1. the diagram may be interpre ted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the mast er and the slave. the miso signal is the output from the slave and the mosi signal is the output from the master. the ss pin of the master must be either high or reconfigured as a general-purpose output not affecting the spi. figure 9-9. spi clock format 0 (cpha = 0) in slave mode, if the ss line is not deasserted between the successi ve transmissions then the content of the spi data register is not transmitted, instead th e last received byte is transmitted. if the ss line is deasserted for at least minimum idle time (half sc k cycle) between successive transmissions then the content of the spi data register is transmitted. tl begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso tt if next transfer begins here for t t , t l , t l minimum 1/2 sck ti tl t l = minimum leading time before the first sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 34 56 78910111213141516 sck edge nr. end of idle state begin of idle state chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 290 freescale semiconductor in master mode, with slave select output enabled the ss line is always deassert ed and reasserted between successive transfers for at least minimum idle time. 9.4.3.3 cpha = 1 transfer format some peripherals require the first sc k edge before the first data bit b ecomes available at the data out pin, the second edge clocks data into the system. in this format, the first sck edge is issued by setting the cpha bit at the beginning of th e 8-cycle transfer operation. the first edge of sck occu rs immediately after the half sck cloc k cycle synchronizati on delay. this first edge commands the slave to transfer its first data bit to the serial data input pin of the master. a half sck cycle later, the second edge appears on th e sck pin. this is the la tching edge for both the master and slave. when the third edge occurs, the value previously latche d from the serial data input pin is shifted into the lsb or msb of the spi shif t register, depending on lsbfe bit. after this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the seri al input pin on the slave. this process continues for a total of 16 edges on the sck line with data bei ng latched on even numbered edges and shifting taking pl ace on odd numbered edges. data reception is double buffer ed, data is serially shifted into the spi shift register duri ng the transfer and is transferred to the parallel spi data re gister after the last bit is shifted in. after the 16th sck edge: ? data that was previously in the spi data register of the master is now in the data register of the slave, and data that was in the data re gister of the slave is in the master. ? the spif flag bit in spisr is set indicating that the transfer is complete. figure 9-10 shows two clocking vari ations for cpha = 1. the diagram ma y be interpreted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the ss pin of the master mu st be either high or reconfigured as a general-purpose output not affecting the spi. the ss line can remain active low between successive transfers (can be tied low at all time s). this format is sometimes preferred in systems ha ving a single fixed master and a single slave that drive the miso data line. ? back-to-back transfers in master mode in master mode, if a tran smission has completed and a new data byte is available in the spi data register, this byte is send out immediately wit hout a trailing and minimum idle time. the spi interrupt request flag (spi f) is common to both the master a nd slave modes. spif gets set one half sck cycle after the last sck edge. chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 291 figure 9-10. spi clock format 1 (cpha = 1) 9.4.4 spi baud rate generation baud rate generation consists of a series of divider st ages. six bits in the spi baud rate register (sppr2, sppr1, sppr0, spr2, spr1, and spr0) de termine the divisor to the spi module clock which results in the spi baud rate. the spi clock rate is determined by the product of the value in the baud rate preselection bits (sppr2?sppr0) and the value in the baud rate se lection bits (spr2?spr0). the module clock divisor equation is shown in figure 9-11 when all bits are clear (the default condition), the spi module clock is divided by 2. when the selection bits (spr2?spr0) are 001 and the preselection bits (sppr2?sppr0) are 000, the module clock divisor becomes 4. when the selection bits are 010, the module clock divisor becomes 8 etc. when the preselection bits are 001, the divisor determin ed by the selection bits is multiplied by 2. when the preselection bits are 010, the divi sor is multiplied by 3, etc. see table 9-7 for baud rate calculations for all bit conditions, based on a 25-mhz bus clock. the two sets of selects al lows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. tl tt for t t , t l , t l minimum 1/2 sck ti tl if next transfer begins here begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t l = minimum leading time before the first sc k edge, not required for back to back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back to back transfers 1 2 34 56 78910111213141516 sck edge nr. end of idle state begin of idle state chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 292 freescale semiconductor the baud rate generator is activated only when the spi is in the master mode and a serial transfer is taking place. in the other cases, the divider is disabled to decrease i dd current. figure 9-11. baud rate divisor equation 9.4.5 special features 9.4.5.1 ss output the ss output feature automa tically drives the ss pin low during transmission to select external devices and drives it high duri ng idle to deselect external devices. when ss output is selected, the ss output pin is connected to the ss input pin of the external device. the ss output is available only in master mode dur ing normal spi operation by asserting ssoe and modfen bit as shown in table 9-3 . the mode fault feature is disabled while ss output is enabled. note care must be taken when using the ss output feature in a multimaster system because the mode fault feature is not available fo r detecting system errors between masters. 9.4.5.2 bidirectional mode (mosi or miso) the bidirectional mode is selected when the spc0 bit is set in spi control register 2 (see table 9-9 ). in this mode, the spi uses only one serial data pin for the interface with external device(s). the mstr bit decides which pin to use. the mosi pin becomes the serial data i/o (m omi) pin for the master mode, and the miso pin becomes serial data i/o (siso) pin for the slave mode. the miso pin in master mode and mosi pin in slave mode are not used by the spi. table 9-9. normal mode and bidirectional mode when spe = 1 master mode mstr = 1 slave mode mstr = 0 normal mode spc0 = 0 bidirectional mode spc0 = 1 baudratedivisor sppr 1 + () 2 ? spr 1 + () = spi mosi miso serial out serial in spi mosi miso serial in serial out spi momi serial out serial in bidiroe spi siso serial in serial out bidiroe chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 293 the direction of each serial i/o pin depends on the bidiroe bit. if th e pin is configured as an output, serial data from the shift re gister is driven out on the pin. the same pi n is also the serial input to the shift register. the sck is output for the master mode and input for the slave mode. the ss is the input or output for the master mode, a nd it is always the input for the slave mode. the bidirectional mode does not affect sck and ss functions. note in bidirectional master mo de, with mode fault enab led, both data pins miso and mosi can be occupied by the spi, though mosi is normally used for transmissions in bidirect ional mode and miso is not used by the spi. if a mode fault occurs, the spi is automatical ly switched to slave mode, in this case miso becomes occupied by the spi and mosi is not used. this has to be considered, if the miso pin is used for other purpose. 9.4.6 error conditions the spi has one error condition: ? mode fault error 9.4.6.1 mode fault error if the ss input becomes low while the spi is configured as a mast er, it indicates a system error where more than one master may be trying to drive the mosi and sck lines simultaneous ly. this condition is not permitted in normal operation, the modf bit in the spi status register is set automatically provided the modfen bit is set. in the special case where the spi is in master mode and modfen bit is cleared, the ss pin is not used by the spi. in this special case, the mode fault error function is inhibited and modf re mains cleared. in case the spi system is configured as a slave, the ss pin is a dedicated input pin. mode fault error doesn?t occur in slave mode. if a mode fault error occurs the spi is switched to slave mode, with the exception that the slave output buffer is disabled. so sck, miso and mosi pins ar e forced to be high impedance inputs to avoid any possibility of conflict w ith another output driver. a transmission in progress is aborted and the spi is forced into idle state. if the mode fault error occurs in th e bidirectional mode for a spi system configured in master mode, output enable of the momi (mosi in bidirec tional mode) is cleared if it was se t. no mode fault error occurs in the bidirectional mode for spi sy stem configured in slave mode. the mode fault flag is cleared automatically by a read of the spi status register (with modf set) followed by a write to spi control register 1. if the mode fault flag is cleare d, the spi becomes a normal master or slave again. chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 294 freescale semiconductor 9.4.7 operation in run mode in run mode with the spi system enab le (spe) bit in the spi control regist er clear, the spi system is in a low-power, disabled state. spi regi sters remain accessible, but clocks to the core of this module are disabled. 9.4.8 operation in wait mode spi operation in wait mode depends upon the state of the spiswai bit in spi control register 2. ? if spiswai is clear, the spi operates normally when the cpu is in wait mode ? if spiswai is set, spi clock generation ceases and the spi module enters a power conservation state when the cpu is in wait mode. ? if spiswai is set and the spi is configured for master, any transmis sion and reception in progress stops at wait mode entry. the transm ission and reception resumes when the spi exits wait mode. ? if spiswai is set and the spi is configured as a slave, any transm ission and reception in progress continues if the sck continues to be driven from the master. this keeps the slave synchronized to the master and the sck. if the master transmits several byt es while the slave is in wait m ode, the slave will continue to send out bytes consiste nt with the operation mode at the start of wait mode (i.e. if the slave is currently sending its spidr to the master, it will continue to send the same byte. else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). note care must be taken when expecting data from a mast er while the slave is in wait or stop mode. even though the shift register will continue to operate, the rest of the spi is shut dow n (i.e. a spif interrupt will not be generated until exiting stop or wait m ode). also, the byte from the shift register will not be copied into the spidr register until after the slave spi has exited wait or stop mode. a spif flag and spidr c opy is only generate d if wait mode is entered or exited during a tranmissi on. if the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a spif nor a spidr copy will occur. 9.4.9 operation in stop mode stop mode is dependent on the system. the spi enters stop mode when the module clock is disabled (held high or low). if the spi is in master mode and exchanging data when the cpu enters stop mode, the transmission is frozen until the cpu exits stop mode. after stop, data to and from the external spi is exchanged correctly. in slave mode, the spi will stay synchronized with the master. the stop mode is not dependent on the spiswai bit. chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 295 9.5 reset the reset values of registers and signals are desc ribed in the memory map and registers section (see section 9.3, ?memory map and register definition? ) which details the regist ers and their bit-fields. ? if a data transmission occurs in slave mode after reset without a write to sp idr, it will transmit garbage, or the byte last received from the master before the reset. ? reading from the spidr after reset will always read a byte of zeros. 9.6 interrupts the spiv3 only originates interrupt requests when spi is enabled (spe bit in spicr1 set). the following is a description of how the spiv3 makes a request and how the mcu should acknowledge that request. the interrupt vector offset and inte rrupt priority are chip dependent. the interrupt flags modf, spif and sptef are logi cally ored to generate an interrupt request. 9.6.1 modf modf occurs when the master detects an error on the ss pin. the master spi must be configured for the modf feature (see table 9-3 ). after modf is set, the current transf er is aborted and th e following bit is changed: ? mstr = 0, the master bit in spicr1 resets. the modf interrupt is reflected in the status regist er modf flag. clearing the flag will also clear the interrupt. this interrupt will stay active while the modf flag is set. modf has an automatic clearing process which is described in section 9.3.2.4, ?spi status register (spisr) . ? 9.6.2 spif spif occurs when new data has been received and copied to the spi data register. after spif is set, it does not clear until it is serviced. spif has an au tomatic clearing process which is described in section 9.3.2.4, ?spi status register (spisr) . ? in the event that the spif is not serviced before the end of the next transfer (i.e. spif remain s active throughout another tr ansfer), the latter transfers will be ignored and no new data will be copied into the spidr. 9.6.3 sptef sptef occurs when the spi data regi ster is ready to accept new data. after sptef is set, it does not clear until it is serviced. sptef ha s an automatic clearing process which is described in section 9.3.2.4, ?spi status register (spisr) . ? chapter 9 serial peripheral interface (spiv3) mc9s12e256 data sheet, rev. 1.08 296 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 297 chapter 10 inter-integrated circuit (iicv2) 10.1 introduction the inter-ic bus (iic) is a two-wire , bidirectional serial bus that provides a simp le, efficient method of data exchange between de vices. being a two-wire device, the iic bus minimizes the need for large numbers of connections between devices, and eliminates the ne ed for an address decoder. this bus is suitable for applicat ions requiring occasional communications over a short distance between a number of devices. it also provides flexibility, allowing additional device s to be connected to the bus for further expansion and system development. the interface is designed to opera te up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communication length and the number of de vices that can be conn ected are limited by a maximum bus capacitance of 400 pf. 10.1.1 features the iic module has the following key features: ? compatible with i2c bus standard ? multi-master operation ? software programmable for one of 256 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection 10.1.2 modes of operation the iic functions the same in normal, special, and emulation modes. it has two low power modes: wait and stop modes. chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 298 freescale semiconductor 10.1.3 block diagram the block diagram of the iic module is shown in figure 10-1 . figure 10-1. iic block diagram 10.2 external signal description the iicv2 module has two external pins. 10.2.1 iic_scl ? serial clock line pin this is the bidirectional serial cl ock line (scl) of the module, compat ible to the iic bus specification. 10.2.2 iic_sda ? serial data line pin this is the bidirectional serial da ta line (sda) of the module, comp atible to the iic bus specification. 10.3 memory map and register definition this section provides a detailed description of all memory and registers for the iic module. 10.3.1 module memory map the memory map for the iic module is given below in figure 10-2 . the address listed for each register is the address offset.the total address for each register is the sum of th e base address for the iic module and the address offset for each register. in/out data shift register address compare sda interrupt clock control start stop arbitration control scl bus_clock iic registers chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 299 10.3.2 register descriptions this section consists of re gister descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. 10.3.2.1 iic address register (ibad) read and write anytime this register contains the address the iic bus w ill respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. register name bit 7654321bit 0 ibad r adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 w ibfd r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w ibcr r iben ibie ms/sl tx/rx txak 00 ibswai w rsta ibsr r tcf iaas ibb ibal 0srw ibif rxak w ibdr r d7 d6 d5 d4 d3 d2 d1 d0 w = unimplemented or reserved figure 10-2. iic register summary 76543210 r adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 w reset00000000 = unimplemented or reserved figure 10-3. iic bus address register (ibad) table 10-1. ibad field descriptions field description 7:1 adr[7:1] slave address ? bit 1 to bit 7 contain the specific slave address to be used by the iic bus module.the default mode of iic bus is slave mode for an address match on the bus. 0 reserved reserved ? bit 0 of the ibad is reserved for future compatibility. this bit will always read 0. chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 300 freescale semiconductor 10.3.2.2 iic frequency di vider register (ibfd) read and write anytime 76543210 r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w reset00000000 figure 10-4. iic bus frequency divider register (ibfd) table 10-2. ibfd field descriptions field description 7:0 ibc[7:0] i bus clock rate 7:0 ? this field is used to prescale the clock for bit rate selection. the bit clock generator is implemented as a prescale divider ? ibc7:6, prescaled sh ift register ? ibc5:3 select the prescaler divider and ibc2-0 select the shift register tap point. the ibc bits are decoded to give the tap and prescale values as shown in ta bl e 1 0 - 3 . table 10-3. i-bus tap and prescale values ibc2-0 (bin) scl tap (clocks) sda tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4 ibc5-3 (bin) scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 0002741 0012742 0102964 0116968 10014171416 10130333032 11062656264 111 126 129 126 128 chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 301 the number of clocks from the falling edge of scl to the first tap (tap[1 ]) is defined by the values shown in the scl2tap column of table 10-3 , all subsequent tap poi nts are separated by 2 ibc5-3 as shown in the tap2tap column in table 10-3 . the scl tap is used to generated th e scl period and the sda tap is used to determine the delay from the falling edge of scl to sda changing, the sda hold time. ibc7?6 defines the multiplier factor mul. the values of mul are shown in the table 10-4 . figure 10-5. scl divider and sda hold table 10-4. multiplier factor ibc7-6 mul 00 01 01 02 10 04 11 reserved scl divider sda hold scl sda sda scl start condition stop condition scl hold(start) scl hold(stop) chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 302 freescale semiconductor the equation used to generate the divi der values from the ibfd bits is: scl divider = mul x {2 x (scl2tap + [(scl_tap -1) x tap2tap] + 2)} the sda hold delay is equal to the cpu clock pe riod multiplied by the sda hold value shown in table 10-5 . the equation used to generate the sd a hold value from the ibfd bits is: sda hold = mul x {scl2tap + [(sda_tap - 1) x tap2tap] + 3} the equation for scl hold values to generate the start and stop conditions fr om the ibfd bits is: scl hold(start) = mul x [scl2start + (scl_tap - 1) x tap2tap] scl hold(stop) = mul x [scl2stop + (scl_tap - 1) x tap2tap] table 10-5. iic divider and hold values (sheet 1 of 5) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) mul = 1 00 20 7 6 11 01 22 7 7 12 02 24 8 8 13 03 26 8 9 14 04 28 9 10 15 05 30 9 11 16 06 34 10 13 18 07 40 10 16 21 08 28 7 10 15 09 32 7 12 17 0a 36 9 14 19 0b 40 9 16 21 0c 44 11 18 23 0d 48 11 20 25 0e 56 13 24 29 0f 68 13 30 35 10 48 9 18 25 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1a 112 17 54 57 1b 128 17 62 65 1c 144 25 70 73 1d 160 25 78 81 1e 192 33 94 97 1f 240 33 118 121 chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 303 20 160 17 78 81 21 192 17 94 97 22 224 33 110 113 23 256 33 126 129 24 288 49 142 145 25 320 49 158 161 26 384 65 190 193 27 480 65 238 241 28 320 33 158 161 29 384 33 190 193 2a 448 65 222 225 2b 512 65 254 257 2c 576 97 286 289 2d 640 97 318 321 2e 768 129 382 385 2f 960 129 478 481 30 640 65 318 321 31 768 65 382 385 32 896 129 446 449 33 1024 129 510 513 34 1152 193 574 577 35 1280 193 638 641 36 1536 257 766 769 37 1920 257 958 961 38 1280 129 638 641 39 1536 129 766 769 3a 1792 257 894 897 3b 2048 257 1022 1025 3c 2304 385 1150 1153 3d 2560 385 1278 1281 3e 3072 513 1534 1537 3f 3840 513 1918 1921 mul = 2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4a 72 18 28 38 4b 80 18 32 42 table 10-5. iic divider and hold values (sheet 2 of 5) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 304 freescale semiconductor 4c 88 22 36 46 4d 96 22 40 50 4e 112 26 48 58 4f 136 26 60 70 50 96 18 36 50 51 112 18 44 58 52 128 26 52 66 53 144 26 60 74 54 160 34 68 82 55 176 34 76 90 56 208 42 92 106 57 256 42 116 130 58 160 18 76 82 59 192 18 92 98 5a 224 34 108 114 5b 256 34 124 130 5c 288 50 140 146 5d 320 50 156 162 5e 384 66 188 194 5f 480 66 236 242 60 320 34 156 162 61 384 34 188 194 62 448 66 220 226 63 512 66 252 258 64 576 98 284 290 65 640 98 316 322 66 768 130 380 386 67 960 130 476 482 68 640 66 316 322 69 768 66 380 386 6a 896 130 444 450 6b 1024 130 508 514 6c 1152 194 572 578 6d 1280 194 636 642 6e 1536 258 764 770 6f 1920 258 956 962 70 1280 130 636 642 71 1536 130 764 770 72 1792 258 892 898 73 2048 258 1020 1026 74 2304 386 1148 1154 75 2560 386 1276 1282 76 3072 514 1532 1538 77 3840 514 1916 1922 78 2560 258 1276 1282 table 10-5. iic divider and hold values (sheet 3 of 5) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 305 79 3072 258 1532 1538 7a 3584 514 1788 1794 7b 4096 514 2044 2050 7c 4608 770 2300 2306 7d 5120 770 2556 2562 7e 6144 1026 3068 3074 7f 7680 1026 3836 3842 mul = 4 80 80 28 24 44 81 88 28 28 48 82 96 32 32 52 83 104 32 36 56 84 112 36 40 60 85 120 36 44 64 86 136 40 52 72 87 160 40 64 84 88 112 28 40 60 89 128 28 48 68 8a 144 36 56 76 8b 160 36 64 84 8c 176 44 72 92 8d 192 44 80 100 8e 224 52 96 116 8f 272 52 120 140 90 192 36 72 100 91 224 36 88 116 92 256 52 104 132 93 288 52 120 148 94 320 68 136 164 95 352 68 152 180 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9a 448 68 216 228 9b 512 68 248 260 9c 576 100 280 292 9d 640 100 312 324 9e 768 132 376 388 9f 960 132 472 484 a0 640 68 312 324 a1 768 68 376 388 a2 896 132 440 452 a3 1024 132 504 516 a4 1152 196 568 580 table 10-5. iic divider and hold values (sheet 4 of 5) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 306 freescale semiconductor 10.3.2.3 iic control register (ibcr) read and write anytime a5 1280 196 632 644 a6 1536 260 760 772 a7 1920 260 952 964 a8 1280 132 632 644 a9 1536 132 760 772 aa 1792 260 888 900 ab 2048 260 1016 1028 ac 2304 388 1144 1156 ad 2560 388 1272 1284 ae 3072 516 1528 1540 af 3840 516 1912 1924 b0 2560 260 1272 1284 b1 3072 260 1528 1540 b2 3584 516 1784 1796 b3 4096 516 2040 2052 b4 4608 772 2296 2308 b5 5120 772 2552 2564 b6 6144 1028 3064 3076 b7 7680 1028 3832 3844 b8 5120 516 2552 2564 b9 6144 516 3064 3076 ba 7168 1028 3576 3588 bb 8192 1028 4088 4100 bc 9216 1540 4600 4612 bd 10240 1540 5112 5124 be 12288 2052 6136 6148 bf 15360 2052 7672 7684 76543210 r iben ibie ms/sl tx/rx txak 00 ibswai w rsta reset00000000 = unimplemented or reserved figure 10-6. iic bus control register (ibcr) table 10-5. iic divider and hold values (sheet 5 of 5) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 307 wait mode is entered via execution of a cpu wai instruction. in the event that the ibswai bit is set, all clocks internal to the iic will be stopped and any transmission currently in progress will halt.if the cpu were woken up by a source other than the iic module, then clocks would restart and the iic would resume table 10-6. ibcr field descriptions field description 7 iben i-bus enable ? this bit controls the software reset of the entire iic bus module. 0 the module is reset and disabled. this is the power-on reset situation. when low the interface is held in reset but registers can be accessed 1 the iic bus module is enabled.this bit must be set before any other ibcr bits have any effect if the iic bus module is enabled in t he middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bu s and starts operating whenever a su bsequent start condition is detected. master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. this would ultimately result in eit her the current bus master or the iic bus module losing arbitration, after which bus operation would return to normal. 6 ibie i-bus interrupt enable 0 interrupts from the iic bus module are disabled. note that this does not clear any currently pending interrupt condition 1 interrupts from the iic bus module are enabled. an iic bus interrupt occurs provided the ibif bit in the status register is also set. 5 ms/sl master/slave mode select bit ? upon reset, this bit is cleared. when this bit is changed from 0 to 1, a start signal is generated on the bus, and the master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operation mode changes from master to slave.a stop signal should only be generated if the ibif flag is set. ms/sl is cleared without generating a stop signal when the master loses arbitration. 0slave mode 1 master mode 4 tx/rx transmit/receive mode select bit ? this bit selects the direction of master and slave transfers. when addressed as a slave this bit should be set by software acco rding to the srw bit in the status register. in master mode this bit should be set according to the type of transf er required. therefore, for address cycles, this bit will always be high. 0 receive 1 transmit 3 txak transmit acknowledge enable ? this bit specifies the value driven onto sda during dat a acknowledge cycles for both master and slave receivers. the iic module will always acknowledge address matches, provided it is enabled, regardless of the valu e of txak. note th at values written to this bit ar e only used when the iic bus is a receiver, not a transmitter. 0 an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data 1 no acknowledge signal response is sent (i.e., acknowledge bit = 1) 2 rsta repeat start ? writing a 1 to this bit will generate a repeated start condition on the bus, provided it is the current bus master. this bit will always be read as a low. attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 generate repeat start cycle 1 reserved reserved ? bit 1 of the ibcr is reserved for future compatibility. this bit will always read 0. 0 ibswai i bus interface stop in wait mode 0 iic bus module clock operates normally 1 halt iic bus module clock generation in wait mode chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 308 freescale semiconductor from where was during the previous transmission. it is not possible for the iic to wake up the cpu when its internal clocks are stopped. if it were the case that the ibswai bit was cleared when the wai instruction was executed, the iic internal clocks and interface would remain alive, continuing th e operation which was curren tly underway. it is also possible to configure the iic such that it will wake up the cpu via an interrupt at the conclusion of the current operation. see the discussion on the ibif and ibie bits in the ibsr and ibcr, respectively. 10.3.2.4 iic status register (ibsr) this status register is read-only with exception of bit 1 (ibif) and bit 4 (ibal), which are software clearable. 76543210 r tcf iaas ibb ibal 0srw ibif rxak w reset10000000 = unimplemented or reserved figure 10-7. iic bus st atus register (ibsr) table 10-7. ibsr field descriptions field description 7 tcf data transferring bit ? while one byte of data is being transferred, th is bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. note that this bit is only valid during or immediately following a transfer to the iic module or from the iic module. 0 transfer in progress 1 transfer complete 6 iaas addressed as a slave bit ? when its own specific address (i-bus address register) is matched with the calling address, this bit is set.the cpu is interrupted provided the ibie is set.then the cpu needs to check the srw bit and set its tx/rx mode accordingly.writing to the i-bus control register clears this bit. 0 not addressed 1 addressed as a slave 5 ibb bus busy bit 0 this bit indicates the status of the bus. when a start sig nal is detected, the ibb is set. if a stop signal is detected, ibb is cleared and the bus enters idle state. 1bus is busy 4 ibal arbitration lost ? the arbitration lost bit (ibal) is set by ha rdware when the arbitration procedure is lost. arbitration is lost in the following circumstances: 1. sda sampled low when the master drives a hi gh during an address or data transmit cycle. 2. sda sampled low when the master drives a high during the ackno wledge bit of a data receive cycle. 3. a start cycle is attempted when the bus is busy. 4. a repeated start cycle is requested in slave mode. 5. a stop condition is detected w hen the master did not request it. this bit must be cleared by software, by writing a one to it. a write of 0 has no effect on this bit. 3 reserved reserved ? bit 3 of ibsr is reserved for future use. a read operation on this bit will return 0. chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 309 10.3.2.5 iic data i/o register (ibdr) in master transmit mode, when data is written to the ibdr a data transfer is in itiated. the most significant bit is sent first. in master receiv e mode, reading this register initia tes next byte data receiving. in slave mode, the same functions are availabl e after an address match has occurred.note that the tx/rx bit in the ibcr must correctly reflect the desire d direction of transfer in master and slave mo des for the transmission to begin. for instance, if the iic is configured for master transmit but a master receive is desired, then reading the ibdr will not initiate the receive. reading the ibdr will return the last byte received while the iic is confi gured in either master receive or slave receive modes. the ibdr does not reflect every byte that is tr ansmitted on the iic bus, nor can software verify that a byte has been writte n to the ibdr correctly by reading it back. in master transmit mode, the first byte of data written to ibdr follow ing assertion of ms/sl is used for the address transfer and should com .prise of the calling addr ess (in position d7:d1) concatenated with the required r/w bit (in position d0). 2 srw slave read/write ? when iaas is set this bit indicates the valu e of the r/w command bi t of the calling address sent from the master this bit is only valid when the i-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. checking this bit, the cpu can select slave transmit/r eceive mode according to the command of the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave 1 ibif i-bus interrupt ? the ibif bit is set when one of the following conditions occurs: ? arbitration lost (ibal bit set) ? byte transfer complete (tcf bit set) ? addressed as slave (iaas bit set) it will cause a processor interrupt reques t if the ibie bit is set. this bit must be cleared by software, writing a one to it. a write of 0 has no effect on this bit. 0 rxak received acknowledge ? the value of sda during the acknowledge bit of a bus cycle. if the received acknowledge bit (rxak) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. if rxak is high, it mean s no acknowledge signal is detected at the 9th clock. 0 acknowledge received 1 no acknowledge received 76543210 r d7 d6 d5 d4 d3 d2 d1 d0 w reset00000000 figure 10-8. iic bus data i/o register (ibdr) table 10-7. ibsr field descriptions (continued) field description chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 310 freescale semiconductor 10.4 functional description this section provides a complete f unctional description of the iicv2. 10.4.1 i-bus protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open dr ain or open collector outputs. logi c and function is exercised on both lines with external pull-up resistors. the va lue of these resistors is system dependent. normally, a standard communication is composed of four parts: start signal, slave addr ess transmission, data transfer and stop signal. they are described briefly in the following sect ions and illustrated in figure 10-9 . figure 10-9. iic-bus transmission signals 10.4.1.1 start signal when the bus is free, i.e. no master device is enga ging the bus (both scl and sda lines are at logical high), a master may initiate communicati on by sending a start signal.as shown in figure 10-9 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transf er (each data transfer may contain several bytes of da ta) and brings all slaves out of their idle states. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 311 figure 10-10. start and stop conditions 10.4.1.2 slave address transmission the first byte of data transfer im mediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. only the slave with a calling address that matche s the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pul ling the sda low at the 9th clock (see figure 10-9 ). no two slaves in the system may have the same address. if the iic bus is master, it must not transmit an address that is equal to its own slave address. the iic bus cannot be master and slave at the same time.however, if arbitration is lost during an address cycle the iic bus will revert to slave mode and operate correctly even if it is being addressed by another master. 10.4.1.3 data transfer as soon as successful slave a ddressing is achieved, the data tran sfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master all transfers that come after an addres s cycle are referred to as data transf ers, even if they carry sub-address information for the slave device. each data byte is 8 bits long. data may be changed only while scl is lo w and must be held stable while scl is high as shown in figure 10-9 . there is one clock pulse on scl for each data bit, the msb being transferred first. each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the sda low at the ninth clock. so one complete data byte transfer needs nine clock pulses. if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop signal to abort the da ta transfer or a start signal (repeated start) to commence a new calling. sda scl start condition stop condition chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 312 freescale semiconductor if the master receiver doe s not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the sda line for the master to generate stop or start signal. 10.4.1.4 stop signal the master can terminate the comm unication by generating a stop signa l to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-hi gh transition of sda while scl at logical 1 (see figure 10-9 ). the master can generate a stop ev en if the slave has generated an acknowledge at which point the slave must release the bus. 10.4.1.5 repeated start signal as shown in figure 10-9 , a repeated start signal is a start si gnal generated without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 10.4.1.6 arbitration procedure the inter-ic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock sync hronization procedur e determines the bus clock, for which the low period is equal to the longest clock low pe riod and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while a nother master transmits logic 0. the losing masters immediately switch over to slave receive mode and stop driving sda output. in this case the transition from master to slave m ode does not generate a st op condition. meanwhile, a status bit is set by hardware to indicate loss of arbitration. 10.4.1.7 clock synchronization because wire-and logic is perfor med on scl line, a high-to-low tran sition on scl line affects all the devices connected on the bus. the devices start counting their low period and as soon as a device's clock has gone low, it holds the scl line low until the cl ock high state is reached.however, the change of low to high in this device clock may not change the state of the scl line if another device clock is within its low period. therefore, synchronized clock scl is he ld low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 10-11 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the de vice clocks and the state of the scl line and all the devices start counting their high peri ods.the first device to complete it s high period pulls the scl line low again. chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 313 figure 10-11. iic-bus clock synchronization 10.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transf er. slave devices may hold the scl low after completion of one byte transfer (9 bits ). in such case, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 10.4.1.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive sc l low for the required period and then release it.if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 10.4.2 operation in run mode this is the basic mode of operation. 10.4.3 operation in wait mode iic operation in wait mode can be configured. depending on the state of internal bits, the iic can operate normally when the cpu is in wait mo de or the iic clock ge neration can be turned off and the iic module enters a power conservation state dur ing wait mode. in the later case, any transmission or reception in progress stops at wait mode entry. 10.4.4 operation in stop mode the iic is inactive in stop mode for reduced power consumption. the stop instruction does not affect iic register states. scl1 scl2 scl internal counter reset wait start counting high period chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 314 freescale semiconductor 10.5 resets the reset state of each i ndividual bit is listed in section 10.3, ?memory map and register definition ,? which details the register s and their bit-fields. 10.6 interrupts iicv2 uses only one interrupt vector. table 10-8. interrupt summary internally there are three types of interrupts in iic. th e interrupt service routine can determine the interrupt type by reading the status register. iic interrupt can be generated on 1. arbitration lost condition (ibal bit set) 2. byte transfer condition (tcf bit set) 3. address detect condition (iaas bit set) the iic interrupt is enabled by the ibie bit in the iic control register. it must be cleared by writing 0 to the ibf bit in the interrupt service routine. 10.7 initialization/application information 10.7.1 iic programming examples 10.7.1.1 initialization sequence reset will put the iic bus control regi ster to its default status . before the interface can be used to transfer serial data, an initializ ation procedure must be carried out, as follows: 1. update the frequency divider re gister (ibfd) and select the re quired division ratio to obtain scl frequency from system clock. 2. update the iic bus address register (ibad) to define its slave address. 3. set the iben bit of the iic bus control register (ibcr) to en able the iic interface system. 4. modify the bits of the iic bus control register (i bcr) to select master/slave mode, transmit/receive mode and interrupt enable or not. interrupt offset vector prio rity source description iic interrupt ? ? ? ibal, tcf, iaas bits in ibsr register when either of ibal, tcf or iaas bits is set may cause an interrupt based on arbitration lost, transfer complete or address detect conditions chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 315 10.7.1.2 generation of start after completion of the initialization procedure, seri al data can be transmitte d by selecting the 'master transmitter' mode. if the device is connected to a mult i-master bus system, the st ate of the iic bus busy bit (ibb) must be tested to check whether the serial bus is free. if the bus is free (ibb=0), the start condition and the fi rst byte (the slave address) can be sent. the data written to the data register comprise s the slave calling address and the ls b set to indicate the direction of transfer required from the slave. the bus free time (i.e., the time between a stop condition and the fo llowing start condition) is built into the hardware that generates the start cycle. depending on the relative fr equencies of the system clock and the scl period it may be necessary to wait until the iic is busy after writi ng the calling address to the ibdr before proceeding with the following instru ctions. this is illustrated in the following example. an example of a program which gene rates the start signal and transmit s the first byte of data (slave address) is shown below: 10.7.1.3 post-transfer software response transmission or reception of a byte will set the data transferring bit (tcf) to 1, which indicates one byte communication is finishe d. the iic bus interrupt bit (ibif) is set al so; an interrupt will be generated if the interrupt function is enabled during initialization by setting the ibie bit. software must clear the ibif bit in the interrupt routine first. the tcf bit will be cleared by reading from the iic bus data i/o register (ibdr) in receive mode or writ ing to ibdr in transmit mode. software may service the iic i/o in the main program by monitoring the ibif bit if the interrupt function is disabled. note that polling should monitor the ibif bit rather than the tcf bit because their operation is different when arbitration is lost. note that when an interrupt occurs at the end of the address cycle the ma ster will always be in transmit mode, i.e. the address is transmitte d. if master receive mode is requ ired, indicated by r/w bit in ibdr, then the tx/rx bit should be toggled at this stage. during slave mode address cycles (iaa s=1), the srw bit in the status re gister is read to determine the direction of the subsequent transfer and the tx/rx bit is programmed accordingl y. for slave mode data cycles (iaas=0) the sr w bit is not valid, the tx/rx bit in the cont rol register should be read to determine the direction of the current transfer. the following is an example of a software response by a 'master transm itter' in the interrupt routine. chflag brset ibsr,#$20,* ;wait for ibb flag to clear txstart bset ibcr,#$30 ;set transmit and master mode;i.e. generate start condition movb calling,ibdr ;transmit the calling address, d0=r/w ibfree brclr ibsr,#$20,* ;wait for ibb flag to set isr bclr ibsr,#$02 ;clear the ibif flag brclr ibcr,#$20,slave ;branch if in slave mode brclr ibcr,#$10,receive ;branch if in receive mode brset ibsr,#$01,end ;if no ack, end of transmission transmit movb databuf,ibdr ;transmit next byte of data chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 316 freescale semiconductor 10.7.1.4 generation of stop a data transfer ends with a stop signal generated by the 'master' devi ce. a master transmitter can simply generate a stop signal afte r all the data has been transmitted. th e following is an example showing how a stop condition is generated by a master transmitter. if a master receiver wants to te rminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting th e transmit acknowledge bit (txak) before reading the 2nd last byte of data. before read ing the last byte of data, a stop signal must be generated first. the following is an example showing how a st op signal is generated by a master receiver. 10.7.1.5 generation of repeated start at the end of data transfer, if th e master continues to want to comm unicate on the bus, it can generate another start signal followed by a nother slave address w ithout first generating a stop signal. a program example is as shown. 10.7.1.6 slave mode in the slave interrupt service routin e, the module addressed as slave bit (iaas) shoul d be tested to check if a calling of its own address has just been re ceived. if iaas is set, software should set the transmit/receive mode sel ect bit (tx/rx bit of ib cr) according to the r/w co mmand bit (srw). writing to the ibcr clears the iaas automatically. note that the only time iaas is read as set is from the interrupt at the end of the address cycle wher e an address match occurred, interr upts resulting from subsequent data transfers will have iaas cleared. a data transfer may now be initia ted by writing information to ibdr, for slave transmits, or dummy re ading from ibdr, in slave receive mode. the slave will drive scl low in-between byte transfers, scl is released wh en the ibdr is accessed in the required mode. mastx tst txcnt ;get value from the transmiting counter beq end ;end if no more data brset ibsr,#$01,end ;end if no ack movb databuf,ibdr ;transmit next byte of data dec txcnt ;decrease the txcnt bra emastx ;exit end bclr ibcr,#$20 ;generate a stop condition emastx rti ;return from interrupt masr dec rxcnt ;decrease the rxcnt beq enmasr ;last byte to be read movb rxcnt,d1 ;check second last byte dec d1 ;to be read bne nxmar ;not last or second last lamar bset ibcr,#$08 ;second last, disable ack ;transmitting bra nxmar enmasr bclr ibcr,#$20 ;last one, generate ?stop? signal nxmar movb ibdr,rxbuf ;read data and store rti restart bset ibcr,#$04 ;another start (restart) movb calling,ibdr ;transmit the calling address;d0=r/w chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 317 in slave transmitter routine, the r eceived acknowledge bit (rxak) must be tested before transmitting the next byte of data. setting rxak means an 'end of data' signal from th e master receiver, after which it must be switched from transmitter mode to receiver mode by software. a dummy read then releases the scl line so that the master can generate a stop signal. 10.7.1.7 arbitration lost if several masters try to engage the bus simultan eously, only one master wins and the others lose arbitration. the devices which lost arbitration are immediat ely switched to slave receive mode by the hardware. their data output to the sda line is stopped, but scl continues to be ge nerated until the end of the byte during which arbitration was lo st. an interrupt occurs at the falli ng edge of the nint h clock of this transfer with ibal=1 and ms/sl=0. if one master at tempts to start transmission while the bus is being engaged by another master, the hardwa re will inhibit the transmission; switch the ms/sl bit from 1 to 0 without generating stop condi tion; generate an interrupt to cpu a nd set the ibal to indicate that the attempt to engage the bus is faile d. when considering these cases, the slave service routine should test the ibal first and the software should clear the ibal bit if it is set. chapter 10 inter-integrated circuit (iicv2) mc9s12e256 data sheet, rev. 1.08 318 freescale semiconductor figure 10-12. flow-chart of ty pical iic interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to ibdr switch to rx mode dummy read from ibdr generate stop signal read data from ibdr and store set txak =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear ibal iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to ibdr set rx mode dummy read from ibdr ack from receiver ? tx next byte read data from ibdr and store switch to rx mode dummy read from ibdr rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n ibif address transfer data transfer mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 319 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) 11.1 introduction the p ulse width m odulator with f ault protection (pmf) module can be configured for one, two, or three complementary pair s. for example: ? one complementary pair and four independent pwm outputs ? two complementary pair and two independent pwm outputs ? three complementary pair and zero independent pwm outputs ? zero complementary pair a nd six independent pwm outputs all pwm outputs can be generated from the same counter, or each pair can have its own counter for three independent pwm frequencies. complementary opera tion permits programmabl e dead-time insertion, distortion correction through curren t sensing by software, and separa te top and bottom output polarity control. each counter value is programmable to support a continuously variable pwm frequency. both edge- and center-aligned synchronous pulse width-control and full range modulation from 0 percent to 100 percent, are supported. the pmf is capable of controlling most motor types: ac induction motors (acim), both brushless (bldc) and br ush dc motors (bdc), switched (srm), and variable reluctance motors (vrm), and stepper motors. 11.1.1 features ? three complementary pwm signal pairs, or six independent pwm signals ? three 15-bit counters ? features of compleme ntary channel operation ? deadtime insertion ? separate top and bottom pulse width correc tion via current status inputs or software ? separate top and bottom polarity control ? edge-aligned or center-aligned pwm signals ? half-cycle reload capability ? integral reload rates from 1 to 16 ? individual software-controlled pwm output ? programmable fault protection ? polarity control chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 320 freescale semiconductor 11.1.2 modes of operation care must be exercised when using this module in the modes listed in table 11-1 . pwm outputs are placed in their inactive states in stop mode, and optionally under wait and fr eeze modes. pwm outputs will be reactivated (assuming they were active to begin with) when these modes are exited. 11.1.3 block diagrams figure 11-1 provides an overview of the pmf module. the mux/swap/current sense block is ti ghtly integrated with the dead time insertion block. this detail is shown in figure 11-2 . note it is possible to have both channels of a complementary pair to be high. for example, if the topnega (negative polarity for pwm0), botnega (negative polarity for pwm1), mask0, and mask1 bits are set, both the pwm complementary outputs of generator a will be high. see section 11.3.2.2, ?pmf configur e 1 register (pmfcfg1)? for the description of topneg and botneg bits, and section 11.3.2.3, ?pmf configure 2 register (pmfcfg2)? for the description of the msk0 and msk1 bits. table 11-1. modes when pwm operation is restricted mode description stop pwm outputs are disabled wait pwm outputs are disabled as a function of the pmfwai bit. freeze pwm outputs are disabled as a function of the pmffrz bit. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 321 figure 11-1. pmf block diagram pmfdtm register registers pmfmod pwmrie pwmen ldok edge outctl0 out0 prescaler pwm0 pin pwm1 pin pwm2 pin pwm3 pin pwm4 pin pwm5 pin pwm prsc0 interrupt control fault bus registers pmfval0-5 pmfcnt registers clock generators mux, swap & current sense out2 out4 protection fault3 pin fault0 pin fault1 pin fault2 pin registers pmdismap polarity control fault pin filters fflag0 pwmrf reload a interrupt request fault0 interrupt request fault1 interrupt request fault2 interrupt request fault3 interrupt request isens1 isens0 fint0 fint1 fint2 fint3 fflag0 fflag1 fflag2 fflag3 fmode0 fmode1 fmode2 fmode3 register pmffpin fflag2 fflag1 fflag3 ldfq2 ldfq3 prsc1 outctl2 outctl4 outctl1 out1 out3 out5 outctl3 outctl5 ldfq1 ldfq0 half pwmrf indep topneg botneg top/bottom generation ipol dt 0?5 6 is0 is1 is2 pin pin pin deadtime insertion multiple registers or bits for timebase a, b, or c a,b,c mtg reload b interrupt request reload a interrupt request reload c interrupt request qsmp0 qsmp2 qsmp1 qsmp3 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 322 freescale semiconductor figure 11-2. detail of mux, swap, and deadtime functions 11.2 external signal description the pulse width modulator has external pins named pwm0?5, fault0?3, and is0 ?is2 . 11.2.1 pwm0?pwm5 pins pwm0?pwm5 are the output pins of the six pwm channels. 11.2.2 fault0?fault3 pins fault0?fault3 are input pins for disabling selected pwm outputs. 11.2.3 is0 ?is2 pins is0 ?is2 are current status pins for top/bottom pulse wi dth correction in complementary channel operation while deadtime is asserted. pwm source selection is based on a number of factors: ? state of current sense pins ? ipol bit ? outctl bit ? center vs edge aligned pwm generator 0 pwm generator swapa out0 out1 1 1 generate complement & insert deadtime 1 1 indepa fault & polarity control pa d 0 pa d 1 msk0 msk1 outctl1 outctl0 1 ipola or isens0 or outctl0 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 323 11.3 memory map and registers 11.3.1 module memory map address name bit 7 6 5 4 3 2 1 bit 0 0x0000 pmfcfg0 r wp mtg edgec edgeb edgea indepc indepb indepa w 0x0001 pmfcfg1 r enha 0 botnegc topnegc botnegb topnegb botnega topnega w 0x0002 pmfcfg2 r0 0 msk5 msk4 msk3 msk2 msk1 msk0 w 0x0003 pmfcfg3 r pmfwai pmffrz 0 vlmode swapc swapb swapa w 0x0004 pmffctl r fmode3 fie3 fmode2 fie2 fmode1 fie1 fmode0 fie0 w 0x0005 pmffpin r0 fpine3 0 fpine2 0 fpine1 0 fpine0 w 0x0006 pmffsta r0 fflag3 0 fflag2 0 fflag1 0 fflag0 w 0x0007 pmfqsmp r qsmp3 qsmp2 qsmp1 qsmp0 w 0x0008 pmfdmpa r dmp13 dmp12 dmp11 dmp10 dmp03 dmp02 dmp01 dmp00 w 0x0009 pmfdmpb r dmp33 dmp32 dmp31 dmp30 dmp23 dmp22 dmp21 dmp20 w 0x000a pmfdmpc r dmp53 dmp52 dmp51 dmp50 dmp43 dmp42 dmp41 dmp40 w 0x000b reserved r w 0x000c pmfoutc r0 0 outctl5 outctl4 outctl3 outctl2 outctl1 outctl0 w 0x000d pmfoutb r0 0 out5 out4 out3 out2 out1 out0 w 0x000e pmfdtms r 0 0 dt5 dt4 dt3 dt2 dt1 dt0 w 0x000f pmfcctl r0 0 isens 0 ipolc ipolb ipola w 0x0010 pmfval0 r pmfval0 w 0x0011 pmfval0 r pmfval0 w = unimplemented or reserved figure 11-3. pmf15b6c register summary (sheet 1 of 3) chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 324 freescale semiconductor 0x0012 pmfval1 r pmfval1 w 0x0013 pmfval1 r pmfval1 w 0x0014 pmfval2 r pmfval2 w 0x0015 pmfval2 r pmfval2 w 0x0016 pmfval3 r pmfval3 w 0x0017 pmfval3 r pmfval3 w 0x0018 pmfval4 r pmfval4 w 0x0019 pmfval4 r pmfval4 w 0x001a pmfval5 r pmfval5 w 0x001b pmfval5 r pmfval5 w 0x001c 0x001f reserved r w 0x0020 pmfenca r pwmena 00000 ldoka pwmriea w 0x0021 pmffqca r ldfqa halfa prsca pwmrfa w 0x0022 pmfcnta r 0 pmfcnta w 0x0023 pmfcnta r pmfcnta w 0x0024 pmfmoda r0 pmfmoda w 0x0025 pmfmoda r pmfmoda w 0x0026 pmfdtma r0 0 0 0 pmfdtma w 0x0027 pmfdtma r pmfdtma w address name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 11-3. pmf15b6c register summary (sheet 2 of 3) chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 325 0x0028 pmfencb r pwmenb 00000 ldokb pwmrieb w 0x0029 pmffqcb r ldfqb halfb prscb pwmrfb w 0x002a pmfcntb r 0 pmfcntb w 0x002b pmfcntb r pmfcntb w 0x002c pmfmodb r0 pmfmodb w 0x002d pmfmodb r pmfmodb w 0x002e pmfdtmb r0 0 0 0 pmfdtmb w 0x002f pmfdtmb r pmfdtmb w 0x0030 pmfencc r pwmenc 00000 ldokc pwmriec w 0x0031 pmffqcc r ldfqc halfc prscc pwmrfc w 0x0032 pmfcntc r 0 pmfcntc w 0x0033 pmfcntc r pmfcntc w 0x0034 pmfmodc r0 pmfmodc w 0x0035 pmfmodc r pmfmodc w 0x0036 pmfdtmc r0 0 0 0 pmfdtmc w 0x0037 pmfdtmc r pmfdtmc w 0x0038 0x003f reserved r w address name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 11-3. pmf15b6c register summary (sheet 3 of 3) chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 326 freescale semiconductor 11.3.2 register descriptions the address of a register is the sum of a base address and an address offs et. the base addres s is defined at the chip level and the address offset is defined at the module level. 11.3.2.1 pmf configure 0 register (pmfcfg0) read anytime. see bit description for write conditions. module base + 0x0000 76543210 r wp mtg edgec edgeb edgea indepc indepb indepa w reset00000000 figure 11-4. pmf configure 0 register (pmfcfg0) table 11-2. pmfcfg0 field descriptions field description 7 wp write protect ? this bit enables write protection to be used for all write-protectable registers. while clear, wp allows write-protected registers to be written. when set, wp prev ents any further writes to write-protected registers. once set, wp can be cleared only by reset. 0 write-protectable registers may be written. 1 write-protectable registers are write-protected. 6 mtg multiple timebase generators ? this bit determines the number of timebase counters used. once set, mtg can be cleared only by reset. if mtg is set, pwm generators b and c and registers $x x28?$xx37 are available. the three generators have their own variable frequencies and are not synchronized. if mtg is cleared, pmf registers from $xx28?$xx37 can not be written and read zeroes, and bits edgec and edgeb are ignored. pair a, pair b and pair c pwms are synchronized to pwm generator a and use registers from $xx20?$xx27. 0 single timebase generator. 1 multiple timebase generators. 5 edgec edge-aligned or center-aligned pwm for pair c ? this bit determines whether pwm4 and pwm5 channels will use edge-aligned or center-aligned waveforms. this bit ha s no effect if mtg bit is cleared. this bit cannot be modified after the wp bit is set. 0 pwm4 and pwm5 are center-aligned pwms 1 pwm4 and pwm5 are edge-aligned pwms 4 edgeb edge-aligned or center-aligned pwm for pair b ? this bit determines whether pwm2 and pwm3 channels will use edge-aligned or center-aligned waveforms. this bit ha s no effect if mtg bit is cleared. this bit cannot be modified after the wp bit is set. 0 pwm2 and pwm3 are center-aligned pwms 1 pwm2 and pwm3 are edge-aligned pwms chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 327 3 edgea edge-aligned or center-aligned pwm for pair a ? this bit determines whether pwm0 and pwm1 channels will use edge-aligned or center-aligned waveforms. it determines waveforms for pair b and pair c if the mtg bit is cleared. this bit cannot be m odified after the wp bit is set. 0 pwm0 and pwm1 are center-aligned pwms 1 pwm0 and pwm1 are edge-aligned pwms 2 indepc independent or complimentary operation for pair c ? this bit determines if the pwm channels 4 and 5 will be independent pwms or complementary pwms. this bit cannot be modified after the wp bit is set. 0 pwm4 and pwm5 are complementary pwm pair 1 pwm4 and pwm5 are independent pwms 1 indepb independent or complimentary operation for pair b ? this bit determines if the pwm channels 2 and 3 will be independent pwms or complementary pwms. this bit cannot be modified after the wp bit is set. 0 pwm2 and pwm3 are complementary pwm pair 1 pwm2 and pwm3 are independent pwms 0 indepa independent or complimentary operation for pair a ? this bit determines if the pwm channels 0 and 1 will be independent pwms or complementary pwms. this bit cannot be modified after the wp bit is set. 0 pwm0 and pwm1 are complementary pwm pair 1 pwm0 and pwm1 are independent pwms table 11-2. pmfcfg0 field descriptions (continued) field description chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 328 freescale semiconductor 11.3.2.2 pmf configure 1 register (pmfcfg1) read anytime. this register cannot be modified after the wp bit is set. a normal pwm output or positive pol arity means that the pwm channel outputs high when the counter value is smaller than or equal to the pulse width va lue and outputs low otherwise. an inverted output or negative polarity means that the pw m channel outputs low when the counter value is smaller than or equal to the pulse width value and outputs high otherwise. module base + 0x0001 76543210 r enha 0 botnegc topnegc botnegb topnegb botnega topnega w reset00000000 = unimplemented or reserved figure 11-5. pmf configure 1 register (pmfcfg1) table 11-3. pmfcfg1 field descriptions field description 7 enha enable hardware acceleration ? this bit enables writing to the vlmode[1:0], swapc, swapb, and swapa bits in the pmfcfg3 register. this bit cannot be modified after the wp bit is set. 0 disable writing to vlmode[1:0 ], swapc, swapb, and swapa bits 1 enable writing to vlmode[1:0 ], swapc, swapb, and swapa bits 5 botnegc pair c bottom-side pwm polarity ? this bit determines the polarity for pair c bottom-side pwm (pwm5). this bit cannot be modified after the wp bit is set. 0 positive pwm5 polarity 1 negative pwm5 polarity 4 topnegc pair c top-side pwm polarity ? this bit determines the polarity for pair c top-side pwm (pwm4). this bit cannot be modified after the wp bit is set. 0 positive pwm4 polarity 1 negative pwm4 polarity 3 botnegb pair b bottom-side pwm polarity ? this bit determines the polarity for pair b bottom-side pwm (pwm3). this bit cannot be modified after the wp bit is set. 0 positive pwm3 polarity 1 negative pwm3 polarity 2 topnegb pair b top-side pwm polarity ? this bit determines the polarity for pair b top-side pwm (pwm2). this bit cannot be modified after the wp bit is set. 0 positive pwm2 polarity 1 negative pwm2 polarity 1 botnega pair a bottom-side pwm polarity ? this bit determines the polarity for pair a bottom-side pwm (pwm1). this bit cannot be modified after the wp bit is set. 0 positive pwm1 polarity 1 negative pwm1 polarity 0 topnega pair a top-side pwm polarity ? this bit determines the polarity for pair a top-side pwm (pwm0). this bit cannot be modified after the wp bit is set. 0 positive pwm0 polarity 1 negative pwm0 polarity chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 329 11.3.2.3 pmf configure 2 register (pmfcfg2) read and write anytime. module base + 0x0002 76543210 r0 0 msk5 msk4 msk3 msk2 msk1 msk0 w reset00000000 = unimplemented or reserved figure 11-6. pmf configure 2 register (pmfcfg2) table 11-4. pmfcfg2 field descriptions field description 5?0 msk[5:0] mask pwmx ? where x is 0, 1, 2, 3, 4, and 5. 0 pwmx is unmasked. 1 pwmx is masked and the channel is set to a value of 0 percent duty cycle. warning when using the topneg/botneg bits and the mskx bits at the same time, when in complementary mode, it is possible to have both pmf channel outputs of a channel pair set to one. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 330 freescale semiconductor 11.3.2.4 pmf configure 3 register (pmfcfg3) read and write anytime. module base + 0x0003 76543210 r pmfwai pmffrz 0 vlmode swapc swapb swapa w reset00000000 = unimplemented or reserved figure 11-7. pmf configure 3 register (pmfcfg3) table 11-5. pmfcfg3 field descriptions field description 7 pmfwai pmf stops while in wait mode ? when set to zero, the pwm generators will continue to run while the chip is in wait mode. in this mode, the peripheral clock continues to run but the cpu clock does not. if the device enters wait mode and this bit is one, then the pwm outputs will be switched to their inactive state until wait mode is exited. at that point the pwm pins will resume operation as programmed in the pwm registers. 0 pmf continues to run in wait mode. 1 pmf is disabled in wait mode. 6 pmffrz pmf stops while in freeze mode ? when set to zero, the pwm generators will continue to run while the chip is in freeze mode. if the device enters freeze mode and this bit is one, then the pwm outputs will be switched to their inactive state until freeze mode is exited. at that point the pwm pins will resume operation as programmed in the pwm registers. 0 pmf continues to run in freeze mode. 1 pmf is disabled in freeze mode. 4?3 vlmode value register load mode ? this field determines the way the value registers are being loaded. this field can only be written if enha is set. 00 = each value register is accessed independently 01 = writing to value register zero also writes to value registers one to five 10 = writing to value register zero also writes to value registers one to three 11 = reserved (defaults to independent access) 2 swapc swap pair c ? this bit can only be written if enha is set. 0no swap. 1 pwm4 and pwm5 are swapped only in complementary mode. 1 swapb swap pair b ? this bit can only be written if enha is set. 0no swap. 1 pwm2 and pwm3 are swapped only in complementary mode. 0 swapc swap pair a ?this bit can only be written if enha is set. 0no swap. 1 pwm0 and pwm1 are swapped only in complementary mode. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 331 11.3.2.5 pmf fault cont rol register (pmffctl) read and write anytime. 11.3.2.6 pmf fault pin enable register (pmffpin) read anytime. this register cannot be modified after the wp bit is set. module base + 0x0004 76543210 r fmode3 fie3 fmode2 fie2 fmode1 fie1 fmode0 fie0 w reset00000000 figure 11-8. pmf fault cont rol register (pmffctl)) table 11-6. pmffctl field descriptions field description 7, 5, 3, 1 fmode[3:0] fault x pin clearing mod e ? this bit selects automatic or manual clearing of faultx pin faults. see section 11.4.8.2, ?automatic fault clearing? and section 11.4.8.3, ?manual fault clearing? for more details. 0 manual fault clearing of faultx pin faults. 1 automatic fault clearing of faultx pin faults. where x is 0, 1, 2, and 3. 6, 4, 2, 0 fie[3:0] fault x pin interrupt enable ? this bit enables cpu interrupt requests to be generated by the faultx pin. the fault protection circuit is independent of the fiex bit and is active when fpinex is set. if a fault is detected, the pwm pins are disabled according to the pmf disable mapping registers. 0 fault x cpu interrupt requests disabled. 1 fault x cpu interrupt requests enabled. where x is 0, 1, 2 and 3. module base + 0x0005 76543210 r0 fpine3 0 fpine2 0 fpine1 0 fpine0 w reset00000000 = unimplemented or reserved figure 11-9. pmf fault pin enable register (pmffpin) table 11-7. pmffpin field descriptions field description 6, 4, 2, 0 fpine[2:0] fault x pin enable ? where x is 0, 1, 2 and 3. 0 faultx pin is disabled for fault protection. 1 faultx pin is enabled for fault protection. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 332 freescale semiconductor 11.3.2.7 pmf fault status register (pmffsta) read and write anytime. 11.3.2.8 pmf fault qualifying samples register (pmfqsmp) read anytime. this register cannot be modified after the wp bit is set. module base + 0x0006 76543210 r0 fflag3 0 fflag2 0 fflag1 0 fflag0 w reset00000000 = unimplemented or reserved figure 11-10. pmf fault fl ag register (pmffsta) table 11-8. pmffsta field descriptions field description 6, 4, 2, 0 fflag[3:0] fault x pin flag ? this flag is set after the required number of samples have been detected after a rising edge on the faultx pin. writing a logic one to fflagx clears it . writing a logic zero has no effect. the fault protection is enabled when fpinex is set even when the pwms are not enabled; therefore, a fault will be latched in, requiring to be cleared in order to prevent an interrupt. 0 no fault on the faultx pin. 1 fault on the faultx pin. note: clearing fflagx satisfies pending fflagx cpu interrupt requests. where x is 0, 1, 2 and 3. module base + 0x0007 76543210 r qsmp3 qsmp2 qsmp1 qsmp0 w reset00000000 figure 11-11. pmf fault qualifying samples register (pmfqsmp) table 11-9. pmfqsmp field descriptions field description 7?0 qsmp[3:0] fault x qualifying samples ? this field indicates the number of co nsecutive samples taken at the faultx pin to determine if a fault is detected. t he first sample is qualifie d after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles. see table 11-10 . where x is 0, 1, 2 and 3. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 333 11.3.2.9 pmf disable mapping registers read anytime. these registers cannot be modified after the wp bit is set. table 11-10. qualifying samples qsmpx number of samples 00 1 sample 1 1 there is an asynchronous path from fault pin to disable pwms immediately but the fault is qualified in two bus cycles. 01 5 samples 10 10 samples 11 15 samples module base + 0x0008 76543210 r dmp13 dmp12 dmp11 dmp10 dmp03 dmp02 dmp01 dmp00 w reset00000000 figure 11-12. pmf disable mapping a register (pmfdmpa) module base + 0x0009 76543210 r dmp33 dmp32 dmp31 dmp30 dmp23 dmp22 dmp21 dmp20 w reset00000000 figure 11-13. pmf disable ma pping b register (pmfdmpb) module base + 0x000a 76543210 r dmp53 dmp52 dmp51 dmp50 dmp43 dmp42 dmp41 dmp40 w reset00000000 figure 11-14. pmf disable ma pping c register (pmfdmpc) table 11-11. pmfdmpa, pmfdmpb, and pmfdmpc field descriptions field description 7?0 dmp[00:53] pmf disable mapping bits ? the fault decoder disables pwm pins selected by the fault logic and the disable mapping registers. see figure 11-15 . each bank of four bits in the disable mapping registers control the mapping of a single pwm pin. refer to table 11-12 . chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 334 freescale semiconductor figure 11-15. fault decoder 11.3.2.10 pmf output control register (pmfoutc) read and write anytime. table 11-12. fault mapping pwm pin controlling register bits pwm0 dmp03 ? dmp00 pwm1 dmp13 ? dmp10 pwm2 dmp23 ? dmp20 pwm3 dmp33 ? dmp30 pwm4 dmp43 ? dmp40 pwm5 dmp53 ? dmp50 module base + 0x000c 76543210 r0 0 outctl5 outctl4 outctl3 outctl2 outctl1 outctl0 w reset00000000 = unimplemented or reserved figure 11-16. pmf output control register (pmfoutc) table 11-13. pmfoutc field descriptions field description 5?0 outctl[5:0] pmf output control bits ? these bits enable software control of their corresponding pwm pin. when outctlx is set, the outx bit activates and deactivates the pwmx output. when operating the pwm in complementary mode, these bits must be switched in pairs for proper operation. that is outctl0 and outctl1 must have the same value; outctl2 and outctl3 must have the same value; and outctl4 and outctl5 must have the same value. 0 software control disabled 1 software control enabled where x is 0, 1, 2, 3, 4 and 5 dmpx0 dmpx1 dmpx2 dmpx3 disable pwm pin x fault0 fault1 fault2 fault3 where x is 0, 1, 2, 3, 4, 5 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 335 11.3.2.11 pmf output control bit register (pmfoutb) read and write anytime. table 11-15. software output control module base + 0x000d 76543210 r0 0 out5 out4 out3 out2 out1 out0 w reset00000000 = unimplemented or reserved figure 11-17. pmf output control bit register (pmfoutb) table 11-14. pmfoutb field descriptions field description 5?0 out[5:0] pmf output control bits ? when the corresponding outctl bit is set, these bits control the pwm pins, illustrated in table 11-15 . outx bit complementary channel oper ation independent channel operation out0 1?pwm0 is active 0?pwm0 is inactive 1?pwm0 is active 0?pwm0 is inactive out1 1?pwm1 is complement of pwm0 0?pwm1 is inactive 1?pwm1 is active 0?pwm1 is inactive out2 1?pwm2 is active 0?pwm2 is inactive 1?pwm2 is active 0?pwm2 is inactive out3 1?pwm3 is complement of pwm2 0?pwm3 is inactive 1?pwm3 is active 0?pwm3 is inactive out4 1?pwm4 is active 0?pwm4 is inactive 1?pwm4 is active 0?pwm4 is inactive out5 1?pwm5 is complement of pwm4 0?pwm5 is inactive 1?pwm5 is active 0?pwm5 is inactive chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 336 freescale semiconductor 11.3.2.12 pmf deadtime sample register (pmfdtms) read anytime and writ es have no effect. 11.3.2.13 pmf correction control register (pmfcctl) read and write anytime. module base + 0x000e 76543210 r 0 0 dt5 dt4 dt3 dt2 dt1 dt0 w reset00000000 = unimplemented or reserved figure 11-18. pmf deadtime sample register (pmfdtms)) table 11-16. pmfdtms field descriptions field description 5?0 dt[5:0] pmf deadtime sample bits ? the dtx bits are grouped in pairs, dt0 and dt1, dt2 and dt3, dt4, and dt5. each pair reflects the corresponding isx pin value as sampled at the end of deadtime. module base + 0x000f 76543210 r0 0 isens 0 ipolc ipolb ipola w reset00000000 = unimplemented or reserved figure 11-19. pmf correction control register (pmfcctl) table 11-17. pmfcctl field descriptions field description 5?4 isens current status sensing method ? this field selects the top/bottom correction scheme, illustrated in ta b l e 1 1 - 1 8 . note: assume the user will provide current sensing circuitr y causing the voltage at the corresponding input pin to be low for positive current and high for negative current. in addition, it assumes the top pwms are pwm 0, 2, and 4 while the bottom pwms are pwm 1, 3, and 5. note: the isens bits are not buffered. changing the current status sensing method ca n affect the present pwm cycle. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 337 table 11-18. correction method selection 2 ipolc current polarity ? this buffered bit selects the pmf value register for the pwm4 and pwm5 pins in top/bottom software correction in complementary mode. 0 pmf value 4 register in next pwm cycle. 1 pmf value 5 register in next pwm cycle. note: the ipolx bits take effect at the beginning of the ne xt load cycle, regardless of the state of the load okay bit, ldok. select top/bottom software correction by writing 01 to the current select bits, isens[1:0], in the pwm control register. reading the ipolx bits read t he buffered value and not necessarily the value currently in effect. 1 ipolb current polarity ? this buffered bit selects the pmf value register for the pwm2 and pwm3 pins in top/bottom software correction in complementary mode. 0 pmf value 2 register in next pwm cycle. 1 pmf value 3 register in next pwm cycle. note: the ipolx bits take effect at the beginning of the ne xt load cycle, regardless of the state of the load okay bit, ldok. select top/bottom software correction by writing 01 to the current select bits, isens[1:0], in the pwm control register. reading the ipolx bits read t he buffered value and not necessarily the value currently in effect. 0 ipola current polarity ? this buffered bit selects the pmf value register for the pwm0 and pwm1 pins in top/bottom software correction in complementary mode. 0 pmf value 0 register in next pwm cycle. 1 pmf value 1 register in next pwm cycle. note: the ipolx bits take effect at the beginning of the ne xt load cycle, regardless of the state of the load okay bit, ldok. select top/bottom software correction by writing 01 to the current select bits, isens[1:0], in the pwm control register. reading the ipolx bits read t he buffered value and not necessarily the value currently in effect. isens correction method 00 no correction 1 1 the current status pins can be used as general purpose input/output ports. 01 manual correction 10 current status sample correction on pins is0 , is1 , and is2 during deadtime 2 2 the polarity of the isx pin is latched when both the top and bottom pwms are off. at the 0% and 100% duty cycle boundaries, there is no deadtime, so no new current value is sensed. 11 current status sample on pins is0 , is1 , and is2 3 at the half cycle in center-aligned operation at the end of the cycle in edge-aligned operation 3 current is sensed even with 0% or 100% duty cycle. table 11-17. pmfcctl field descriptions (continued) field description chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 338 freescale semiconductor 11.3.2.14 pmf value 0 register (pmfval0) read and write anytime. 11.3.2.15 pmf value 1 register (pmfval1) read and write anytime. module base + 0x0010 1514131211109876543210 r pmfval0 w reset000000000 0000000 figure 11-20. pmf value 0 register (pmfval0) table 11-19. pmfval0 field descriptions field description 16?0 pmfval0 pmf value 0 bits ? the 16-bit signed value in this buffered regi ster is the pulse width in pwm0 clock period. a value less than or equal to zero deactivates the pwm output for the entire pwm period. a value greater than, or equal to the modulus, activates the pwm output for the entire pwm period. see table 11-46 . the terms activate and deactivate refer to the high and low logic states of the pwm output. note: pmfval0 is buffered. the value written does not take effect until the ldok bit is set and the next pwm load cycle begins reading pmfval0 reads the value in the buffer and not necessarily the value the pwm generator is currently using. module base + 0x0012 1514131211109876543210 r pmfval1 w reset000000000 0000000 figure 11-21. pmf value 1 register (pmfval1) table 11-20. pmfval1 field descriptions field description 16?0 pmfval1 pmf value 1 bits ? the 16-bit signed value in this buffered regi ster is the pulse width in pwm1 clock period. a value less than or equal to zero deactivates the pwm output for the entire pwm period. a value greater than, or equal to the modulus, activates the pwm output for the entire pwm period. see table 11-46 . the terms activate and deactivate refer to the high and low logic states of the pwm output. note: pmfval1 is buffered. the value written does not take effect until the ldok bit is set and the next pwm load cycle begins. reading pmfval1 reads the value in the buffer and not necessa rily the value the pwm generator is currently using. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 339 11.3.2.16 pmf value 2 register (pmfval2) read and write anytime. 11.3.2.17 pmf value 3 register (pmfval3) read and write anytime. module base + 0x0014 1514131211109876543210 r pmfval2 w reset000000000 0000000 figure 11-22. pmf value 2 register (pmfval2) table 11-21. pmfval2 field descriptions field description 16?0 pmfval2 pmf value 2 bits ? the 16-bit signed value in this buffered regi ster is the pulse width in pwm2 clock period. a value less than or equal to zero deactivates the pwm output for the entire pwm period. a value greater than, or equal to the modulus, activates the pwm output for the entire pwm period. see table 11-46 . the terms activate and deactivate refer to the high and low logic states of the pwm output. note: pmfval2 is buffered. the value written does not take effect until the ldok bit is set and the next pwm load cycle begins. reading pmfval2 reads the value in the buffer and not necessa rily the value the pwm generator is currently using. module base + 0x0016 1514131211109876543210 r pmfval3 w reset000000000 0000000 figure 11-23. pmf value 3 register (pmfval3) table 11-22. pmfval3 field descriptions field description 16?0 pmfval3 pmf value 3 bits ? the 16-bit signed value in this buffered regi ster is the pulse width in pwm3 clock period. a value less than or equal to zero deactivates the pwm output for the entire pwm period. a value greater than, or equal to the modulus, activates the pwm output for the entire pwm period. see table 11-46 . the terms activate and deactivate refer to the high and low logic states of the pwm output. note: pmfval3 is buffered. the value written does not take effect until the ldok bit is set and the next pwm load cycle begins. reading pmfval3 reads the value in the buffer and not necessa rily the value the pwm generator is currently using. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 340 freescale semiconductor 11.3.2.18 pmf value 4 register (pmfval4) read and write anytime. 11.3.2.19 pmf value 5 register (pmfval5) read and write anytime. module base + 0x0018 1514131211109876543210 r pmfval4 w reset000000000 0000000 figure 11-24. pmf value 4 register (pmfval4) table 11-23. pmfval4 field descriptions field description 16?0 pmfval4 pmf value 4 bits ? the 16-bit signed value in this buffered regi ster is the pulse width in pwm4 clock period. a value less than or equal to zero deactivates the pwm output for the entire pwm period. a value greater than, or equal to the modulus, activates the pwm output for the entire pwm period. see table 11-46 . the terms activate and deactivate refer to the high and low logic states of the pwm output. note: pmfval4 is buffered. the value written does not take effect until the ldok bit is set and the next pwm load cycle begins. reading pmfval4 reads the value in the buffer and not necessa rily the value the pwm generator is currently using. module base + 0x001a 1514131211109876543210 r pmfval5 w reset000000000 0000000 figure 11-25. pmf value 5 register (pmfval5) table 11-24. pmfval5 field descriptions field description 16?0 pmfval5 pmf value 5 bits ? the 16-bit signed value in this buffered regi ster is the pulse width in pwm5 clock period. a value less than or equal to zero deactivates the pwm output for the entire pwm period. a value greater than, or equal to the modulus, activates the pwm output for the entire pwm period. see table 11-46 . the terms activate and deactivate refer to the high and low logic states of the pwm output. note: pmfval5 is buffered. the value written does not take effect until the ldok bit is set and the next pwm load cycle begins. reading pmfval5 reads the value in the buffer and not necessa rily the value the pwm generator is currently using. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 341 11.3.2.20 pmf enable control a register (pmfenca) read and write anytime. module base + 0x0020 76543210 r pwmena 00000 ldoka pwmriea w reset00000000 = unimplemented or reserved figure 11-26. pmf en able control a register (pmfenca) table 11-25. pmfenca field descriptions field description 7 pwmena pwm generator a enable ? when mtg is clear, this bit when set enables the pwm generators a, b and c and the pwm0?5 pins. when pwmena is clear, pwm generators a, b and c are disabled, and the pwm0?5 pins are in their inactive states unless the corresponding outctlx bits are set. when mtg is set, this bit when set enables the pwm generator a and the pwm0 and pwm1 pins. when pwmena is clear, the pwm generator a is disabled and pwm0 and pwm1 pins are in their inactive states unless the outctl0 and outctl1 bits are set. 0 pwm generator a and pwm0?1 (2?5 if mtg=0) pins di sabled unless the respective outctl bit is set. 1 pwm generator a and pwm0?1 (2?5 if mtg=0) pins enabled. 1 ldoka load okay a ? when mtg is clear, this bit allows loads of the prsca bits, the pmfmoda register and the pwmval0?5 registers into a set of buffers. the buffered prescaler a divisor, pwm counter modulus a value, and all pwm pulse widths take effect at the next pwm reload. when mtg is set, this bit allows loads of the prsca bi ts, the pmfmoda register and the pwmval0?1 registers into a set of buffers. the buffered prescaler divisor a, pwm counter modulus a value, pwm0?1 pulse widths take effect at the next pwm reload. set ldoka by reading it when it is logic zero and then writing a logic one to it. ldoka is automatically cleared after the new values are loaded, or can be manually clea red before a reload by writing a logic zero to it. reset clears ldoka. 0 do not load new modulus a, prescaler a, and pwm0?1 (2?5 if mtg=0) values 1 load prescaler a, modulus a, and pwm0?1 (2?5 if mtg=0) values note: do not set pwmena bit before setting the ldoka bit and do not clear the ldoka bit at the same time as setting the pwmena bit. 0 pwmriea pwm reload interrupt enable a ? this bit enables the pwmrfa flag to generate cpu interrupt requests. 0 pwmrfa cpu interrupt requests disabled 1 pwmrfa cpu interrupt requests enabled chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 342 freescale semiconductor 11.3.2.21 pmf frequency cont rol a register (pmffqca) read and write anytime. module base + 0x0021 76543210 r ldfqa halfa prsca pwmrfa w reset00000000 figure 11-27. pmf frequency control a register (pmffqca) table 11-26. pmffqca field descriptions field description 7?4 ldfqa load frequency a ? this field selects the pwm load frequency according to table 11-27 . see section 11.4.7.2, ?load frequency? for more details. note: the ldfqa field takes effect when the current load cycl e is complete, regardless of the state of the load okay bit, ldoka. reading the ldfqa field reads the buffered value and not necessarily the value currently in effect. 3 halfa half cycle reload a ? this bit enables half-cycle re loads in center-aligned pwm mo de. this bit has no effect on edge-aligned pwms. 0 half-cycle reloads disabled 1 half-cycle reloads enabled 2?1 prsca prescaler a ? this buffered field selects the pwm clock frequency illustrated in table 11-28 . note: reading the prsca field reads the buffered value and not necessarily the value currently in effect. the prsca field takes effect at the beginning of the next pwm cycle and only when the load okay bit, ldoka, is set. 0 pwmrfa pwm reload flag a ? this flag is set at the b eginning of every reload cycle re gardless of the state of the ldoka bit. clear pwmrfa by reading pmffqca with pwmrfa set and then writing a logic one to the pwmrfa bit. if another reload occurs before the cleari ng sequence is complete, writing logic one to pwmrfa has no effect. 0 no new reload cycle sinc e last pwmrfa clearing 1 new reload cycle since last pwmrfa clearing note: clearing pwmrfa satisfies pending pwmrfa cpu interrupt requests. table 11-27. pwm reload frequency a ldfqa pwm reload frequency ldfq[3:0] pwm reload frequency 0000 every pwm opportunity 1000 every 9 pwm opportunities 0001 every 2 pwm opportunities 1001 every 10 pwm opportunities 0010 every 3 pwm opportunities 1010 every 11 pwm opportunities 0011 every 4 pwm opportunities 1011 every 12 pwm opportunities 0100 every 5 pwm opportunities 1100 every 13 pwm opportunities 0101 every 6 pwm opportunities 1101 every 14 pwm opportunities 0110 every 7 pwm opportunities 1110 every 15 pwm opportunities 0111 every 8 pwm opportunities 1111 every 16 pwm opportunities chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 343 11.3.2.22 pmf counter a register (pmfcnta) read anytime and writ es have no effect. 11.3.2.23 pmf counter modulo a register (pmfmoda) read and write anytime. table 11-28. pwm prescaler a prsca pwm clock frequency 00 f bus 01 f bus /2 10 f bus /4 11 f bus /8 module base + 0x0022 1514131211109876543210 r 0 pmfcnta w reset000000000 0000000 = unimplemented or reserved figure 11-28. pmf counter a register (pmfcnta) table 11-29. pmfcnta field descriptions field description 14?0 pmfcnta pmf counter a bits ? this register displays the st ate of the 15-bit pwm a counter. module base + 0x0024 1514131211109876543210 r0 pmfmoda w reset000000000 0000000 = unimplemented or reserved figure 11-29. pmf counter modulo a register (pmfmoda) table 11-30. pmfmoda field descriptions field description 14?0 pmfmoda pmf counter modulo a bits ? the 15-bit unsigned value written to th is register is the pwm period in pwm clock periods. do not write a modulus value of zero. note: the pwm counter modulo register is buffered. the value written does not take effect until the ldoka bit is set and the next pwm load cycl e begins. reading pmfmoda reads th e value in the buffer. it is not necessarily the value the pwm g enerator a is currently using. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 344 freescale semiconductor 11.3.2.24 pmf deadtime a register (pmfdtma) read anytime. this register cannot be modified after the wp bit is set. 11.3.2.25 pmf enable control b register (pmfencb) read anytime and writ e only if mtg is set. module base + 0x0026 1514131211109876543210 r0000 pmfdtma w reset000011111 1111111 = unimplemented or reserved figure 11-30. pmf deadtime a register (pmfdtma) table 11-31. pmfdtma field descriptions field description 11?0 pmfdtma pmf deadtime a bits ? the 12-bit value written to this register is the number of pwm clock cycles in complementary channel operation. a reset sets the pwm deadtime register to a default value of 0x0fff, selecting a deadtime of 256-pwm clock cycles minus one bus clock cycle. note: deadtime is affected by changes to the prescaler value. the deadtime duration is determined as follows: dt = p pmfdtma ? 1, where dt is deadtime, p is the prescaler value, pmfdtma is the programmed value of dead time. for example: if the prescaler is programmed for a divide-by-two and the pmfdtma is set to five, then p = 2 and the deadtime value is equal to dt = 2 5 ? 1 = 9 ipbus clock cycles. a special case exists when the p = 1, then dt = pmfdtma. module base + 0x0028 76543210 r pwmenb 00000 ldokb pwmrieb w reset00000000 = unimplemented or reserved figure 11-31. pmf en able control b register (pmfencb) table 11-32. pmfencb field descriptions field description 7 pwmenb pwm generator b enable ? if mtg is clear, this bit reads zero and cannot be written. if mtg is set, this bit when set enables the pwm generator b and the pwm2 and pwm3 pins. when pwmenb is clear, pwm generator b is disabled, and the pwm2 and pwm3 pins are in their inactive states unless the outctl2 and outctl3 bits are set. 0 pwm generator b and pwm2?3 pins disabled unless the respective outctl bit is set. 1 pwm generator b and pwm2?3 pins enabled. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 345 11.3.2.26 pmf frequency cont rol b register (pmffqcb) read anytime and writ e only if mtg is set. 1 ldokb load okay b ? if mtg is clear, this bit reads zero and cannot be written. if mtg is set, this bit loads the prscb bits, the pmfm odb register and the pwmval2?3 registers into a set of buffers. the buffered prescaler divisor b, pwm counter modulus b value, pwm2?3 pulse widths take effect at the next pwm reload. set ldokb by reading it when it is logic zero and then writing a logic one to it. ldokb is automatically cleared after the new values are loaded, or can be manually clea red before a reload by writing a logic zero to it. reset clears ldokb. 0 do not load new modulus b, prescaler b, and pwm2?3 values. 1 load prescaler b, modulus b, and pwm2?3 values. note: do not set pwmenb bit before setting the ldokb bit and do not clear the ldokb bit at the same time as setting the pwmenb bit. 0 pwmrieb pwm reload interrupt enable b ? if mtg is clear, this bit reads zero and cannot be written. if mtg is set, this bit enables the pwmrfb flag to generate cpu interrupt requests. 0 pwmrfb cpu interrupt requests disabled 1 pwmrfb cpu interrupt requests enabled module base + 0x0029 76543210 r ldfqb halfb prscb pwmrfb w reset00000000 figure 11-32. pmf frequency control b register (pmffqcb) table 11-33. pmffqcb field descriptions field description 7?4 ldfqb load frequency b ? this field selects the pwm load frequency according to table 11-34 . see section 11.4.7.2, ?load frequency? for more details. note: the ldfqb field takes effect when the current load cycl e is complete, regardless of the state of the load okay bit, ldokb. reading the ldfqb field reads the buffered value and not necessarily the value currently in effect. 3 halfb half cycle reload b ? this bit enables half-cycle re loads in center-aligned pwm mo de. this bit has no effect on edge-aligned pwms. 0 half-cycle reloads disabled 1 half-cycle reloads enabled table 11-32. pmfencb field descriptions (continued) field description chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 346 freescale semiconductor 2?1 prscb prescaler b ? this buffered field selects the pwm clock frequency illustrated in ta b l e 1 1 - 3 5 . note: reading the prscb field reads the buffered value and not necessarily the value currently in effect. the prscb field takes effect at the beginning of the ne xt pwm cycle and only when the load okay bit, ldokb, is set. 0 pwmrfb pwm reload flag b ? this flag is set at the begi nning of every reload cycle rega rdless of the state of the ldokb bit. clear pwmrfb by reading pmffqcb with pwmrfb set and then writing a logic one to the pwmrfb bit. if another reload occurs before the clear ing sequence is complete, writing logic one to pwmrfb has no effect. 0 no new reload cycle sinc e last pwmrfb clearing 1 new reload cycle since last pwmrfb clearing note: clearing pwmrfb satisfies pending pwmrfb cpu interrupt requests. table 11-34. pwm reload frequency b ldfqb pwm reload frequency ldfq[3:0] pwm reload frequency 0000 every pwm opportunity 1000 every 9 pwm opportunities 0001 every 2 pwm opportunities 1001 every 10 pwm opportunities 0010 every 3 pwm opportunities 1010 every 11 pwm opportunities 0011 every 4 pwm opportunities 1011 every 12 pwm opportunities 0100 every 5 pwm opportunities 1100 every 13 pwm opportunities 0101 every 6 pwm opportunities 1101 every 14 pwm opportunities 0110 every 7 pwm opportunities 1110 every 15 pwm opportunities 0111 every 8 pwm opportunities 1111 every 16 pwm opportunities table 11-35. pwm prescaler b prscb pwm clock frequency 00 f bus 01 f bus /2 10 f bus /4 11 f bus /8 table 11-33. pmffqcb field descriptions (continued) field description chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 347 11.3.2.27 pmf counter b register (pmfcntb) read anytime and writ es have no effect. 11.3.2.28 pmf counter modulo b register (pmfmodb) read anytime and writ e only if mtg is set. module base + 0x002a 1514131211109876543210 r 0 pmfcntb w reset000000000 0000000 = unimplemented or reserved figure 11-33. pmf counter b register (pmfcntb) table 11-36. pmfcntb field descriptions field description 14?0 pmfcntb pmf counter b ? this register displays the st ate of the 15-bit pwm b counter. module base + 0x002c 1514131211109876543210 r0 pmfmodb w reset000000000 0000000 = unimplemented or reserved figure 11-34. pmf counter modulo b register (pmfmodb) table 11-37. pmfmodb field descriptions field description 14?0 pmfmodb pmf counter modulo b ? the 15-bit unsigned value written to this register is the pwm period in pwm clock periods. do not write a modulus value of zero. note: the pwm counter modulo register is buffered. the value written does not take effect until the ldokb bit is set and the next pwm load cycl e begins. reading pmfmodb reads th e value in the buffer. it is not necessarily the value the pwm g enerator b is currently using. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 348 freescale semiconductor 11.3.2.29 pmf deadtime b register (pmfdtmb) read anytime and write only if mtg is set. this register cannot be modified after the wp bit is set. 11.3.2.30 pmf enable control c register (pmfencc) read anytime and writ e only if mtg is set. module base + 0x002e 1514131211109876543210 r0000 pmfdtmb w reset000011111 1111111 = unimplemented or reserved figure 11-35. pmf deadtime b register (pmfdtmb) table 11-38. pmfdtmb field descriptions field description 11?0 pmfdtmb pmf deadtime b ? the 12-bit value wr itten to this register is the number of pwm clock cycles in complementary channel operation. a reset sets the pwm deadtime register to a default value of 0x0fff, selecting a deadtime of 256-pwm clock cycles minus one bus clock cycle. note: deadtime is affected by changes to the prescaler value. the deadtime duration is determined as follows: dt = p pmfdtmb ? 1, where dt is deadtime, p is the prescaler value, pmfdtmb is the programmed value of dead time. for example: if the prescaler is programmed for a divide-by-two and the pmfdtmb is set to five, then p = 2 and the deadtime value is equal to dt = 2 5 ? 1 = 9 ipbus clock cycles. a special case exists when the p = 1, then dt = pmfdtmb. module base + 0x0030 76543210 r pwmenc 00000 ldokc pwmriec w reset00000000 = unimplemented or reserved figure 11-36. pmf en able control c register (pmfencc) table 11-39. pmfencc field descriptions field description 7 pwmenc pwm generator c enable ? if mtg is clear, this bit reads zero and cannot be written. if mtg is set, this bit when set enables the pwm generator c and the pwm4 and pwm5 pins. when pwmenc is clear, pwm generator c is disabled, and the pwm4 an d pwm5 pins are in their inactive states unless the outctl4 and outctl5 bits are set. 0 pwm generator c and pwm4?5 pins disabled unless the respective outctl bit is set. 1 pwm generator c and pwm4?5 pins enabled. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 349 11.3.2.31 pmf frequency cont rol c register (pmffqcc) read anytime and writ e only if mtg is set. 1 ldokc load okay c ? if mtg is clear, this bit reads zero and can not be written. if mtg is set, this bit loads the pr scc bits, the pmfmodc register and the pwmval4?5 registers into a set of buffers. the buffered prescaler divisor c, pwm counter modulus c value, pwm4?5 pulse widths take effect at the next pwm reload. set ldokc by reading it when it is logic zero and then wr iting a logic one to it. ldokc is automatically cleared after the new values are loaded, or can be manually clea red before a reload by writing a logic zero to it. reset clears ldokc. 0 do not load new modulus c, prescaler c, and pwm4?5 values. 1 load prescaler c, modulus c, and pwm4?5 values. note: do not set pwmenc bit before setting the ldokc bit and do not clear the ldokc bit at the same time as setting the pwmenc bit. 0 pwmriec pwm reload interrupt enable c ? if mtg is clear, this bit reads zero and cannot be written. if mtg is set, this bit enables the pwmrfc flag to generate cpu interrupt requests. 0 pwmrfc cpu interrupt requests disabled 1 pwmrfc cpu interrupt requests enabled module base + 0x0031 76543210 r ldfqc halfc prscc pwmrfc w reset00000000 figure 11-37. pmf frequency control c register (pmffqcc) table 11-40. pmffqcc field descriptions field description 7?4 ldfqc load frequency c ? this field selects the pwm load frequency according to table 11-41 . see section 11.4.7.2, ?load frequency? for more details. note: the ldfqc field takes effect when the current load cycle is complete, re gardless of the state of the load okay bit, ldokc. reading the ldfqc field reads the buffered value and not necessarily the value currently in effect. 3 halfc half cycle reload c ? this bit enables half-cycle reloads in center-a ligned pwm mode. this bit has no effect on edge-aligned pwms. 0 half-cycle reloads disabled 1 half-cycle reloads enabled table 11-39. pmfencc field descriptions (continued) field description chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 350 freescale semiconductor 2 prscc prescaler c ? this buffered field selects the pwm clock frequency illustrated in table 11-42 . note: reading the prscc field reads the buffered value and not necessarily the value currently in effect. the prscc field takes effect at the beginning of the next pwm cycle and only when the load okay bit, ldokc, is set. 0 pwmrfc pwm reload flag c ? this flag is set at the b eginning of every reload cycle re gardless of the state of the ldokc bit. clear pwmrfc by reading pmffqcc with pwmrfc set and then writing a logic one to the pwmrfc bit. if another reload occurs before the clearing sequence is complete, writing logic one to pwmrfc has no effect. 0 no new reload cycle sinc e last pwmrfc clearing 1 new reload cycle since last pwmrfc clearing note: clearing pwmrfc satisfies pending pwmrfc cpu interrupt requests. table 11-41. pwm reload frequency c ldfqc pwm reload frequency ldfq[3:0] pwm reload frequency 0000 every pwm opportunity 1000 every 9 pwm opportunities 0001 every 2 pwm opportunities 1001 every 10 pwm opportunities 0010 every 3 pwm opportunities 1010 every 11 pwm opportunities 0011 every 4 pwm opportunities 1011 every 12 pwm opportunities 0100 every 5 pwm opportunities 1100 every 13 pwm opportunities 0101 every 6 pwm opportunities 1101 every 14 pwm opportunities 0110 every 7 pwm opportunities 1110 every 15 pwm opportunities 0111 every 8 pwm opportunities 1111 every 16 pwm opportunities table 11-42. pwm prescaler c prscc pwm clock frequency 00 f bus 01 f bus /2 10 f bus /4 11 f bus /8 table 11-40. pmffqcc field descriptions (continued) field description chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 351 11.3.2.32 pmf counter c register (pmfcntc) read anytime and writ es have no effect. 11.3.2.33 pmf counter modulo c register (pmfmodc) read anytime and writ e only if mtg is set. module base + 0x0032 1514131211109876543210 r 0 pmfcntc w reset000000000 0000000 = unimplemented or reserved figure 11-38. pmf counter c register (pmfcntc) table 11-43. pmfcntc field descriptions field description 14?0 pmfcntc? pmf counter c ? this register displays the st ate of the 15-bit pwm c counter. module base + 0x0034 1514131211109876543210 r0 pmfmodc w reset000000000 0000000 = unimplemented or reserved figure 11-39. pmf counter modulo c register (pmfmodc) table 11-44. pmfmodc field descriptions field description 14?0 pmfmodc pmf couner modulo c ? the 15-bit unsigned value written to this register is the pwm period in pwm clock periods. do not write a modulus value of zero. note: the pwm counter modulo register is buffered. the val ue written does not take effect until the ldokc bit is set and the next pwm load cycle begins. reading pmfmodc reads the value in the buffer. it is not necessarily the value the pwm g enerator a is currently using. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 352 freescale semiconductor 11.3.2.34 pmf deadtime c register (pmfdtmc) read anytime and write only if mtg is set. this register cannot be modified after the wp bit is set. module base + 0x0000 1514131211109876543210 r0000 pmfdtmc w reset000011111 1111111 = unimplemented or reserved figure 11-40. pmf deadtime c register (pmfdtmc) table 11-45. pmfdtmc field descriptions field description 11?0 pmfdtmc pmf deadtime c ? the 12-bit value wr itten to this register is the number of pwm clock cycles in complementary channel operation. a reset sets the pwm deadtime register to a default value of 0x0fff, selecting a deadti me of 4096-pwm clock cycles minus one bus clock cycle. note: deadtime is affected by changes to the prescaler value. the deadtime duration is determined as follows: dt = p pmfdtmc ? 1, where dt is deadtime, p is the prescaler value, pmfdtmc is the programmed value of dead time. for example: if the prescaler is programmed for a divide-by-two and the pmfdtmc is set to five, then p = 2 and the deadtime value is equal to dt = 2 5 ? 1 = 9 ipbus clock cycles. a special case exists when the p = 1, then dt = pmfdtmc. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 353 11.4 functional description 11.4.1 block diagram a block diagram of the pmf is shown in figure 11-1 . the mtg bit allows the use of multiple pwm generators (a, b, and c) or just a single generator (a). pwm0 and pw m1 constitute pair a, pwm2 and pwm3 constitute pair b, and pw m4 and pwm5 constitute pair c. 11.4.2 prescaler to permit lower pwm frequencies, the prescaler produces the pwm clock fre quency by dividing the bus clock frequency by one, two, four, and eight. each pw m generator has its own prescaler divisor. each prescaler is buffered and will not be used by its pw m generator until the corres ponding load ok bit is set and a new pwm reload cycle begins. 11.4.3 pwm generator each pwm generator contains a 15-bit up/dow n pwm counter producing output signals with software-selectables: ? alignment?the logic state of each pair edge bit determines whether the pwm pair outputs are edge-aligned or center-aligned ? period?the value written to eac h pair pwm counter modulo regist er is used to determine the pwm pair period. the period can also be varied by using the prescaler ? with edge-aligned output, the modulus is th e period of the pwm output in clock cycles ? with center-aligned output, the modulus is one-half of the pw m output period in clock cycles ? pulse width?the number written to the pwm value register deter mines the pulse width duty cycle of the pwm output in clock cycles ? with center-aligned output, the pul se width is twice the value wr itten to the pwm value register ? with edge-aligned output, the pulse width is the value written to the pwm value register 11.4.3.1 alignment each edge-align bit, edgex, selects either cente r-aligned or edge-aligned pwm generator outputs. figure 11-41. center-aligned pwm output up/down counter modulus = 4 alignment reference pwm output duty cycle = 50% chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 354 freescale semiconductor figure 11-42. edge-aligned pwm output note because of the equals-comparator arch itecture of this pmf, the modulus equals zero case is considered illegal. therefore, the modulus register does not return to zero, and a modulus valu e of zero will result in waveforms inconsistent with the other modulus waveforms. if a modulus of zero is loaded, the counter will continually count down from $7f ff. this operation will not be tested or gua ranteed. consider it illega l. however, the dead-time constraints and fault conditions will still be guaranteed. 11.4.3.2 period a pwm period is determined by the value wri tten to the pwm counter modulo register. the pwm counter is an up/down counter in a cent er-aligned operation. in this mode the pwm highest output resolution is two bus clock cycles. pwm period = (pwm modulus) (pwm clock period) 2 figure 11-43. center-aligned pwm period up counter modulus = 4 alignment reference pwm output duty cycle = 50% up/down counter pwm clock period pwm period = 8 x pwm clock period modulus = 4 count 1234 3210 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 355 in an edge-aligned operation, the pw m counter is an up counter. the pwm output resolution is one bus clock cycle. pwm period = pwm modulus pwm clock period figure 11-44. edge-aligned pwm period 11.4.3.3 duty cycle the signed 16-bit number wri tten to the pmf value registers is the pulse width in pwm clock periods of the pwm generator output. note a pwm value less than or equal to ze ro deactivates the pwm output for the entire pwm period. a pwm value greater than or equal to the modulus activates the pwm output for the entire pwm period. table 11-46. pwm value and underflow conditions pmfvalx condition pwm value used $0000?$7fff normal value in registers $8000?$ffff underflow $0000 up counter pwm clock period pwm period = 4 x pwm clock period modulus = 4 count 1 2 3 4 duty cycle pmfval modulus ------------------------------- - 100 = chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 356 freescale semiconductor center-aligned operation is illustrated in figure 11-45 . pwm pulse width = (pwm value) (pwm clock period) 2 figure 11-45. center-aligned pwm pulse width edge-aligned operation is illustrated in figure 11-46 . pwm pulse width = (pwm value) (pwm clock period) figure 11-46. edge-aligned pwm pulse width up/down counter modulus = 4 pwm value = 0 0/4 = 0% pwm value = 1 1/4 = 25% pwm value = 2 2/4 = 50% pwm value = 3 3/4 = 75% pwm value = 4 4/4 = 100% count 012343210123 4321 up counter pwm value = 0 modulus = 4 pwm value = 1 pwm value = 2 pwm value = 3 pwm value = 4 0/4 = 0% 1/4 = 25% 2/4 = 50% 3/4 = 75% 4/4 = 100% count 1 2 3 0 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 357 11.4.4 independent or comple mentary channel operation writing a logic one to a indepx bit configures a pair of the pw m outputs as two independent pwm channels. each pwm output has its own pwm value register operating independently of the other channels in independent channel operation. writing a logic zero to a indepx bit configures th e pwm output as a pair of complementary channels. the pwm pins are paired as shown in figure 11-47 in complementary channel operation. figure 11-47. complementary channel pairs the complementary channel operation is for driving t op and bottom transistors in a motor drive circuit, such as the one in figure 11-48 . figure 11-48. typical 3 phase ac motor drive pwm channels 0 and 1 pmfval1 pwm channels 2 and 3 pwm channels 4 and 5 register top bottom top bottom top bottom pmfval0 register pmfval3 register pmfval2 register pmfval5 register pmfval4 register pair a pa i r b pa i r c pwm 0 pwm 2 ac inputs to motor pwm 4 pwm 3 pwm 5 pwm 1 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 358 freescale semiconductor in complementary channel operation, there are three additional features: ? deadtime insertion ? separate top and bottom pulse widt h correction for distortions are ca used by deadtime inserted and the motor drive characteristics ? separate top and bottom ou tput polarity control ? swap functionality 11.4.5 deadtime generators while in the complementary mode, eac h pwm pair can be used to drive top/bottom transistors, as shown in figure 11-49 . ideally, the pwm pairs are an inversion of each other. when the top pwm channel is active, the bottom pwm channel is inactive, and vice versa. note to avoid a short-circuit on the dc bus and endangering the transistor, there must be no overlap of conducting intervals between top and bottom transistor. but the transistor?s charac teristics make its switching-off time longer than switching-on time. to a void the conducting overlap of top and bottom transistors, deadtime needs to be inserted in the switching period. deadtime generators automatically insert software-s electable activation delays into each pair of pwm outputs. the deadtime register (pmfdtmx) specifi es the number of pwm clock cycles to use for deadtime delay. every time the deadtime generator inputs changes st ate, deadtime is inserted. deadtime forces both pwm outputs in the pair to the inactive state. a method of correcting this, adding to or subtracting from the pwm value used, is discussed next. figure 11-49. deadtime generators mux out0 outctl0 mux out2 outctl2 mux out4 outctl4 pwm generator current status deadtime generator out1 deadtime generator deadtime generator pwm0 & pwm2 & pwm4 & out3 out5 top/bottom generator top/bottom generator top/bottom generator top (pwm0) to fault protection to fault protection to fault protection bottom (pwm1) top (pwm2) bottom (pwm3) top (pwm4) bottom (pwm5) pwm1 pwm3 pwm5 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 359 figure 11-50. deadtime inse rtion, center alignment figure 11-51. deadtime at duty cycle boundaries figure 11-52. deadtime and small pulse widths note the waveform at the pad is delayed by two bus clock cycles for deadtime insertion. pwm0, no deadtime pwm1, no deadtime pwm0, deadtime = 1 pwm1, deadtime = 1 modulus = 4 pwm value = 2 pwm0, no deadtime pwm1, no deadtime pwm0, deadtime = 2 pwm1, deadtime = 2 modulus = 3 pwm value = 3 pwm value = 3 pwm value = 3 pwm value = 1 modulus = 3 pwm0, no deadtime pwm0, deadtime = 3 pwm1, no deadtime pwm1, deadtime = 3 2 pwm value pwm value = 1 pwm value = 2 pwm value = 3 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 360 freescale semiconductor 11.4.5.1 top/bottom correction in complementary mode, either the top or the botto m transistor controls the output voltage. however, deadtime has to be inserted to a void overlap of conducting interval be tween the top and bottom transistor. both transistors in complementary mode are off dur ing deadtime, allowing the output voltage to be determined by the current status of load and introduce distor tion in the output voltage. see figure 11-53 . on ac induction motors running open-loop, the distorti on typically manifests itself as poor low-speed performance, such as torque ripple and rough operation. figure 11-53. deadtime distortion during deadtime, load inductance di storts output voltage by keeping current flowing through the diodes. this deadtime current flow creates a load voltage that varies with current direct ion. with a positive current flow, the load voltage during deadtime is equal to th e bottom supply, putting the t op transistor in control. with a negative current flow, the lo ad voltage during deadtim e is equal to the top supply putting the bottom transistor in control. remembering that the original pwm pulse widths we re shortened by deadtime insertion, the averaged sinusoidal output will be less than desired value. however, when deadtime is inserted, it creates a distortion in motor current waveform. this distortio n is aggravated by dissimilar turn-on and turn-off delays of each of the transistors. by giving the pwm module information on which transistor is controlling at a given time this distortion can be corrected. for a typical circuit in complement ary channel operation, only one of the transistors will be effective in controlling the output voltage at any given time. this depends on the direct ion of the motor current for that pair. see figure 11-53 . to correct distortion one of two different factors must be added to the desired pwm value, depending on whether th e top or bottom transistor is controll ing the output voltage . therefore, the software is responsible for calc ulating both compensated pwm values prior to placing them in an odd-numbered/even numbered pwm register pair. either the odd or the even pmfval register controls the pulse width at any given time. desired deadtime pwm to top positive negative pwm to bottom positive current negative current load voltage transistor transistor load voltage load voltage current current v+ chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 361 for a given pwm pair, whether the odd or even pm fval register is active depends on either: ? the state of the current status pin, isx , for that driver ? the state of the odd/even correction bit, ipolx, for that driver to correct deadtime distortion, soft ware can decrease or increase th e value in the appropriate pmfval register. ? in edge-aligned operation, decreasi ng or increasing the pwm value by a correction value equal to the deadtime typically compen sates for deadtime distortion. ? in center-aligned operation, decreasing or increa sing the pwm value by a correction value equal to one-half the deadtime typically compensates for deadtime distortion. in the complementary channel operation, isen s selects one of three correction methods: ? manual correction ? automatic current status correction during deadtime ? automatic current status correction when the pwm counter value equals the value in the pwm counter modulus registers note assume the user will provide curren t status sensing circuitry causing the voltage at the corresponding input pin to be low for positive current and high for negative current. in addition, it assumes the top pwms are pwm 0, 2, and 4 while the bottom pwms are pwm 1, 3, and 5. table 11-47. correction method selection isens correction method 00 no correction 1 1 the current status pins can be used as general purpose input/output ports. 01 manual correction 10 current status sample correction on pins is0 , is1 , and is2 during deadtime 2 2 the polarity of the isx pin is latched when both the top and bottom pwms are off. at the 0% and 100% duty cycle boundaries, there is no deadtime, so no new current value is sensed. 11 current status sample on pins is0 , is1 , and is2 3 at the half cycle in center-aligned operation at the end of the cycle in edge-aligned operation 3 current is sensed even with 0% or 100% duty cycle. chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 362 freescale semiconductor 11.4.5.2 manual correction the ipolx bits select either the odd or the even pwm value registers to use in the next pwm cycle. table 11-48. top/bottom manual correction note ipolx bits are buffered so only one pw m register is used per pwm cycle. if an ipolx bit changes during a pwm period, the new value does not take effect until the next pwm period. ipolx bits take effect at the end of each pwm cycle regardless of the state of the load okay bit, ldok. figure 11-54. internal correction logic when isens = 01 to detect the current status, the voltage on each isx pin is sampled twice in a pwm period, at the end of each deadtime. the value is stored in the dtx bits in the pmf deadtime sample register (pmfdtms). the dtx bits are a timing marker especially indicat ing when to toggle betwee n pwm value registers. software can then set the ipolx bit to toggle pmfval registers according to dtx values. bit logic atate output control ipola 0 pmfval0 controls pwm0/pwm1 pair 1 pmfval1 controls pwm0/pwm1 pair ipolb 0 pmfval2 controls pwm2/pwm3 pair 1 pmfval3 controls pwm2/pwm3 pair ipolc 0 pmfval4 controls pwm4/pwm5 pair 1 pmfval5 controls pwm4/pwm5 pair deadtime generator dq clk ipolx bit a/b a b top pwm bottom pwm pwm cycle start pwm controlled by odd pwmvalregister pwm controlled by even pwmval register chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 363 figure 11-55. current-status sense scheme for deadtime correction if both d flip-flops latch low, dt0 = 0, dt1 = 0, duri ng deadtime periods if curr ent is large and flowing out of the compleme ntary circuit. see figure 11-55 . if both d flip-flops latch the high, dt0 = 1, dt1 = 1, during deadtime periods if current is also large and flowing into th e complementary circuit. however, under low-current, the output voltage of the compleme ntary circuit during deadti me is somewhere between the high and low levels. the current cannot fr ee-wheel throughout the oppos ition anti-body diode, regardless of polarity, giving additi onal distortion when the current cros ses zero. sampled results will be dt0 = 0 and dt1 = 1. thus, the best ti me to change one pwm value register to another is just before the current zero crossing. figure 11-56. output voltage waveforms pwm0 pwm1 dq clk dq clk voltage sensor is0 pin pwm0 pwm1 dt0 dt1 positive current negative current deadtime pwm to top positive negative pwm to bottom load voltage with load voltage with transistor transistor high positive current low positive current current current load voltage with high negative current load voltage with negative current tbtb t = deadtime interval before assertion of top pwm b = deadtime interval before assertion of bottom pwm v + chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 364 freescale semiconductor 11.4.5.3 current-sensing correction a current sense pin, isx , for a pwm pair selects eith er the odd or the even pwm value registers to use in the next pwm cycle. the selecti on is based on user-provided curren t sense circuitry driving the isx pin high for negative current and low for positive current. previously shown, the curr ent direction can be dete rmined by the output voltage during deadtime. thus, a simple external voltage sensor can be used when current status is completed during deadtime, isens = 10. deadtime does not exists at the 100 percent and zero percent duty cycle boundaries. therefore, the second automatic mode must be used for correction, isens = 11, where current status is sampled at the half cycle in center-aligned operation and at the end of cycle in edge-aligned operation. using this mode requires external circuitry. it ac tually senses current direction. figure 11-57. internal correction logic when isens = 10 figure 11-58. internal correction logic when isens = 11 table 11-49. top/bottom current-sense correction pin logic state output control is0 0 pmfval0 controls pwm0/pwm1 pair 1 pmfval1 controls pwm0/pwm1 pair is1 0 pmfval2 controls pwm2/pwm3 pair 1 pmfval3 controls pwm2/pwm3 pair is2 0 pmfval4 controls pwm4/pwm5 pair 1 pmfval5 controls pwm4/pwm5 pair dq clk pwm controlled by pwm controlled by deadtime generator dq clk isx pin a/b a b pwm cycle start top pwm bottom pwm initial value = 0 odd pwmval register even pwmval register in deadtime dq clk pwm controlled by pwm controlled by deadtime generator dq clk isx pin a/b a b pwm cycle start top pwm bottom pwm initial value = 0 odd pwmval register even pwmval register pmfcnt = pmfmod chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 365 note values latched on the isx pins are buffered so only one pwm register is used per pwm cycle. if a current status change s during a pwm period, the new value does not take effect until the next pwm period. when initially enabled by setting the pwmen bit, no current status has previous ly been sampled. pwm value registers one, three, and five initially control th e three pwm pairs when conf igured for current status correction. 11.4.5.4 output polarity output polarity of the pwms is determined by two options: topn eg and botneg. the top polarity option, topneg, controls the polarity of pwm 0, pwm2 and pwm4. the bottom polarity option, botneg, controls the polarity of pwm1, pwm3 and pwm5. positive polarity means when the pwm is active its output is high. conversely, negative polarity means when the pwm is active its output is low. the topneg and botneg are in th e configure register. topneg is the output of pwm0, pwm2 and pwm4. they are active low. if topneg is set, pwm0, pwm2, and pwm4 outputs become active-low . when botneg is set, pwm 1, pwm3, and pwm5 outputs are active-low . when these bits are clear, their respective pwm pins are active-high . see figure 11-59 and figure 11-60 . figure 11-59. correction with positive current figure 11-60. correction with negative current desired load voltage bottom pwm load voltage top pwm desired load voltage bottom pwm load voltage top pwm chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 366 freescale semiconductor figure 11-61. pwm polarity 11.4.6 software output control setting output control enable bit, outctlx, enables software to drive the pwm outputs rather than the pwm generator. in an independent mode, with outctlx = 1, the output bit outx, controls the pwmx channel. in a complementary channel operation the ev en outctl bit is used to enable software output control for the pair. but the outctl bits must be switched in pairs for pr oper operation. the outctlx and outx bits are in the pwm output control register. note during software output control, topn eg and botneg s till control output polarity. it will take upto 3 clock cycles to see the effect of output control on the pwm output pins. in independent pwm operation, setting or clearing th e outx bit activates or deactivates the pwmx output. in complementary channel operati on, the even-numbered outx bits re place the pwm generator outputs as inputs to the deadtime generators. complementar y channel pairs still cannot be active simultaneously, and the deadtime generators continue to insert deadtime in both channels of that pair, whenever an even outx bit toggles. even outx bits control the top pw m signals while the odd outx bits control the bottom pwm signals with respect to the even outx bits. setting the odd outx bit makes its corresponding pwmx the complement of its even pa ir, while clearing the odd outx bit deactivates the odd pwmx. up/down counter pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 edge-aligned modulus = 4 up/down counter pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 modulus = 4 up counter pwm = 0 pwm = 2 pwm = 3 pwm = 4 pwm = 1 modulus = 4 center-aligned positive polarity positive polarity up counter pwm = 0 pwm = 2 pwm = 3 pwm = 4 pwm = 1 modulus = 4 center-aligned negative polarity edge-aligned negative polarity chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 367 setting the outctlx bits do not disable the pwm gene rators and current status sensing circuitry. they continue to run, but no longer cont rol the output pins. when the outc tlx bits are cleared, the outputs of the pwm generator become the inputs to the deadtime ge nerators at the beginning of the next pwm cycle. software can drive the pwm outputs even when pwm enable bit (pwmen) is set to zero. note avoid an unexpected deadtime inserti on by clearing the outx bits before setting and after clearing the outctlx bits. figure 11-62. setting out0 with outctl set in complementary mode modulus = 4 pwm value = 2 deadtime = 2 pwm0 pwm1 pwm0 with deadtime pwm1 with deadtime outctl0 out0 pwm0 pwm1 out1 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 368 freescale semiconductor figure 11-63. clearing out0 with outctl set in complementary mode figure 11-64. setting outctl with out0 set in complementary mode modulus = 4 pwm value = 2 deadtime = 2 pwm0 pwm1 pwm0 with deadtime pwm1 with deadtime outctl0 out0 pwm0 pwm1 out1 modulus = 4 pwm value = 2 deadtime = 2 pwm0 pwm1 pwm0 with deadtime pwm1 with deadtime outctl0 out0 pwm0 pwm1 out1 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 369 11.4.7 pwm generator loading 11.4.7.1 load enable the load okay bit, ldok, enables loading the pwm generator with: ? a prescaler divisor?from the prsc1 a nd prsc0 bits in pwm control register ? a pwm period?from the pwm counter modulus registers ? a pwm pulse width?from the pwm value registers ldok prevents reloading of these pw m parameters before software is finished calculat ing them setting ldok allows the prescaler bits, pm fmod and pmfvalx regist ers to be loaded into a set of buffers. the loaded buffers use the pwm generator at the beginni ng of the next pwm reload cycle. set ldok by reading it when it is a logic zero and then writing a logic one to it. after loading, ldok is automatically cleared. 11.4.7.2 load frequency the ldfq3, ldfq2, ldfq1, and ldfq0 b its in the pwm control register (pwmctl) select an integral loading frequency of one to 16-pwm reload opportuniti es. the ldfq bits take effect at every pwm reload opportunity, regardless the stat e of the load okay bit, ldok. the half bit in the pwmctl register controls half-cycle reloads fo r center-aligned pwms. if the half bit is set, a reload opportunity occurs at the beginning of every pwm cycle and half cycle when the count equals the modulus. if the half bit is not set, a reload opportunity occurs onl y at the beginning of every cycle. reload opportunities can only occur at the beginning of a pwm cycle in edge-aligned mode. note loading a new modulus on a half cycl e will force the count to the new modulus value minus one on the next cl ock cycle. half cycle reloads are possible only in center-aligned mode. enabling or disabling half-cycle reloads in edge-aligned mode will have no effect on the reload rate. figure 11-65. full cycle reload frequency change figure 11-66. half cycle reload frequency change reload change up/down to every two opportunities to every opportunity counter reload frequency to every four opportunities reload change up/down to every two opportunities to every opportunity counter reload frequency to every two opportunities to every four opportunities chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 370 freescale semiconductor 11.4.7.3 reload flag with a reload opportunity, regardless an actual relo ad occurs as determined by ldok bit, the pwmf reload flag is set. if the pwm reload interrupt enab le bit, pwmrie is set, th e pwmf flag generates cpu interrupt requests allowing software to calculate ne w pwm parameters in real time. when pwmrie is not set, reloads still occur at the selected relo ad rate without generati ng cpu interrupt requests. figure 11-67. pwmrf reload interrupt request figure 11-68. full-cycle center-aligned pwm value loading figure 11-69. full-cycle center-aligned modulus loading vdd cpu interrupt pwm reload request dq clk clr read pwmrf as 1 then write 0 to pwmf reset pwmrf pwmrie pwm half = 0, ldfq[3:0] = 00 = reload every cycle ldok = 1 modulus = 3 pwm value = 1 pwmrf = 1 0 3 2 1 1 3 2 1 0 3 1 1 up/down counter up/down pwm half = 0, ldfq[3:0] = 00 = reload every cycle ldok = 1 modulus = 2 pwm value = 1 pwmrf = 1 1 3 1 1 1 2 1 1 1 1 1 1 0 2 1 1 counter chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 371 figure 11-70. half-cycle center-aligned pwm value loading figure 11-71. half-cycle center-aligned modulus loading figure 11-72. edge-aligned pwm value loading pwm half = 1, ldfq[3:0] = 00 = reload every half-cycle ldok = 1 modulus = 3 pwm value = 1 pwmrf = 1 0 3 2 1 1 3 1 1 0 3 3 1 up/down counter 1 3 2 1 0 3 2 1 1 3 3 1 1 3 1 1 up/down pwm half = 1, ldfq[3:0] = 00 = reload every half-cycle ldok = 1 modulus = 2 pwm value = 1 pwmrf = 1 0 3 1 1 0 4 1 1 1 1 1 1 0 2 1 1 counter 0 2 1 1 1 4 1 1 1 4 1 1 up-only pwm ldfq[3:0] = 00 = reload every cycle counter ldok = 1 modulus = 3 pwm value = 1 pwmrf = 1 0 3 2 1 1 3 2 1 0 3 1 1 0 3 1 1 chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 372 freescale semiconductor figure 11-73. untitled figure 11.4.7.4 initialization initialize all registers and set the ldok bit befo re setting the pwmen bit. with ldok set, setting pwmen for the first time after re set, immediately loads the pwm ge nerator thereby se tting the pwmrf flag. pwmrf generates a cpu interr upt request if the pwmrie bit is set. in complementary channel operation with current-status correct ion selected, pwm value registers one, three, and five control the outputs for the first pwm cycle. note even if ldok is not set, setting pwmen also sets the pwmrf flag. to prevent a cpu interrupt request, cl ear the pwmrie bit before setting pwmen. setting pwmen for the first time afte r reset without first se tting ldok loads a pres caler divisor of one, a pwm value of $0000, and an unknown m odulus. the pwm generator uses the last values loaded if pwmen is cleared and then set while ldok equals zer o.initializing the deadtime register, after setting pwmen or outctlx, can cause an im proper deadtime insertion. howeve r, the deadtime can never be shorter than the specified value. figure 11-74. pwmen and pwm pins in independent operation figure 11-75. pwmen and pwm pins in complementary operation up-only pwm ldfq[3:0] = 00 = reload every cycle ldok = 1 modulus = 3 pwm value = 2 pwmrf = 1 counter 1 4 2 1 1 2 2 1 0 1 2 1 hi-z active hi-z ipbus pwmen pwm clock bit pins hi-z active ipbus pwmen pwm clock bit pins hi-z chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 373 when the pwmen bit is cleared: ? the pwmx outputs will be tri-stated unless outctlx = 1 ? the pwm counter is cl eared and does not count ? the pwm generator for ces its outputs to zero ? the pwmrf flag and pending cpu interrupt requests are not cleared ? all fault circuitry remain s active unless fpinex = 0 ? software output control remains active ? deadtime insertion continues during software output control 11.4.8 fault protection fault protection can disable any combination of pwm pins. faults are generate d by a logic one on any of the fault pins. each fault pin can be ma pped arbitrarily to any of the pwm pins. when fault protection hardware disables pwm pins, the pwm generator continues to run, only the output pins are deactivated. the fault decoder disables pwm pins selected by th e fault logic and the disable mapping register. see figure 11-15 . each bank of four bits in the disable mapping register cont rol the mapping for a single pwm pin. refer to table 11-12 . the fault protection is enabled even wh en the pwm is not enabled; therefor e, a fault will be latched in and will be cleared in order to prevent an interrupt when the pwm is enabled. 11.4.8.1 fault pin sample filter each fault pin has a sample filter to test for fault conditions. after every bus cy cle setting the faultx pin at logic zero, the filter synchron ously samples the pin once every four bus cycles. qsmp determines the number of consecutive samples that must be logic one fo r a fault to be detected. when a fault is detected, the corresponding faultx pin flag, fflagx, is set. clear fflagx by writing a logic one to it. if the fiex, faultx pin interrupt enable bit is se t, the fflagx flag generate s a cpu interrupt request. the interrupt request latch remains set until: ? software clears the fflagx fl ag by writing a logic one to it ? software clears the fiex bi t by writing a logic zero to it ? a reset occurs chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 374 freescale semiconductor 11.4.8.2 automatic fault clearing setting a fault mode bit, fmode x, configures faults from the fa ultx pin for automatic clearing. when fmodex is set, disabled pwm pins are enable d when the faultx pin returns to logic zero and a new pwm half cy cle begins. see figure 11-76 . clearing the fflagx flag doe s not affect disabled pwm pins when fmodex is set. figure 11-76. automatic fault clearing 11.4.8.3 manual fault clearing clearing a fault mode bit, fmode x, configures faults from the faultx pin for manual clearing: ? pwm pins disabled by the fault0 pin or the fault2 pin are enabled by clearing the corresponding fflagx flag. the time at whic h the pwm pins are enabled depends on the corresponding qsmpx bit setting. if qsmpx = 00, th e pwm pins are enabled on the next ip bus cycle when the logic level detected by the filter at the fault pin is logic zero. if qsmpx = 01,10 or 11, the pwms are enabled when the next pwm half cycle be gins regardless of th e state of the logic level detected by the filter at the fault. see figure 11-77 and figure 11-78 . ? pwm pins disabled by the fault1 pi n or the fault3 pin are enabled when ? software clears the corresponding fflagx flag ? the filter detects a lo gic zero on the fault pin at the star t of the next pwm half cycle boundary. see figure 11-79 . figure 11-77. manual fault clearing (faults 0 & 2) ? qsmp = 00 pwms enabled pwms disabled pwms enabled fault pin disabled enabled pwms enabled fault0 or fault2 pwms enabled pwms disabled fflagx cleared chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 375 figure 11-78. manual fault clearing (faults 0 & 2) - qsmp=01, 10, or 11 figure 11-79. manual fault clearing (faults 1 & 3) note pwm half-cycle boundaries occur at both the pwm cycle start and when the counter equals the modulus, so in edge-aligned operation full-cycles and half-cycles are equal. note fault protection also applies during software output control when the outctlx bits are set. fault cleari ng still occurs at half pwm cycle boundaries while the pwm generator is engaged, pwmen equals one. but the outx bits can control the pwm pi ns while the pwm generator is off, pwmen equals zero. thus, fault clearing occurs at ipbus cycles while the pwm generator is off and at the start of pwm cycles when the generator is engaged. 11.5 resets all pwm registers are reset to their default values upon any system reset. 11.6 clocks the system bus clock is the onl y clock required by this module. pwms enabled fault0 or fault2 pwms enabled pwms disabled fflagx cleared pwms enabled fault1 or fault3 pwms enabled pwms disabled fflagx cleared chapter 11 pulse width modulator with fault protection (pmf15b6cv2) mc9s12e256 data sheet, rev. 1.08 376 freescale semiconductor 11.7 interrupts seven pwm sources can genera te cpu interrupt requests: ? reload flag x (pwmrfx)?pwmrfx is set at th e beginning of every pwm generator x reload cycle. the reload interrupt enable bit, pwmr iex, enables pwmrfx to generate cpu interrupt requests. where x is a, b and c. ? fault flag x (fflagx)?the ffl agx bit is set when a logic one occurs on the faultx pin. the fault pin interrupt enable x bit, fiex, enables the fflagx flag to generate cpu in terrupt requests. where x is 0, 1, 2 and 3. mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 377 chapter 12 pulse-width modulator (pwm8b6cv1) 12.1 introduction the pulse width modulation (pwm) definition is based on the hc12 pwm definitions. the pwm8b6cv1 module contains the basic features fr om the hc11 with some of the enhancements incorporated on the hc12, that is center aligned out put mode and four availa ble clock sources. the pwm8b6cv1 module has six channels with independent control of le ft and center aligned outputs on each channel. each of the six pwm channels has a programmable period and duty cycle as well as a de dicated counter. a flexible clock select sche me allows a total of four different cloc k sources to be used with the counters. each of the modulators can create independent continuous waveforms wi th software-selectable duty rates from 0% to 100%. the pwm outputs can be programmed as left aligned outputs or center aligned outputs 12.1.1 features ? six independent pwm ch annels with programmabl e period and duty cycle ? dedicated counter for each pwm channel ? programmable pwm enable/disable for each channel ? software selection of pwm duty pulse polarity for each channel ? period and duty cycle are double buffered. change take s effect when the end of the effective period is reached (pwm counter reaches 0) or when the channel is disabled. ? programmable center or left al igned outputs on individual channels ? six 8-bit channel or three 16-bit channel pwm resolution ? four clock sources (a, b, sa, and sb) provide for a wide range of frequencies. ? programmable clock select logic ? emergency shutdown 12.1.2 modes of operation there is a software programmable opt ion for low power consum ption in wait mode th at disables the input clock to the prescaler. in freeze mode there is a software programmable option to disable the input clock to the prescaler. this is useful for emulation. chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 378 freescale semiconductor 12.1.3 block diagram figure 12-1. pwm8b6cv1 block diagram 12.2 external signal description the pwm8b6cv1 module has a total of six external pins. 12.2.1 pwm5 ? pulse width modulator channel 5 pin this pin serves as waveform output of pwm cha nnel 5 and as an input for the emergency shutdown feature. 12.2.2 pwm4 ? pulse width modulator channel 4 pin this pin serves as waveform output of pwm channel 4. 12.2.3 pwm3 ? pulse width modulator channel 3 pin this pin serves as waveform output of pwm channel 3. period and duty counter channel 5 bus clock clock select pwm clock period and duty counter channel 4 period and duty counter channel 3 period and duty counter channel 2 period and duty counter channel 1 period and duty counter channel 0 pwm channels alignment polarity control pwm8b6c pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 enable chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 379 12.2.4 pwm2 ? pulse width modulator channel 2 pin this pin serves as waveform output of pwm channel 2. 12.2.5 pwm1 ? pulse width modulator channel 1 pin this pin serves as waveform output of pwm channel 1. 12.2.6 pwm0 ? pulse width modulator channel 0 pin this pin serves as waveform output of pwm channel 0. 12.3 memory map and register definition this subsection describes in detail all the regist ers and register bits in the pwm8b6cv1 module. the special-purpose registers and regi ster bit functions that would not normally be made available to device end users, such as f actory test control register s and reserved registers ar e clearly identified by means of shading the appropriate portions of address maps and register diag rams. notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions. 12.3.1 module memory map the following paragraphs describe the content of the registers in the pwm8b6cv1 module. the base address of the pwm8b6cv1 module is determined at the mcu level when the mcu is defined. the register decode map is fixed and begins at the first address of th e module address offset. table 12-1 shows the registers associated with the pwm and their relative offset from the base address. the register detail description follows the order in whic h they appear in the register map. reserved bits within a register wi ll always read as 0 and the write will be unimplemented. unimplemented functions are indicate d by shading the bit. table 12-1 shows the memory map for the pwm8b6cv1 module. note register address = base a ddress + address offset, wh ere the base address is defined at the mcu level and the addr ess offset is defined at the module level. chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 380 freescale semiconductor table 12-1. pwm8b6cv1 memory map address offset register access 0x0000 pwm enable register (pwme) r/w 0x0001 pwm polarity register (pwmpol) r/w 0x0002 pwm clock select register (pwmclk) r/w 0x0003 pwm prescale clock sele ct register (pwmprclk) r/w 0x0004 pwm center align enable register (pwmcae) r/w 0x0005 pwm control register (pwmctl) r/w 0x0006 pwm test register (pwmtst) 1 1 pwmtst is intended for factory test purposes only. r/w 0x0007 pwm prescale counter register (pwmprsc) 2 2 pwmprsc is intended for factory test purposes only. r/w 0x0008 pwm scale a register (pwmscla) r/w 0x0009 pwm scale b register (pwmsclb) r/w 0x000a pwm scale a counter register (pwmscnta) 3 3 pwmscnta is intended for factory test purposes only. r/w 0x000b pwm scale b counter register (pwmscntb) 4 4 pwmscntb is intended for factory test purposes only. r/w 0x000c pwm channel 0 counter register (pwmcnt0) r/w 0x000d pwm channel 1 counter register (pwmcnt1) r/w 0x000e pwm channel 2 counter register (pwmcnt2) r/w 0x000f pwm channel 3 counter register (pwmcnt3) r/w 0x0010 pwm channel 4 counter register (pwmcnt4) r/w 0x0011 pwm channel 5 counter register (pwmcnt5) r/w 0x0012 pwm channel 0 period register (pwmper0) r/w 0x0013 pwm channel 1 period register (pwmper1) r/w 0x0014 pwm channel 2 period register (pwmper2) r/w 0x0015 pwm channel 3 period register (pwmper3) r/w 0x0016 pwm channel 4 period register (pwmper4) r/w 0x0017 pwm channel 5 period register (pwmper5) r/w 0x0018 pwm channel 0 duty register (pwmdty0) r/w 0x0019 pwm channel 1 duty register (pwmdty1) r/w 0x001a pwm channel 2 duty register (pwmdty2) r/w 0x001b pwm channel 3 duty register (pwmdty3) r/w 0x001c pwm channel 4 duty register (pwmdty4) r/w 0x001d pwm channel 5 duty register (pwmdty5) r/w 0x001e pwm shutdown register (pwmsdn) r/w chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 381 12.3.2 register descriptions the following paragraphs describe in detail all the registers and regi ster bits in the pwm8b6cv1 module. register name bit 7 6 5 4 3 2 1 bit 0 pwme r 0 0 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w pwmpol r 0 0 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w pwmclk r 0 0 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w pwmprclk r 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w pwmcae r 0 0 cae5 cae4 cae2 cae2 cae1 cae0 w pwmctl r 0 con45 con23 con01 pswai pfrz 00 w pwmtstr00 0 0000 0 w pwmprsc r 0 0 0 0 0 0 0 0 w pwmscla r bit 7 6 5 4 3 2 1 bit 0 w pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w pwmscnta r 0 0 0 0 0 0 0 0 w pwmscntb r 0 0 0 0 0 0 0 0 w pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 w00 0 0000 0 pwmcnt1 r bit 7 6 5 4 3 2 1 bit 0 w00 0 0000 0 pwmcnt2 r bit 7 6 5 4 3 2 1 bit 0 w00 0 0000 0 = unimplemented or reserved figure 12-2. pwm register summary chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 382 freescale semiconductor pwmcnt3 r bit 7 6 5 4 3 2 1 bit 0 w00 0 0000 0 pwmcnt4 r bit 7 6 5 4 3 2 1 bit 0 w00 0 0000 0 pwmcnt5 r bit 7 6 5 4 3 2 1 bit 0 w00 0 0000 0 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w pwmsdb r pwmif pwmie 0 pwmlvl 0pwm5in pwm5inl pwm5ena wpwmrstrt register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 12-2. pwm register summary (continued) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 383 12.3.2.1 pwm enable register (pwme) each pwm channel has an enable bit (pwmex) to st art its waveform output. when any of the pwmex bits are set (pwmex = 1), the asso ciated pwm output is enabled imme diately. however, the actual pwm waveform is not available on the associated pwm output until its cloc k source begins its next cycle due to the synchronization of pwmex and the clock source. note the first pwm cycle after enabli ng the channel can be irregular. an exception to this is when channels are concaten ated. after concatenated mode is enabled (conxx bits set in pwmctl register), enabling/ disabling the corresponding 16-bit pw m channel is controlled by the low-order pwmex bit. in this case, the high-or der bytes pwmex bits have no effect and their corresponding pwm output lines are disabled. while in run mode, if all six pwm channels are di sabled (pwme5?pwme0 = 0), the prescaler counter shuts off for power savings. read: anytime write: anytime 76543210 r0 0 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w reset00000000 = unimplemented or reserved figure 12-3. pwm enable register (pwme) table 12-2. pwme field descriptions field description 5 pwme5 pulse width channel 5 enable 0 pulse width channel 5 is disabled. 1 pulse width channel 5 is enabled. the pulse modulate d signal becomes available at pwm,output bit 5 when its clock source begins its next cycle. 4 pwme4 pulse width channel 4 enable 0 pulse width channel 4 is disabled. 1 pulse width channel 4 is enabled. the pulse modulated signal becomes available at pwm, output bit 4 when its clock source begins its next cycle. if con45 = 1, then bit has no effect and pwm output line 4 is disabled. 3 pwme3 pulse width channel 3 enable 0 pulse width channel 3 is disabled. 1 pulse width channel 3 is enabled. the pulse modulated signal becomes available at pwm, output bit 3 when its clock source begins its next cycle. 2 pwme2 pulse width channel 2 enable 0 pulse width channel 2 is disabled. 1 pulse width channel 2 is enabled. the pulse modulated signal becomes available at pwm, output bit 2 when its clock source begins its next cycle. if con23 = 1, t hen bit has no effect and pwm output line 2 is disabled. chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 384 freescale semiconductor 12.3.2.2 pwm polarity register (pwmpol) the starting polarity of each pwm channel waveform is determined by the associated ppolx bit in the pwmpol register. if the polarity bit is 1, the pwm ch annel output is high at the beginning of the cycle and then goes low when the duty count is reached. conversely, if the polarity bit is 0 the output starts low and then goes high when th e duty count is reached. read: anytime write: anytime note ppolx register bits can be written anytime. if the polarity is changed while a pwm signal is being generated, a trunc ated or stretched pulse can occur during the transition 1 pwme1 pulse width channel 1 enable 0 pulse width channel 1 is disabled. 1 pulse width channel 1 is enabled. the pulse modulated signal becomes available at pwm, output bit 1 when its clock source begins its next cycle. 0 pwme0 pulse width channel 0 enable 0 pulse width channel 0 is disabled. 1 pulse width channel 0 is enabled. the pulse modulated signal becomes available at pwm, output bit 0 when its clock source begins its next cycle. if con01 = 1, then bit has no effect and pwm output line 0 is disabled. 76543210 r0 0 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w reset00000000 = unimplemented or reserved figure 12-4. pwm polarity register (pwmpol) table 12-3. pwmpol field descriptions field description 5 ppol5 pulse width channel 5 polarity 0 pwm channel 5 output is low at the beginning of the period, then goes high when the duty count is reached. 1 pwm channel 5 output is high at the beginning of the pe riod, then goes low when the duty count is reached. 4 ppol4 pulse width channel 4 polarity 0 pwm channel 4 output is low at the beginning of the period, then goes high when the duty count is reached. 1 pwm channel 4 output is high at the beginning of the pe riod, then goes low when the duty count is reached. 3 ppol3 pulse width channel 3 polarity 0 pwm channel 3 output is low at the beginning of the period, then goes high when the duty count is reached. 1 pwm channel 3 output is high at the beginning of the pe riod, then goes low when the duty count is reached. table 12-2. pwme field descriptions (continued) field description chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 385 12.3.2.3 pwm clock select register (pwmclk) each pwm channel has a choice of two clocks to us e as the clock source for that channel as described below. read: anytime write: anytime note register bits pclk0 to pclk5 can be written anytime. if a clock select is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. 2 ppol2 pulse width channel 2 polarity 0 pwm channel 2 output is low at the beginning of the period, then goes high when the duty count is reached. 1 pwm channel 2 output is high at the beginning of the pe riod, then goes low when the duty count is reached. 1 ppol1 pulse width channel 1 polarity 0 pwm channel 1 output is low at the beginning of the period, then goes high when the duty count is reached. 1 pwm channel 1 output is high at the beginning of the pe riod, then goes low when the duty count is reached. 0 ppol0 pulse width channel 0 polarity 0 pwm channel 0 output is low at the beginning of the period, then goes high when the duty count is reached 1 pwm channel 0 output is high at the beginning of the pe riod, then goes low when the duty count is reached. 76543210 r0 0 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w reset00000000 = unimplemented or reserved figure 12-5. pwm clock se lect register (pwmclk) table 12-4. pwmclk field descriptions field description 5 pclk5 pulse width channel 5 clock select 0 clock a is the clock source for pwm channel 5. 1 clock sa is the clock source for pwm channel 5. 4 pclk4 pulse width channel 4 clock select 0 clock a is the clock source for pwm channel 4. 1 clock sa is the clock source for pwm channel 4. 3 pclk3 pulse width channel 3 clock select 0 clock b is the clock source for pwm channel 3. 1 clock sb is the clock source for pwm channel 3. table 12-3. pwmpol field descriptions (continued) field description chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 386 freescale semiconductor 12.3.2.4 pwm prescale clock se lect register (pwmprclk) this register selects the prescale clock source for clocks a and b independently. read: anytime write: anytime note pckb2?pckb0 and pcka2?pcka0 register bits can be written anytime. if the clock prescale is changed whil e a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. 2 pclk2 pulse width channel 2 clock select 0 clock b is the clock source for pwm channel 2. 1 clock sb is the clock source for pwm channel 2. 1 pclk1 pulse width channel 1 clock select 0 clock a is the clock source for pwm channel 1. 1 clock sa is the clock source for pwm channel 1. 0 pclk0 pulse width channel 0 clock select 0 clock a is the clock source for pwm channel 0. 1 clock sa is the clock source for pwm channel 0. 76543210 r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w reset00000000 = unimplemented or reserved figure 12-6. pwm prescaler clock select register (pwmprclk) table 12-5. pwmprclk field descriptions field description 6:5 pckb[2:0] prescaler select for clock b ? clock b is 1 of two clock sources which can be used for channels 2 or 3. these three bits determine the rate of clock b, as shown in ta bl e 1 2 - 6 . 2:0 pcka[2:0] prescaler select for clock a ? clock a is 1 of two clock sources which can be used for channels 0, 1, 4, or 5. these three bits determine the ra te of clock a, as shown in ta bl e 1 2 - 7 . table 12-4. pwmclk field descriptions (continued) field description chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 387 12.3.2.5 pwm center align enable register (pwmcae) the pwmcae register contains six c ontrol bits for the selection of cent er aligned outputs or left aligned outputs for each pwm channel. if the caex bit is se t to a 1, the corresponding pw m output will be center aligned. if the caex bit is cleared, the corres ponding pwm output will be left aligned. reference section 12.4.2.5, ?left aligned outputs , ? and section 12.4.2.6, ?center aligned outputs , ? for a more detailed description of the pwm output modes. read: anytime write: anytime note write these bits only when the corresponding channel is disabled. table 12-6. clock b prescaler selects pckb2 pckb1 pckb0 value of clock b 0 0 0 bus clock 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128 table 12-7. clock a prescaler selects pcka2 pcka1 pcka0 value of clock a 0 0 0 bus clock 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128 76543210 r0 0 cae5 cae4 cae3 cae2 cae1 cae0 w reset00000000 = unimplemented or reserved figure 12-7. pwm center align enable register (pwmcae) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 388 freescale semiconductor 12.3.2.6 pwm control register (pwmctl) the pwmctl register provides for various control of the pwm module. read: anytime write: anytime there are three control bits for concat enation, each of which is used to concatenate a pair of pwm channels into one 16-bit channel. when channels 4 and 5 are concatenated, channel 4 registers become the high-order bytes of the double-byte cha nnel. when channels 2 and 3 are concatenated, channel 2 registers become the high-order bytes of the double-byte cha nnel. when channels 0 and 1 are concatenated, channel 0 registers become the high-or der bytes of the double-byte channel. table 12-8. pwmcae field descriptions field description 5 cae5 center aligned output mode on channel 5 0 channel 5 operates in left aligned output mode. 1 channel 5 operates in center aligned output mode. 4 cae4 center aligned output mode on channel 4 0 channel 4 operates in left aligned output mode. 1 channel 4 operates in center aligned output mode. 3 cae3 center aligned output mode on channel 3 1 channel 3 operates in left aligned output mode. 1 channel 3 operates in center aligned output mode. 2 cae2 center aligned output mode on channel 2 0 channel 2 operates in left aligned output mode. 1 channel 2 operates in center aligned output mode. 1 cae1 center aligned output mode on channel 1 0 channel 1 operates in left aligned output mode. 1 channel 1 operates in center aligned output mode. 0 cae0 center aligned output mode on channel 0 0 channel 0 operates in left aligned output mode. 1 channel 0 operates in center aligned output mode. 76543210 r0 con45 con23 con01 pswai pfrz 00 w reset00000000 = unimplemented or reserved figure 12-8. pwm control register (pwmctl) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 389 reference section 12.4.2.7, ?pwm 16-bit functions , ? for a more detailed descri ption of the concatenation pwm function. note change these bits only when both co rresponding channels are disabled. table 12-9. pwmctl field descriptions field description 6 con45 concatenate channels 4 and 5 0 channels 4 and 5 are separate 8-bit pwms. 1 channels 4 and 5 are concatenated to create one 16-bit pwm channel. channel 4 becomes the high-order byte and channel 5 becomes the low-order byte. channel 5 output pin is used as the output for this 16-bit pwm (bit 5 of port pwmp). channel 5 clock select control bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. 5 con23 concatenate channels 2 and 3 0 channels 2 and 3 are separate 8-bit pwms. 1 channels 2 and 3 are concatenated to create one 16-bit pwm channel. channel 2 becomes the high-order byte and channel 3 becomes the low-order byte. channel 3 output pin is used as the output for this 16-bit pwm (bit 3 of port pwmp). channel 3 clock select control bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. 4 con01 concatenate channels 0 and 1 0 channels 0 and 1 are separate 8-bit pwms. 1 channels 0 and 1 are concatenated to create one 16-bit pwm channel. channel 0 becomes the high-order byte and channel 1 becomes the low-order byte. channel 1 output pin is used as the output for this 16-bit pwm (bit 1 of port pwmp). channel 1 clock select control bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. 3 pswai pwm stops in wait mode ? enabling this bit allows for lower power c onsumption in wait mode by disabling the input clock to the prescaler. 0 allow the clock to the prescaler to continue while in wait mode. 1 stop the input clock to the prescaler whenever the mcu is in wait mode. 2 pfrz pwm counters stop in freeze mode ? in freeze mode, there is an option to disable the input clock to the prescaler by setting the pfrz bit in t he pwmctl register. if this bit is set, whenever the mcu is in freeze mode the input clock to the prescaler is disabled. this feature is useful during emulation as it allows the pwm function to be suspended. in this way, the counters of the pwm c an be stopped while in freeze mode so that after normal program flow is continued, the counters are re-enabled to simulate real-time operations. because the registers remain accessible in this mode, to re-e nable the prescaler clock, either disabl e the pfrz bit or exit freeze mode. 0 allow pwm to continue while in freeze mode. 1 disable pwm input clock to the prescaler whenever the part is in freeze mode. this is useful for emulation. chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 390 freescale semiconductor 12.3.2.7 reserved register (pwmtst) this register is reserved for factory testing of the pwm module and is not available in normal modes. read: always read 0x0000 in normal modes write: unimplemented in normal modes note writing to this register when in special modes can alter the pwm functionality. 12.3.2.8 reserved register (pwmprsc) this register is reserved for factory testing of the pwm module and is not available in normal modes. read: always read 0x0000 in normal modes write: unimplemented in normal modes note writing to this register when in special modes can alter the pwm functionality. 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 12-9. reserved register (pwmtst) 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 12-10. reserved register (pwmprsc) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 391 12.3.2.9 pwm scale a register (pwmscla) pwmscla is the programmable scale value used in sc aling clock a to generate clock sa. clock sa is generated by taking clock a, dividing it by the value in the pwmscla register and divi ding that by two. clock sa = clock a / (2 * pwmscla) note when pwmscla = 0x0000, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmscla). read: anytime write: anytime (causes the scale counter to load the pwmscla value) 12.3.2.10 pwm scale b register (pwmsclb) pwmsclb is the programmable scale value used in sc aling clock b to generate clock sb. clock sb is generated by taking clock b, dividi ng it by the value in the pwmsclb register and divi ding that by two. clock sb = clock b / (2 * pwmsclb) note when pwmsclb = 0x0000, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmsclb). read: anytime write: anytime (causes the scale c ounter to load the pwmsclb value). 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset00000000 figure 12-11. pwm scale a register (pwmscla) 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset00000000 figure 12-12. pwm scale b register (pwmsclb) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 392 freescale semiconductor 12.3.2.11 reserved registers (pwmscntx) the registers pwmscnta and pwms cntb are reserved for factory testing of the pwm module and are not available in normal modes. read: always read 0x0000 in normal modes write: unimplemented in normal modes note writing to these registers when in special modes can alter the pwm functionality. 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 12-13. reserved register (pwmscnta) 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 12-14. reserved register (pwmscntb) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 393 12.3.2.12 pwm channel counter registers (pwmcntx) each channel has a dedicated 8-bit up/down counter whic h runs at the rate of the selected clock source. the counter can be read at any time without affecti ng the count or the operation of the pwm channel. in left aligned output mode, the counter counts from 0 to th e value in the period regist er ? 1. in center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to up, the immediate load of both duty and period register s with values from the buffers, and the output to change according to the polarity bit. the counter is also cleared at th e end of the effective period (see section 12.4.2.5, ?left aligned outputs , ? and section 12.4.2.6, ?center aligned outputs , ? for more details). when the channel is di sabled (pwmex = 0), the pwmcntx register does not count. when a channel becomes enabled (pwmex = 1), the associ ated pwm counter starts at the count in the pwmcntx register. for more detailed informat ion on the operation of the counters, reference section 12.4.2.4, ?pwm timer counters.? in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low- or high-order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. note writing to the counter while the chan nel is enabled can cause an irregular pwm cycle to occur. 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset00000000 figure 12-15. pwm channel counter registers (pwmcnt0) 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset00000000 figure 12-16. pwm channel counter registers (pwmcnt1) 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset00000000 figure 12-17. pwm channel counter registers (pwmcnt2) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 394 freescale semiconductor read: anytime write: anytime (any value written causes pwm counter to be reset to 0x0000). 12.3.2.13 pwm channel peri od registers (pwmperx) there is a dedicated period register for each channel. the value in this register determines the period of the associated pwm channel. the period registers for each channel are double buffere d so that if they change while the channel is enabled, the change will not take eff ect until one of the following occurs: ? the effective period ends ? the counter is written (counter resets to 0x0000) ? the channel is disabled in this way, the output of the pwm will always be ei ther the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writes to the peri od register will go directly to the latches as well as the buffer. note reads of this register return the mo st recent value written. reads do not necessarily return the value of the currently active period due to the double buffering scheme. reference section 12.4.2.3, ?pwm period and duty , ? for more information. 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset00000000 figure 12-18. pwm channel counter registers (pwmcnt3) 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset00000000 figure 12-19. pwm channel counter registers (pwmcnt4) 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset00000000 figure 12-20. pwm channel counter registers (pwmcnt5) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 395 to calculate the output period, take th e selected clock source period for the channel of interest (a, b, sa, or sb) and multiply it by the value in the period register for that channel: ? left aligned output (caex = 0) ? pwmx period = channel clock period * pw mperx center aligned output (caex = 1) ? pwmx period = channel cloc k period * (2 * pwmperx) for boundary case programming values, please refer to section 12.4.2.8, ?pwm boundary cases.? 76543210 r bit 7654321bit 0 w reset00000000 figure 12-21. pwm channel period registers (pwmper0) 76543210 r bit 7654321bit 0 w reset00000000 figure 12-22. pwm channel period registers (pwmper1) 76543210 r bit 7654321bit 0 w reset00000000 figure 12-23. pwm channel period registers (pwmper2) 76543210 r bit 7654321bit 0 w reset00000000 figure 12-24. pwm channel period registers (pwmper3) 76543210 r bit 7654321bit 0 w reset00000000 figure 12-25. pwm channel period registers (pwmper4) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 396 freescale semiconductor read: anytime write: anytime 12.3.2.14 pwm channel duty registers (pwmdtyx) there is a dedicated duty register for each channel. th e value in this register determines the duty of the associated pwm channel. the duty valu e is compared to the c ounter and if it is equa l to the counter value a match occurs and the output changes state. the duty registers for each channel ar e double buffered so that if they ch ange while the channel is enabled, the change will not take effect until one of the following occurs: ? the effective period ends ? the counter is written (counter resets to 0x0000) ? the channel is disabled in this way, the output of the pwm w ill always be either the old duty waveform or the new duty waveform, not some variation in between. if the ch annel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. note reads of this register return the mo st recent value written. reads do not necessarily return the value of the currently active duty due to the double buffering scheme. reference section 12.4.2.3, ?pwm period and duty , ? for more information. note depending on the polarity bit, the duty re gisters will contain the count of either the high time or the low time. if the polarity bit is 1, the output starts high and then goes low when the duty c ount is reached, so the duty registers contain a count of the high time. if the polarity bit is 0, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. to calculate the output duty cycle (high time as a % of period) for a particular channel: ? polarity = 0 (ppolx = 0) duty cycle = [(pwmperx? pwmdtyx)/pwmperx] * 100% ? polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% ? for boundary case programming values, please refer to section 12.4.2.8, ?pwm boundary cases.? 76543210 r bit 7654321bit 0 w reset00000000 figure 12-26. pwm channel period registers (pwmper5) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 397 read: anytime write: anytime 76543210 r bit 7654321bit 0 w reset11111111 figure 12-27. pwm channel duty registers (pwmdty0) 76543210 r bit 7654321bit 0 w reset11111111 figure 12-28. pwm channel duty registers (pwmdty1) 76543210 r bit 7654321bit 0 w reset11111111 figure 12-29. pwm channel duty registers (pwmdty2) 76543210 r bit 7654321bit 0 w reset11111111 figure 12-30. pwm channel duty registers (pwmdty3) 76543210 r bit 7654321bit 0 w reset11111111 figure 12-31. pwm channel duty registers (pwmdty4) 76543210 r bit 7654321bit 0 w reset11111111 figure 12-32. pwm channel duty registers (pwmdty5) chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 398 freescale semiconductor 12.3.2.15 pwm shutdown register (pwmsdn) the pwmsdn register provides for the shutdown f unctionality of the pwm module in the emergency cases. read: anytime write: anytime 76543210 r pwmif pwmie 0 pwmlvl 0pwm5in pwm5inl pwm5ena wpwmrstrt reset00000000 = unimplemented or reserved figure 12-33. pwm shutdown register (pwmsdn) table 12-10. pwmsdn field descriptions field description 7 pwmif pwm interrupt flag ? any change from passive to asserted (active) state or from active to passive state will be flagged by setting the pwmif flag = 1. the flag is clear ed by writing a logic 1 to it. writing a 0 has no effect. 0 no change on pwm5in input. 1 change on pwm5in input 6 pwmie pwm interrupt enable ? if interrupt is enabled an interrupt to the cpu is asserted. 0 pwm interrupt is disabled. 1 pwm interrupt is enabled. 5 pwmrstrt pwm restart ? the pwm can only be restarted if the pwm chann el input 5 is deasserted. after writing a logic 1 to the pwmrstrt bit (trigger event) the pwm channel s start running after the corresponding counter passes next ?counter = 0? phase. also, if the pwm5ena bit is reset to 0, the pwm do not start before the counter passes 0x0000. the bit is always read as 0. 4 pwmlvl pwm shutdown output level ? if active level as defined by the pwm5in input, gets asserted all enabled pwm channels are immediately driven to the level defined by pwmlvl. 0 pwm outputs are forced to 0 1 pwm outputs are forced to 1. 2 pwm5in pwm channel 5 input status ? this reflects the current status of the pwm5 pin. 1 pwm5inl pwm shutdown active in put level for channel 5 ? if the emergency shutdown feature is enabled (pwm5ena = 1), this bit determines the active level of the pwm5 channel. 0 active level is low 1 active level is high 0 pwm5ena pwm emergency shutdown enable ? if this bit is logic 1 the pin associated with channel 5 is forced to input and the emergency shutdown feature is enabled. all the ot her bits in this register are meaningful only if pwm5ena = 1. 0 pwm emergency feature disabled. 1 pwm emergency feature is enabled. chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 399 12.4 functional description 12.4.1 pwm clock select there are four available clocks cal led clock a, clock b, clock sa (s caled a), and clock sb (scaled b). these four clocks are based on the bus clock . clock a and b can be software sele cted to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. clock sa uses clock a as an input and divides it further with a reloadable counter. similarly, clock sb uses clock b as an input and divides it further with a reloadable counter. the rates available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. similar rates are available for clock sb. each pwm channel has the capab ility of selecting one of two clocks, either the pre-scaled clock (clock a or b) or the scaled clock (clock sa or sb). the block diagram in figure 12-34 shows the four different clocks a nd how the scaled clocks are created. 12.4.1.1 prescale the input clock to the pwm prescaler is the bus clock. it can be disabled whenever the part is in freeze mode by setting the pfrz bit in the pw mctl register. if this bit is set, whenever the mcu is in freeze mode the input clock to the prescaler is disabled. this is useful for emulation in order to freeze the pwm. the input clock can also be disabled when all si x pwm channels are disabled (pwme5?pwme0 = 0) this is useful for re ducing power by disabling the prescale counter. clock a and clock b are scal ed values of the input clock. the value is software selectab le for both clock a and clock b and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/ 128 times the bus clock. the value selected for clock a is determined by the pcka2, pcka1, and pc ka0 bits in the pwmprclk register. the value selected for clock b is determined by the pckb2, pckb1, and pckb0 bits also in the pwmprclk register. chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 400 freescale semiconductor figure 12-34. pwm clock select block diagram 2 4 8 16 32 64 128 pckb2 pckb1 pckb0 m u x clock a clock b clock sa clock a/2, a/4, a/6,....a/512 prescale scale divide by prescaler taps: pfrz freeze bus clock clock select m u x pclk0 clock to pwm ch 0 m u x pclk2 clock to pwm ch 2 m u x pclk1 clock to pwm ch 1 m u x pclk4 clock to pwm ch 4 m u x pclk5 clock to pwm ch 5 m u x pclk3 clock to pwm ch 3 load div 2 pwmsclb 8-bit down counter clock sb clock b/2, b/4, b/6,....b/512 m u x pcka2 pcka1 pcka0 pwme5:0 count = 1 load div 2 pwmscla 8-bit down counter count = 1 chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 401 12.4.1.2 clock scale the scaled a clock uses clock a as an input and di vides it further with a us er programmable value and then divides this by 2. the scaled b clock uses cloc k b as an input and divides it further with a user programmable value and then divides this by 2. the ra tes available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8, ..., or 512 in increm ents of divide by 2. simila r rates are available for clock sb. clock a is used as an input to an 8-bit down counter. th is down counter loads a user programmable scale value from the scale regi ster (pwmscla). when the down counter reaches 1, two things happen; a pulse is output and the 8-bit counter is re-loaded. the output signal from this circuit is further divided by two. this gives a greater range with onl y a slight reduction in granularity. clock sa equals clock a divided by two times the value in the pwmscla register. note clock sa = clock a / (2 * pwmscla) when pwmscla = 0x0000, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. similarly, clock b is used as an input to an 8-bit down counter followed by a divide by two producing clock sb. thus, clock sb equals clock b divided by two times the value in the pwmsclb register. note clock sb = clock b / (2 * pwmsclb) when pwmsclb = 0x0000, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. as an example, consider the case in which the us er writes 0x00ff into the pwmscla register. clock a for this case will be bus clock divided by 4. a pulse will occur at a rate of once every 255 x 4 bus cycles. passing this through the di vide by two circuit produces a clock signal at a bus clock divided by 2040 rate. similarly, a value of 0x0001 in the pwmscla register when clock a is bus clock divided by 4 will produce a bus clock divided by 8 rate. writing to pwmscla or pwmsclb causes the a ssociated 8-bit down counter to be re-loaded. otherwise, when changing rates th e counter would have to count down to 0x0001 be fore counting at the proper rate. forcing the associated counter to re-load the scale regist er value every time pwmscla or pwmsclb is written prevents this. note writing to the scale registers whil e channels are operating can cause irregularities in the pwm outputs. chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 402 freescale semiconductor 12.4.1.3 clock select each pwm channel has the capability of selecting one of two clocks. fo r channels 0, 1, 4, and 5 the clock choices are clock a or cl ock sa. for channels 2 and 3 the choices are clock b or clock sb. the clock selection is done with th e pclkx control bits in the pwmclk register. note changing clock control bits while channels are operating can cause irregularities in the pwm outputs. 12.4.2 pwm channel timers the main part of the pwm module are the actual timers . each of the timer channels has a counter, a period register and a duty register (each are 8 bit). the wa veform output period is controlled by a match between the period register and the value in the counter. the dut y is controlled by a match between the duty register and the counter value and causes th e state of the output to change dur ing the period. the starting polarity of the output is al so selectable on a per channel basis. figure 12-35 shows a block diag ram for pwm timer. figure 12-35. pwm timer channel block diagram clock source t r q q m u x ppolx from port pwmp data register pwmex (clock edge sync) to pin driver gate 8-bit compare = pwmdtyx 8-bit compare = pwmperx m u x caex up/down t r q q reset 8-bit counter pwmcntx chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 403 12.4.2.1 pwm enable each pwm channel has an enable bit (pwmex) to st art its waveform output. when any of the pwmex bits are set (pwmex = 1), the asso ciated pwm output signal is enable d immediately. however, the actual pwm waveform is not avai lable on the associated pwm output until it s clock source begins its next cycle due to the synchronization of pwmex and the clock sour ce. an exception to this is when channels are concatenated. refer to section 12.4.2.7, ?pwm 16-bit functions , ? for more detail. note the first pwm cycle after enabli ng the channel can be irregular. on the front end of the pwm timer, the clock is enabled to the pwm circuit by the pwmex bit being high. there is an edge-synchronizing circuit to guarantee that the clock will onl y be enabled or disabled at an edge. when the channel is disabled (pwmex = 0), the counter for the channel does not count. 12.4.2.2 pwm polarity each channel has a polarity bit to al low starting a waveform cycle with a high or low signal. this is shown on the block diagram as a mux select of either the q output or the q output of the pwm output flip-flop. when one of the bits in the pwmpol register is se t, the associated pwm channel output is high at the beginning of the waveform, then goes low when the duty count is reac hed. conversely, if the polarity bit is 0, the output starts low and then goe s high when the duty count is reached. 12.4.2.3 pwm period and duty dedicated period and duty re gisters exist for each chan nel and are double bu ffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: ? the effective period ends ? the counter is written (counter resets to 0x0000) ? the channel is disabled in this way, the output of the pwm will always be ei ther the old waveform or the new waveform, not some variation in between. if the channe l is not enabled, then writes to th e period and duty registers will go directly to the latches as well as the buffer. a change in duty or period can be forced into effect ?immediately? by writing the new value to the duty and/or period registers and then writ ing to the counter. this forces the counter to reset and the new duty and/or period values to be latched. in addition, because the counter is r eadable it is possi ble to know where the count is with respect to the duty value and software can be used to make adjustments . note when forcing a new period or duty into effect immediately, an irregular pwm cycle can occur. depending on the polarity bit, the duty re gisters will contain the count of either the high time or the low time. chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 404 freescale semiconductor 12.4.2.4 pwm timer counters each channel has a dedicated 8-bit up/down counter whic h runs at the rate of the selected clock source (reference figure 12-34 for the available cl ock sources and rates) . the counter compares to two registers, a duty register and a peri od register as shown in figure 12-35 . when the pwm counter matches the duty register the output flip-flop changes state causing the pwm waveform to also change state. a match between the pwm counter and the pe riod register behaves differently depending on what output mode is selected as shown in figure 12-35 and described in section 12.4.2.5, ?left aligned outputs , ? and section 12.4.2.6, ?center aligned outputs.? each channel counter can be read at anytime wit hout affecting the count or the operation of the pwm channel. any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to up, the immediate load of both duty and period register s with values from the buffers, and the output to change according to the polarity bit. when the channel is di sabled (pwmex = 0), the counter stops. when a channel becomes enabled (pwmex = 1), the associated pw m counter continues from the count in the pwmcntx register. this allows the waveform to re sume when the channel is re-enabled. when the channel is disabled, writing 0 to th e period register will cause the count er to reset on the next selected clock. note if the user wants to start a new ?clean? pwm waveform without any ?history? from the old waveform, the user must write to channel counter (pwmcntx) prior to enabling th e pwm channel (pwmex = 1). generally, writes to the counter are done prior to enab ling a channel to start from a known state. however, writing a counter can also be done while the pwm channel is enable d (counting). the effect is similar to writing the counter when the channel is disabled except that the new period is starte d immediately with the output set according to the polarity bit. note writing to the counter while the channe l is enabled can cau se an irregular pwm cycle to occur. the counter is cleared at the e nd of the effective period (see section 12.4.2.5, ?left aligned outputs , ? and section 12.4.2.6, ?center aligned outputs , ? for more details). table 12-11. pwm timer counter conditions counter clears (0x0000) coun ter counts counter stops when pwmcntx register written to any value when pwm channel is enabled (pwmex = 1). counts from last value in pwmcntx. when pwm channel is disabled (pwmex = 0) effective period ends chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 405 12.4.2.5 left aligned outputs the pwm timer provides the choice of two types of outputs, le ft aligned or center aligned outputs. they are selected with the caex bits in the pwmcae re gister. if the caex bit is cleared (caex = 0), the corresponding pwm output will be left aligned. in left aligned output mode, the 8- bit counter is configured as an up counter only. it compares to two registers, a duty register and a period regi ster as shown in the block diagram in figure 12-35 . when the pwm counter matches the duty regist er the output flip-flop changes stat e causing the pwm waveform to also change state. a match between the pwm counter and the period register resets the counter and the output flip-flop as shown in figure 12-35 as well as performing a load from the double buffer period and duty register to the associated registers as described in section 12.4.2.3, ?pwm period and duty.? the counter counts from 0 to the value in the period register ? 1. note changing the pwm output mode from le ft aligned output to center aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 12-36. pwm left aligned output waveform to calculate the output frequency in left aligned output mode for a partic ular channel, take the selected clock source frequency for the channel (a, b, sa, or sb) and divide it by the value in the period register for that channel. ? pwmx frequency = clock (a, b, sa, or sb) / pwmperx ? pwmx duty cycle (high time as a% of period): ? polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% ? polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% as an example of a left aligned output, consider the following case: clock source = bus clock, where bus clock = 10 mhz (100 ns period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 mhz/4 = 2.5 mhz pwmx period = 400 ns pwmx duty cycle = 3/4 *100% = 75% pwmdtyx period = pwmperx ppolx = 0 ppolx = 1 chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 406 freescale semiconductor shown below is the output waveform generated. figure 12-37. pwm left aligned output example waveform 12.4.2.6 center aligned outputs for center aligned output m ode selection, set the caex bit (caex = 1) in the pwmcae register and the corresponding pwm output wi ll be center aligned. the 8-bit counter operates as an up/ down counter in this m ode and is set to up whenever the counter is equal to 0x0000. the counter compares to two registers, a duty register and a period register as shown in the block diagram in figure 12-35 . when the pwm counter matches the duty register the output flip-flop changes state causing the pwm waveform to also ch ange state. a match between the pwm counter and the period register changes the counter directio n from an up-count to a down-count. when the pwm counter decrements and matches the duty register again, the output fl ip-flop changes state causing the pwm output to also change state. when the pwm count er decrements and reaches 0, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated regist ers is performed as described in section 12.4.2.3, ?pwm period and duty.? the counter counts from 0 up to th e value in the period register and then back down to 0. thus the effective period is pwmperx*2. note changing the pwm output mode from le ft aligned output to center aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 12-38. pwm center aligned output waveform e = 100 ns duty cycle = 75% period = 400 ns ppolx = 0 ppolx = 1 pwmdtyx pwmdtyx period = pwmperx*2 pwmperx pwmperx chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 407 to calculate the output frequency in center aligned output mode for a partic ular channel, take the selected clock source frequency for the channe l (a, b, sa, or sb) and divide it by twice the value in the period register for that channel. ? pwmx frequency = clock (a, b, sa, or sb) / (2*pwmperx) ? pwmx duty cycle (high time as a% of period): ? polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% ? polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% as an example of a center aligned output, consider the following case: clock source = bus clock, where bus clock = 10 mhz (100 ns period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 mhz/8 = 1.25 mhz pwmx period = 800 ns pwmx duty cycle = 3/4 *100% = 75% shown below is the output waveform generated. figure 12-39. pwm center aligned output example waveform 12.4.2.7 pwm 16-bit functions the pwm timer also has the option of generating 6-channels of 8-bits or 3-channels of 16-bits for greater pwm resolution}. this 16-bit channel option is achieved through the con catenation of two 8-bit channels. the pwmctl register contains thre e control bits, each of which is us ed to concatenate a pair of pwm channels into one 16-bit channel. ch annels 4 and 5 are concat enated with the con45 bit, channels 2 and 3 are concatenated with the con23 bit, and channe ls 0 and 1 are concatenated with the con01 bit. note change these bits only when both co rresponding channels are disabled. when channels 4 and 5 are concatenated, channel 4 registers become the high- order bytes of the double byte channel as shown in figure 12-40 . similarly, when channels 2 a nd 3 are concatenated, channel 2 registers become the high-order bytes of the double byt e channel. when channels 0 and 1 are concatenated, channel 0 registers become the high-or der bytes of the double byte channel. e = 100 ns e = 100 ns period = 800 ns duty cycle = 75% chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 408 freescale semiconductor figure 12-40. pwm 16-bit mode when using the 16-bit concatenated mode, the clock s ource is determined by th e low-order 8-bit channel clock select control bits. that is channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. the resulting pwm is output to the pins of the correspondi ng low-order 8-bit channel as also shown in figure 12-40 . the polarity of the resulting pwm output is controlled by the ppolx bit of the corresponding low-order 8-bit channel as well. after concatenated mode is enabled (conxx bits set in pwmctl register), enabling/disabling the corresponding 16-bit pwm channel is controlled by the low-order pwmex bi t. in this case, the high-order bytes pwmex bits have no effect and th eir corresponding pwm output is disabled. in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high-order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. either left aligned or center aligne d output mode can be used in con catenated mode and is controlled by the low-order caex bit. the hi gh-order caex bit has no effect. pwmcnt4 pwcnt5 pwm5 clock source 5 high low period/duty compare pwmcnt2 pwcnt3 pwm3 clock source 3 high low period/duty compare pwmcnt0 pwcnt1 pwm1 clock source 1 high low period/duty compare chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 409 table 12-12 is used to summarize which channels are used to set the various contro l bits when in 16-bit mode. 12.4.2.8 pwm boundary cases table 12-13 summarizes the boundary conditi ons for the pwm regardless of the output mode (left aligned or center aligned) a nd 8-bit (normal) or 16-bit (concatenation): 12.5 resets the reset state of each individua l bit is listed within the regi ster description section (see section 12.3, ?memory map and register definition , ? which details the registers a nd their bit-fields. all special functions or modes which are initiali zed during or just following reset are described within this section. ? the 8-bit up/down counter is configur ed as an up counter out of reset. ? all the channels are disabled and all the counters don?t count. 12.6 interrupts the pwm8b6cv1 module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (pwmie) is set. this bi t is the enable for the interrupt. the interrupt flag pwmif is set whenever the input level of the pwm5 channel changes while pwm5ena=1 or when pwmena is being asserted whil e the level at pwm5 is active. a description of the registers involved and aff ected due to this interrupt is explained in section 12.3.2.15, ?pwm shutdown register (pwmsdn).? table 12-12. 16-bit concatenation mode summary conxx pwmex ppolx pclkx caex pwmx output con45 pwme5 ppol5 pclk5 cae5 pwm5 con23 pwme3 ppol3 pclk3 cae3 pwm3 con01 pwme1 ppol1 pclk1 cae1 pwm1 table 12-13. pwm boundary cases pwmdtyx pwmperx ppo lx pwmx output 0x0000 (indicates no duty) >0x0000 1 always low 0x0000 (indicates no duty) >0x0000 0 always high xx 0x0000 1 (indicates no period) 1 counter = 0x0000 and does not count. 1 always high xx 0x0000 1 (indicates no period) 0 always low >= pwmperx xx 1 always high >= pwmperx xx 0 always low chapter 12 pulse-width modulator (pwm8b6cv1) mc9s12e256 data sheet, rev. 1.08 410 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 411 chapter 13 timer module (tim16b4cv1) 13.1 introduction the basic timer consists of a 16-bit, software-programmable c ounter driven by a seven-stage programmable prescaler. this timer can be used for many purposes, including input waveform me asurements while simultaneously generating an output waveform. pulse widths can vary from microseconds to many seconds. this timer contains 4 complete input capture/output compare ch annels ioc[7:4] and one pulse accumulator. the input capture functi on is used to detect a selected tr ansition edge and record the time. the output compare function is used for generating output si gnals or for timer soft ware delays. the 16-bit pulse accumulator is used to operate as a simple ev ent counter or a gated time accumulator. the pulse accumulator shares timer channel 7 when in event mode. a full access for the counter registers or the input capture/output compare regist ers should take place in one clock cycle. accessing high byte a nd low byte separately for all of these registers may not yield the same result as accessing them in one word. 13.1.1 features the tim16b4cv1 includes th ese distinctive features: ? four input capture/output compare channels ? clock prescaling ? 16-bit counter ? 16-bit pulse accumulator 13.1.2 modes of operation stop: timer is off because clocks are stopped. freeze: timer counter keep on running, unle ss tsfrz in tscr (0x0006) is set to 1. wait: counters keep on running, unless ts wai in tscr (0x0006) is set to 1. normal: timer counter keep on running, unle ss ten in tscr (0x0006) is cleared to 0. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 412 freescale semiconductor 13.1.3 block diagrams figure 13-1. tim16b4cv1 block diagram prescaler 16-bit counter 16-bit pulse accumulator ioc5 ioc4 ioc6 ioc7 pa input interrupt pa overflow interrupt timer overflow interrupt timer channel 4 interrupt timer channel 7 interrupt registers bus clock input capture output compare input capture output compare input capture output compare input capture output compare channel 4 channel 5 channel 6 channel 7 chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 413 figure 13-2. 16-bit pulse accumulator block diagram figure 13-3. interrupt flag setting figure 13-4. channel 7 output compare/pulse accumulator logic note for more information see the respec tive functional descriptions in section 13.4, ?functional description , ? of this document. edge detector intermodule bus pt7 m clock divide by 64 clock select clk0 clk1 4:1 mux timclk paclk paclk / 256 paclk / 65536 prescaled clock (pclk) (timer clock) interrupt mux (pamod) pacnt ptn edge 16-bit main timer tcn input set cnf interrupt detector capture register pulse accumulator pad om7 ol7 oc7m7 channel 7 output compare chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 414 freescale semiconductor 13.2 external signal description the tim16b4cv1 module has a to tal of four external pins. 13.2.1 ioc7 ? input capture and output compare channel 7 pin this pin serves as input capture or output compare fo r channel 7. this can also be configured as pulse accumulator input. 13.2.2 ioc6 ? input capture and output compare channel 6 pin this pin serves as input capture or output compare for channel 6. 13.2.3 ioc5 ? input capture and output compare channel 5 pin this pin serves as input capture or output compare for channel 5. 13.2.4 ioc4 ? input capture and output compare channel 4 pin this pin serves as input capture or output compare for channel 4. note for the description of interrupts see section 13.6, ?interrupts? . 13.3 memory map and register definition this section provides a detailed descri ption of all memory and registers. 13.3.1 module memory map the memory map for the tim16b4cv1 module is given below in table 13-1 . the address listed for each register is the address offset. the total address for e ach register is the sum of the base address for the tim16b4cv1 module and the addre ss offset for each register. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 415 table 13-1. tim16b4cv1 memory map address offset use access 0x0000 timer input capture/outp ut compare select (tios) r/w 0x0001 timer compare force register (cforc) r/w 1 1 always read 0x0000. 0x0002 output compare 7 mask register (oc7m) r/w 0x0003 output compare 7 da ta register (oc7d) r/w 0x0004 timer count register (tcnt(hi)) r/w 2 2 only writable in special modes (test_mode = 1). 0x0005 timer count register (tcnt(lo)) r/w 2 0x0006 timer system control register1 (tscr1) r/w 0x0007 timer toggle overflow register (ttov) r/w 0x0008 timer control register1 (tctl1) r/w 0x0009 reserved ? 3 3 write has no effect; return 0 on read 0x000a timer control register3 (tctl3) r/w 0x000b reserved ? 3 0x000c timer interrupt enable register (tie) r/w 0x000d timer system control register2 (tscr2) r/w 0x000e main timer interrupt flag1 (tflg1) r/w 0x000f main timer interrupt flag2 (tflg2) r/w 0x0010 - 0x0017 reserved ? 3 0x0018 timer input capture/output compare register4 (tc4(hi)) r/w 4 4 write to these registers have no meani ng or effect during input capture. 0x0019 timer input capture/output compare register 4 (tc4(lo)) r/w 4 0x001a timer input capture/output compare register 5 (tc5(hi)) r/w 4 0x001b timer input capture/output compare register 5 (tc5(lo)) r/w 4 0x001c timer input capture/output compare register 6 (tc6(hi)) r/w 4 0x001d timer input capture/output compare register 6 (tc6(lo)) r/w 4 0x001e timer input capture/output compare register 7 (tc7(hi)) r/w 4 0x001f timer input capture/output compare register 7 (tc7(lo)) r/w 4 0x0020 16-bit pulse accumulator control register (pactl) r/w 0x0021 pulse accumulator flag register (paflg) r/w 0x0022 pulse accumulator count register (pacnt(hi)) r/w 0x0023 pulse accumulator count register (pacnt(lo)) r/w 0x0024 ? 0x002c reserved ? 3 0x002d timer test register (timtst) r/w 2 0x002e ? 0x002f reserved ? 3 chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 416 freescale semiconductor 13.3.2 register descriptions this section consists of re gister descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. register name bit 7654321bit 0 0x0000 tios r ios7ios6ios5ios4ios3ios2ios1ios0 w 0x0001 cforc r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 0x0002 oc7m r oc7m7oc7m6oc7m5oc7m4oc7m3oc7m2oc7m1oc7m0 w 0x0003 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w 0x0004 tcnth r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w 0x0005 tcntl r tcnt7 tcnt6 tcnt5 tcnt4 t cnt3 tcnt2 tcnt1 tcnt0 w 0x0006 tscr2 r ten tswai tsfrz tffca 0000 w 0x0007 ttov r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w 0x0008 tctl1 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w 0x0009 reserved r00000000 w 0x000a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x000b reserved r00000000 w 0x000c tie r c7i c6i c5i c4i c3i c2i c1i c0i w = unimplemented or reserved figure 13-5. tim16b4cv1 register summary chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 417 0x000d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x000e tflg1 r c7f c6f c5f c4f c3f c2f c1f c0f w 0x000f tflg2 r tof 0000000 w 0x0010?0x0017 reserved r00000000 w 0x0018?0x001f tcxh?tcxl r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0020 pac t l r0 paen pamod pedge clk1 clk0 paovi pai w 0x0021 pa f l g r000000 paov f pa i f w 0x0022 pacnth r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w 0x0023 pacntl r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w 0x0024?0x002f reserved r w register name bit 7654321bit 0 = unimplemented or reserved figure 13-5. tim16b4cv1 register summary (continued) chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 418 freescale semiconductor 13.3.2.1 timer input capture/ou tput compare select (tios) read: anytime write: anytime 13.3.2.2 timer compare force register (cforc) read: anytime but will always re turn 0x0000 (1 state is transient) write: anytime 76543210 r ios7 ios6 ios5 ios4 0000 w reset00000000 = unimplemented or reserved figure 13-6. timer input capture/output compare select (tios) table 13-2. tios field descriptions field description 7:4 ios[7:4] input capture or output compare channel configuration 0 the corresponding channel acts as an input capture. 1 the corresponding channel acts as an output compare. 76543210 r00000000 w foc7 foc6 foc5 foc4 reset00000000 = unimplemented or reserved figure 13-7. timer compare force register (cforc) table 13-3. cforc field descriptions field description 7:4 foc[7:4] force output compare action for channel 7:4 ? a write to this register with the corresponding data bit(s) set causes the action which is programmed for output comp are ?x? to occur immediately. the action taken is the same as if a successful comparison had just taken place with the tcx register except the interrupt flag does not get set. note: a successful channel 7 output compare overrides any channel 6:4 compares. if forced output compare on any channel occurs at the same time as the successfu l output compare then forc ed output compare action will take precedence and interrupt flag won?t get set. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 419 13.3.2.3 output compare 7 mask register (oc7m) read: anytime write: anytime 13.3.2.4 output compare 7 data register (oc7d) read: anytime write: anytime 76543210 r oc7m7 oc7m6 oc7m5 oc7m4 0000 w reset00000000 = unimplemented or reserved figure 13-8. output compare 7 mask register (oc7m) table 13-4. oc7m field descriptions field description 7:4 oc7m[7:4] output compare 7 mask ? setting the oc7mx (x ranges from 4 to 6) will set the corresponding port to be an output port when the corresponding tiosx (x ranges from 4 to 6) bit is set to be an output compare. note: a successful channel 7 output com pare overrides any channel 6:4 compares. for each oc7m bit that is set, the output compare action reflects the corresponding oc7d bit. 76543210 r oc7d7 oc7d6 oc7d5 oc7d4 0000 w reset00000000 = unimplemented or reserved figure 13-9. output compare 7 data register (oc7d) table 13-5. oc7d field descriptions field description 7:4 oc7d[7:4] output compare 7 data ? a channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 420 freescale semiconductor 13.3.2.5 timer count register (tcnt) the 16-bit main timer is an up counter. a full access for the counter register should take place in one clock cycl e. a separate read/write for high byte and low byte will give a different result than accessing them as a word. read: anytime write: has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). the period of the first count after a write to the tcnt regi sters may be a different size because the write is not synchronized with the prescaler clock. 15 14 13 12 11 10 9 9 r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w reset00000000 figure 13-10. timer count register high (tcnth) 76543210 r tcnt7 tcnt6 tcnt5 tcnt4 t cnt3 tcnt2 tcnt1 tcnt0 w reset00000000 figure 13-11. timer count register low (tcntl) chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 421 13.3.2.6 timer system cont rol register 1 (tscr1) read: anytime write: anytime 76543210 r ten tswai tsfrz tffca 0000 w reset00000000 = unimplemented or reserved figure 13-12. timer system control register 1 (tscr2) table 13-6. tscr1 field descriptions field description 7 ten timer enable 0 disables the main timer, including the counter. can be used for reducing power consumption. 1 allows the timer to function normally. if for any reason the timer is not active, there is no 64 clock for the pulse accumulator because the 64 is generated by the timer prescaler. 6 tswai timer module stops while in wait 0 allows the timer module to continue running during wait. 1 disables the timer module when the mcu is in the wa it mode. timer interrupts cannot be used to get the mcu out of wait. tswai also affects pulse accumulator. 5 tsfrz timer stops while in freeze mode 0 allows the timer counter to continue running while in freeze mode. 1 disables the timer counter whenever the mcu is in freeze mode. this is useful for emulation. tsfrz does not stop the pulse accumulator. 4 tffca timer fast flag clear all 0 allows the timer flag clearing to function normally. 1 for tflg1(0x000e), a read from an input capture or a write to the output com pare channel (0x0010?0x001f) causes the corresponding channel flag, cnf, to be cleared. for tflg2 (0x000f), any access to the tcnt register (0x0004, 0x0005) clears the tof flag. any a ccess to the pacnt registers (0x0022, 0x0023) clears the paovf and paif flags in the paflg register (0x0021 ). this has the advantage of eliminating software overhead in a separate clear sequence. extra care is required to avoid accidental flag clearing due to unintended accesses. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 422 freescale semiconductor 13.3.2.7 timer toggle on overflow register 1 (ttov) read: anytime write: anytime 13.3.2.8 timer control register 1 (tctl1) read: anytime write: anytime 76543210 r tov7 tov6 tov5 tov4 0000 w reset00000000 = unimplemented or reserved figure 13-13. timer toggle on overflow register 1 (ttov) table 13-7. ttov field descriptions field description 7:4 tov[7:4] toggle on overflow bits ? tovx toggles output compare pin on overfl ow. this feature only takes effect when in output compare mode. when set, it takes precedence ov er forced output compare but not channel 7 override events. 0 toggle output compare pin on overflow feature disabled. 1 toggle output compare pin on overflow feature enabled. 76543210 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w reset00000000 figure 13-14. timer control register 1 (tctl1) table 13-8. tctl1/tctl2 field descriptions field description 7:4 omx output mode ? these four pairs of control bits are encoded to specify the output action to be taken as a result of a successful ocx compare. when either omx or ol x is 1, the pin associated with ocx becomes an output tied to ocx. note: to enable output action by omx bits on timer po rt, the corresponding bit in oc7m should be cleared. 7:4 olx output level ? these four pairs of control bits are encoded to specify the output action to be taken as a result of a successful ocx compare. when either omx or ol x is 1, the pin associated with ocx becomes an output tied to ocx. note: to enable output action by olx bits on timer port, the corresponding bit in oc7m should be cleared. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 423 to operate the 16-bit pulse accumulator independen tly of input capture or output compare 7 and 4 respectively the user must set the corresponding bi ts iosx = 1, omx = 0 a nd olx = 0. oc7m7 in the oc7m register must also be cleared. 13.3.2.9 timer control register 3 (tctl3) read: anytime write: anytime. table 13-9. compare result output action omx olx action 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to zero 1 1 set ocx output line to one 76543210 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w reset00000000 figure 13-15. timer control register 3 (tctl3) table 13-10. tctl3/tctl4 field descriptions field description 7:0 edgnb edgna input capture edge control ? these eight pairs of control bits conf igure the input capture edge detector circuits. table 13-11. edge detector circuit configuration edgnb edgna configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling) chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 424 freescale semiconductor 13.3.2.10 timer interrupt enable register (tie) read: anytime write: anytime. 13.3.2.11 timer system cont rol register 2 (tscr2) read: anytime write: anytime. 76543210 r c7i c6i c5i c4i 0000 w reset00000000 = unimplemented or reserved figure 13-16. timer interrupt enable register (tie) table 13-12. tie field descriptions field description 7:4 c7i:c0i input capture/output compare ?x? interrupt enable ? the bits in tie correspond bit-for-bit with the bits in the tflg1 status register. if cleared, the corresponding flag is disabled from causing a hardware interrupt. if set, the corresponding flag is enabled to cause a interrupt. 76543210 r toi 000 tcre pr2 pr1 pr0 w reset00000000 = unimplemented or reserved figure 13-17. timer system control register 2 (tscr2) table 13-13. tscr2 field descriptions field description 7 toi timer overflow in terrupt enable 0 interrupt inhibited. 1 hardware interrupt requested when tof flag set. 3 tcre timer counter reset enable ? this bit allows the timer counter to be reset by a successful output compare 7 event. this mode of operation is similar to an up-counting modulus counter. 0 counter reset inhibited and counter free runs. 1 counter reset by a successful output compare 7. if tc7 = 0x0000 and tcre = 1, tcnt will stay at 0x0000 continuously. if tc7 = 0xffff and tcre = 1, tof will never be set when tcnt is reset from 0xffff to 0x0000. 2 pr[2:0] timer prescaler select ? these three bits select the frequency of the timer prescaler clock derived from the bus clock as shown in table 13-14 . chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 425 note the newly selected prescale factor wi ll not take effect until the next synchronized edge where all pres cale counter stages equal zero. 13.3.2.12 main timer interrupt flag 1 (tflg1) read: anytime write: used in the clearing mechanism (set bits caus e corresponding bits to be cl eared). writing a zero will not affect current status of the bit. table 13-14. timer clock selection pr2 pr1 pr0 timer clock 0 0 0 bus clock / 1 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128 76543210 r c7f c6f c5f c4f 0000 w reset00000000 = unimplemented or reserved figure 13-18. main timer interrupt flag 1 (tflg1) table 13-15. tflg1 field descriptions field description 7:4 c[7:4]f input capture/output compare channel ?x? flag ? these flags are set when an input capture or output compare event occurs. clear a channel flag by writing one to it. when tffca bit in tscr register is se t, a read from an input capture or a write into an output compare channel (0x0010?0x001f) will cause the corresponding channel flag cxf to be cleared. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 426 freescale semiconductor 13.3.2.13 main timer interrupt flag 2 (tflg2) tflg2 indicates when interr upt conditions have o ccurred. to clear a bit in the flag register, write the bit to one. read: anytime write: used in clearing mechanism (set bi ts cause corresponding bits to be cleared). any access to tcnt will clear tflg2 register if the tffca bi t in tscr register is set. 76543210 r tof 0000000 w reset00000000 unimplemented or reserved figure 13-19. main timer interrupt flag 2 (tflg2) table 13-16. tflg2 field descriptions field description 7 tof timer overflow flag ? set when 16-bit free-running timer overflows from 0xffff to 0x0000. this bit is cleared automatically by a write to the tflg 2 register with bit 7 set. (see also tcre control bit explanation.) chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 427 13.3.2.14 timer input capture/output compare registers high and low 4?7 (tcxh and tcxl) depending on the tios bit for the co rresponding channel, these registers ar e used to latch the value of the free-running counter when a defined transition is sensed by the corres ponding input capture edge detector or to trigger an output action for output compare. read: anytime write: anytime for output compare function.writes to these registers have no me aning or effect during input capture. all timer input capture/out put compare registers are reset to 0x0000. note read/write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. 15 14 11 12 11 10 9 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset00000000 figure 13-20. timer input capture/output compare register x high (tcxh) 76543210 r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000 figure 13-21. timer input capture/out put compare register x low (tcxl) chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 428 freescale semiconductor 13.3.2.15 16-bit pulse accumulator control register (pactl) when paen is set, the pact is enabled.t he pact shares the input pin with ioc7. read: any time write: any time 76543210 r0 paen pamod pedge clk1 clk0 paovi pai w reset00000000 unimplemented or reserved figure 13-22. 16-bit pulse accumulator control register (pactl) table 13-17. pactl field descriptions field description 6 paen pulse accumulator system enable ? paen is independent from ten. with timer disabled, the pulse accumulator can function unless pulse accumulator is disabled. 0 16-bit pulse accumulator system disabled. 1 pulse accumulator system enabled. 5 pa m o d pulse accumulator mode ? this bit is active only when the pulse accumulator is enabled (paen = 1). see ta b l e 1 3 - 1 8 . 0 event counter mode. 1 gated time accumulation mode. 4 pedge pulse accumulator edge control ? this bit is active only when the pulse accumulator is enabled (paen = 1). for pamod bit = 0 (event counter mode). see table 13-18 . 0 falling edges on ioc7 pin cause the count to be incremented. 1 rising edges on ioc7 pin cause the count to be incremented. for pamod bit = 1 (gated time accumulation mode). 0 ioc7 input pin high enables m (bus clock) divided by 64 clock to pulse accumulator and the trailing falling edge on ioc7 sets the paif flag. 1 ioc7 input pin low enables m (bus clock) divided by 64 clock to pulse accumulator and the trailing rising edge on ioc7 sets the paif flag. 3:2 clk[1:0] clock select bits ? refer to table 13-19 . 1 paov i pulse accumulator overflow interrupt enable 0 interrupt inhibited. 1 interrupt requested if paovf is set. 0 pa i pulse accumulator input interrupt enable 0 interrupt inhibited. 1 interrupt requested if paif is set. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 429 note if the timer is not active (ten = 0 in tscr), there is no divide-by-64 because the 64 clock is generated by the timer prescaler. for the description of paclk please refer figure 13-22 . if the pulse accumulator is disabled (paen = 0), the pr escaler clock from the timer is always used as an input clock to the timer counter. the change from one selected clock to the other happens immediately after these bits are written. table 13-18. pin action pamod pedge pin action 0 0 falling edge 0 1 rising edge 1 0 div. by 64 clock enabled with pin high level 1 1 div. by 64 clock enabled with pin low level table 13-19. timer clock selection clk1 clk0 timer clock 0 0 use timer prescaler clock as timer counter clock 0 1 use paclk as input to timer counter clock 1 0 use paclk/256 as timer counter clock frequency 1 1 use paclk/65536 as timer counter clock frequency chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 430 freescale semiconductor 13.3.2.16 pulse accumulator flag register (paflg) read: anytime write: anytime when the tffca bit in the tscr regist er is set, any access to the pacnt register w ill clear all the flags in the paflg register. 76543210 r000000 paov f pa i f w reset00000000 unimplemented or reserved figure 13-23. pulse accumulator flag register (paflg) table 13-20. paflg field descriptions field description 1 paov f pulse accumulator overflow flag ? set when the 16-bit pulse accumulato r overflows from 0xffff to 0x0000. this bit is cleared automatically by a wr ite to the paflg register with bit 1 set. 0 pa i f pulse accumulator input edge flag ? set when the selected edge is detected at the ioc7 input pin.in event mode the event edge triggers paif and in gated time accu mulation mode the trailing edge of the gate signal at the ioc7 input pin triggers paif. this bit is cleared by a write to the paflg register with bit 0 set. any access to the pacnt register will clear all the flags in this register when tffca bit in register tscr(0x0006) is set. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 431 13.3.2.17 pulse accumulators count registers (pacnt) read: anytime write: anytime these registers contain the numbe r of active input edges on its i nput pin since the last reset. when pacnt overflows from 0xffff to 0x0000, the inte rrupt flag paovf in paflg (0x0021) is set. full count register access should take place in one clock cycle. a separa te read/write for high byte and low byte will give a different result than accessing them as a word. note reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulato r input pin may mi ss the last count because the input has to be synchr onized with the bus clock first. 15 14 13 12 11 10 9 0 r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w reset00000000 figure 13-24. pulse accumulator count register high (pacnth) 76543210 r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w reset00000000 figure 13-25. pulse accumulator count register low (pacntl) chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 432 freescale semiconductor 13.4 functional description this section provides a complete functional descripti on of the timer tim16b4cv1 block. please refer to the detailed timer block diagram in figure 13-26 as necessary. figure 13-26. detailed timer block diagram prescaler channel 4 ioc4 pin 16-bit counter logic pr[2:1:0] divide-by-64 tc4 edge detect pacnt(hi):pacnt(lo) paovf pedge paovi pamod pae 16-bit comparator tcnt(hi):tcnt(lo) 16-bit counter interrupt logic tof toi c4f edge detect cxf channel7 tc7 16-bit comparator c7f ioc7 pin logic edge detect om:ol4 tov4 om:ol7 tov7 edg7a edg7b edg4b tcre paif clear counter paif pai interrupt logic cxi interrupt request paovf ch. 7 compare ch.7 capture mux clk[1:0] paclk paclk/256 paclk/65536 ioc4 pin ioc7 pin paclk paclk/256 paclk/65536 te ch. 4 compare ch. 4 capture pa input edg4a channel 7 output compare ioc4 ioc7 bus clock bus clock paovf paovi tof c4f c7f chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 433 13.4.1 prescaler the prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. the prescaler select bi ts, pr[2:0], select the prescaler divisor. pr[2:0] are in ti mer system control register 2 (tscr2). 13.4.2 input capture clearing the i/o (input/output) select bit, iosx, configures channel x as an input capture channel. the input capture function captures the time at which an ex ternal event occurs. when an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, tcx. the minimum pulse width for the input captur e input is greater than two bus clocks. an input capture on channel x sets the cxf flag. the cxi bit enables the cxf flag to generate interrupt requests. 13.4.3 output compare setting the i/o select bit, iosx, configures channel x as an output compare channel. the output compare function can generate a periodic pul se with a programmable polarity, duration, and frequency. when the timer counter reaches the value in th e channel registers of an output co mpare channel, the timer can set, clear, or toggle the channel pin. an output compar e on channel x sets the cxf flag. the cxi bit enables the cxf flag to generate interrupt requests. the output mode and level bits, omx and olx, select set, clear, toggle on output compare. clearing both omx and olx disconnects the pi n from the output logic. setting a force output compare bi t, focx, causes an output compar e on channel x. a forced output compare does not set the channel flag. a successful output compare on channel 7 overrid es output compares on all other output compare channels. the output compare 7 mask register masks the bits in the out put compare 7 data register. the timer counter reset enable bit, tcre, enables cha nnel 7 output compares to reset the timer counter. a channel 7 output compare can reset the timer counter ev en if the ioc7 pin is being used as the pulse accumulator input. writing to the timer port bit of an output compare pi n does not affect the pin st ate. the value written is stored in an internal latch. when the pin becomes available for gene ral-purpose output, the last value written to the bit appears at the pin. 13.4.4 pulse accumulator the pulse accumulator (pacnt) is a 16-bit counter that can opera te in two modes: event counter mode ? counting edges of selected polarity on the pulse accum ulator input pin, pai. gated time accumulation mode ? c ounting pulses from a divide-by-64 clock. the pamod bit selects the mode of operation. the minimum pulse width for the pai i nput is greater than two bus clocks. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 434 freescale semiconductor 13.4.5 event counter mode clearing the pamod bit configures the pacnt for event counter operat ion. an active edge on the ioc7 pin increments the pulse accumula tor counter. the pedge bit selects falling edges or rising edges to increment the count. note the pacnt input and timer channel 7 use the same pin ioc7. to use the ioc7, disconnect it from the output l ogic by clearing the channel 7 output mode and output level b its, om7 and ol7. also cl ear the channel 7 output compare 7 mask bit, oc7m7. the pulse accumulator counter regi ster reflect the number of active input edges on the pacnt input pin since the last reset. the paovf bit is set when the accumulator roll s over from 0xffff to 0x0000. the pulse accumulator overflow interrupt enable bit, paovi, enables th e paovf flag to generate interrupt requests. note the pulse accumulator counter can op erate in event counter mode even when the timer enable bit, ten, is clear. 13.4.6 gated time accumulation mode setting the pamod bit configures the pulse accumu lator for gated time accumu lation operation. an active level on the pacnt input pin enable s a divided-by-64 clock to drive th e pulse accumulator. the pedge bit selects low levels or high levels to enable the divided-by-64 clock. the trailing edge of the active level at the ioc7 pin sets the paif. the pai bit enables the paif flag to generate interrupt requests. the pulse accumulator counter regi ster reflect the number of pulses from the divided-by-64 clock since the last reset. note the timer prescaler generates the divi ded-by-64 clock. if the timer is not active, there is no divided-by-64 clock. 13.5 resets the reset state of each indi vidual bit is listed within section 13.3, ?memory map and register definition? which details the register s and their bit fields. 13.6 interrupts this section describes interrupts or iginated by the tim16b4cv1 block. table 13-21 lists the interrupts generated by the tim16b4cv1 to communicate with the mcu. chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 435 the tim16b4cv1 uses a total of 7 interrupt vectors. the interrupt vector offsets and interrupt numbers are chip dependent. 13.6.1 channel [7:4] interrupt (c[7:4]f) this active high outputs will be assert ed by the module to request a timer channel 7 ? 4 interrupt to be serviced by the system controller. 13.6.2 pulse accumulator input interrupt (paovi) this active high output will be asserted by the module to request a timer pulse accumula tor input interrupt to be serviced by the system controller. 13.6.3 pulse accumulator ov erflow interrupt (paovf) this active high output will be asserted by the m odule to request a timer pulse accumulator overflow interrupt to be serviced by the system controller. 13.6.4 timer overflow interrupt (tof) this active high output will be asse rted by the module to reque st a timer overflow inte rrupt to be serviced by the system controller. table 13-21. tim16b8cv1 interrupts interrupt offset 1 1 chip dependent. vector 1 priority 1 source description c[7:4]f ? ? ? timer channel 7?4 active high timer channel interrupts 7?4 paovi ? ? ? pulse accumulator input active high pulse accumulator input interrupt paovf ? ? ? pulse accumulator overflow pulse accumulator overflow interrupt tof ? ? ? timer overflow timer overflow interrupt chapter 13 timer module (tim16b4cv1) mc9s12e256 data sheet, rev. 1.08 436 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 437 chapter 14 dual output voltage regulator (vreg3v3v2) 14.1 introduction the vreg is a dual output voltage regulator providing two separate 2.5 v (typical) supplies differing in the amount of current that can be sourced. the regul ator input voltage range is from 3.3 v up to 5 v (typical). 14.1.1 features the block vreg includes these distinctive features: ? two parallel, linear voltage regulators ? bandgap reference ? low-voltage detect (lvd) with low-voltage interrupt (lvi) ? power-on reset (por) ? low-voltage reset (lvr) 14.1.2 modes of operation there are three modes vreg can operate in: ? full-performance mode (fpm) (mcu is not in stop mode) the regulator is active, providing the nominal supply voltage of 2.5 v with full current sourcing capability at both outputs. features lvd (low-volta ge detect), lvr (low- voltage reset), and por (power-on reset) are available. ? reduced-power mode (rpm ) (mcu is in stop mode) the purpose is to reduce power c onsumption of the device. the ou tput voltage may degrade to a lower value than in full-performance mode, a dditionally the current sourcing capability is substantially reduced. only the por is availa ble in this mode, lvd and lvr are disabled. ? shutdown mode controlled by v regen (see chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for connectivity of v regen ). this mode is characterized by minimum power consumption. the regulator outputs are in a high impedance state, only the por feature is available, lvd and lvr are disabled. this mode must be used to disable the chip inte rnal regulator vreg, i.e. , to bypass the vreg to use external supplies. chapter 14 dual output voltage regulator (vreg3v3v2) mc9s12e256 data sheet, rev. 1.08 438 freescale semiconductor 14.1.3 block diagram figure 14-1 shows the function principle of vreg by means of a block diagram. the regulator core reg consists of two parallel sub- blocks, reg1 and reg2, providing two independent output voltages. figure 14-1. vreg3v3 block diagram lv r lv d por v ddr v dd lvi por lvr ctrl v ss v ddpll v sspll v regen reg reg2 reg1 pin v dda v ssa reg: regulator core lvd: low voltage detect ctrl: regulator control lvr: low voltage reset por: power-on reset chapter 14 dual output voltage regulator (vreg3v3v2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 439 14.2 external signal description due to the nature of vreg being a voltage regulat or providing the chip inte rnal power supply voltages most signals are power supply signals connected to pads. table 14-1 shows all signals of vreg associated with pins. note check chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for connectivity of the signals. 14.2.1 v ddr ? regulator power input signal v ddr is the power input of vreg. all currents sourced into the re gulator loads flow through this pin. a chip external decoupling capaci tor (100 nf...220 nf, x7r ceramic) between v ddr and v ssr can smoothen ripple on v ddr . for entering shutdown mode, pin v ddr should also be tied to ground on devices without a v regen pin. 14.2.2 v dda , v ssa ? regulator reference supply signals v dda /v ssa which are supposed to be relatively quiet are used to supply the analog parts of the regulator. internal precisi on reference circuits are supplied from th ese signals. a chip external decoupling capacitor (100 nf...220 nf, x7r ceramic) between v dda and v ssa can further improve the quality of this supply. table 14-1. vreg ? signal properties name port function reset state pull up v ddr ? vreg power input (positive supply) ? ? v dda ? vreg quiet input (positive supply) ? ? v ssa ? vreg quiet input (ground) ? ? v dd ? vreg primary output (positive supply) ? ? v ss ? vreg primary output (ground) ? ? v ddpll ? vreg secondary output (positive supply) ? ? v sspll ? vreg secondary output (ground) ? ? v regen (optional) ? vreg (optional) regulator enable ? ? chapter 14 dual output voltage regulator (vreg3v3v2) mc9s12e256 data sheet, rev. 1.08 440 freescale semiconductor 14.2.3 v dd , v ss ? regulator output1 (core logic) signals v dd /v ss are the primary outputs of vreg that provid e the power supply for the core logic. these signals are connected to device pins to allow ex ternal decoupling capacitors (100 nf...220 nf, x7r ceramic). in shutdown mode an external supply at v dd /v ss can replace the voltage regulator. 14.2.4 v ddpll , v sspll ? regulator output2 (pll) signals v ddpll /v sspll are the secondary outputs of vreg th at provide the power supply for the pll and oscillator. these signals are c onnected to device pins to allow external decoupling capacitors (100 nf...220 nf, x7r ceramic). in shutdown mode an external supply at v ddpll /v sspll can replace the voltage regulator. 14.2.5 v regen ? optional regulator enable this optional signal is used to shutdown vreg. in that case v dd /v ss and v ddpll /v sspll must be provided externally. shutdown mode is entered with v regen being low. if v regen is high, the vreg is either in full-performance mode or in reduced-power mode. for the connectivity of v regen see chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? . note switching from fpm or rpm to shutdown of vreg and vice versa is not supported while th e mcu is powered. 14.3 memory map and register definition this subsection provides a detailed descrip tion of all registers accessible in vreg. 14.3.1 module memory map figure 14-2 provides an overview of all used registers. table 14-2. vreg memory map address offset use access 0x0000 vreg control register (vregctrl) r/w chapter 14 dual output voltage regulator (vreg3v3v2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 441 14.3.2 register descriptions the following paragraphs describe, in address order, all the vreg registers and their individual bits. 14.3.2.1 vreg ? control register (vregctrl) the vregctrl register allows to se parately enable features of vreg. note on entering the reduced-power mode the lvif is not cleared by the vreg. 14.4 functional description block vreg is a voltage re gulator as depicted in figure 14-1 . the regulator functional elements are the regulator core (reg), a low-voltage detect module (lvd), a power-on re set module (por) and a low-voltage reset module (lvr). there is also the regulator control block (ctr l) which represents the interface to the digital core logic but al so manages the operating modes of vreg. 14.4.1 reg ? regulator core vreg, respectively its regulator co re has two parallel, independent regulation loops (reg1 and reg2) that differ only in the amount of cu rrent that can be sourced to the c onnected loads. therefore, only reg1 providing the supply at v dd /v ss is explained. the principle is also valid for reg2. 76543210 r00000lvds lvie lvif w reset00000000 = unimplemented or reserved figure 14-2. vreg3v3 ? control register (vregctrl) table 14-3. vregctrl field descriptions field description 2 lv d s low-voltage detect status bit ? this read-only status bit reflects the input voltage. writes have no effect. 0 input voltage v dda is above level v lv i d or rpm or shutdown mode. 1 input voltage v dda is below level v lv i a and fpm. 1 lv i e low-voltage interrupt enable bit 0 interrupt request is disabled. 1 interrupt will be requested whenever lvif is set. 0 lv i f low-voltage interrupt flag ? lvif is set to 1 when lvds status bit changes. this flag can only be cleared by writing a 1. writing a 0 has no effect. if enabled (lvie = 1), lvif causes an interrupt request. 0 no change in lvds bit. 1 lvds bit has changed. chapter 14 dual output voltage regulator (vreg3v3v2) mc9s12e256 data sheet, rev. 1.08 442 freescale semiconductor the regulator is a linear series regulator with a bandgap reference in its fu ll-performance mode and a voltage clamp in reduced-power mode. a ll load currents flow from input v ddr to v ss or v sspll , the reference circuits are connected to v dda and v ssa . 14.4.2 full-performance mode in full-performance mode, a fra ction of the output voltage (v dd ) and the bandgap reference voltage are fed to an operational amplifie r. the amplified input voltage difference controls the gate of an output driver which basically is a large nmos tr ansistor connected to the output. 14.4.3 reduced-power mode in reduced-power mode, the driver gate is connected to a buffere d fraction of the input voltage (v ddr ). the operational amplifier and the bandgap ar e disabled to reduce power consumption. 14.4.4 lvd ? low-voltage detect sub-block lvd is responsible for generating the low- voltage interrupt (lvi). lvd monitors the input voltage (v dda ?v ssa ) and continuously updates the st atus flag lvds. interrupt fl ag lvif is set whenever status flag lvds changes its value. the lvd is avai lable in fpm and is inactiv e in reduced-power mode and shutdown mode. 14.4.5 por ? power-on reset this functional block monitors output v dd . if v dd is below v pord , signal por is high, if it exceeds v pord , the signal goes low. the transition to lo w forces the cpu in the power-on sequence. due to its role during chip power-up this module must be active in all operating modes of vreg. 14.4.6 lvr ? low-voltage reset block lvr monitors the primary output voltage v dd . if it drops below the assertion level (v lvra ) signal lvr asserts and when rising above the deassertion level (v lvrd ) signal lvr negates again. the lvr function is available only in full-performance mode. 14.4.7 ctrl ? re gulator control this part contains the register bl ock of vreg and further digital f unctionality needed to control the operating modes. ctrl also represents th e interface to the digital core logic. chapter 14 dual output voltage regulator (vreg3v3v2) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 443 14.5 resets this subsection describes how vreg controls the re set of the mcu.the reset values of registers and signals are provided in section 14.3, ?memory map and register definition? . possible reset sources are listed in table 14-4 . 14.5.1 power-on reset during chip power-up the digital core ma y not work if its supply voltage v dd is below the por deassertion level (v pord ). therefore, signal por which forces the other blocks of the device into reset is kept high until v dd exceeds v pord . then por becomes low and the reset generator of the device continues the start-up sequence. the power-on reset is active in all operation modes of vreg. 14.5.2 low-voltage reset for details on low-voltage reset see section 14.4.6, ?lvr ? low-voltage reset? . 14.6 interrupts this subsection describes all interrupts originated by vreg. the interrupt vectors request ed by vreg are listed in table 14-5 . vector addresses and interrupt priorities are defined at mcu level. 14.6.1 lvi ? low-voltage interrupt in fpm vreg monitors the input voltage v dda . whenever v dda drops below level v lvia the status bit lvds is set to 1. vice versa, lvds is reset to 0 when v dda rises above level v lvid . an interrupt, indicated by flag lvif = 1, is triggered by any change of the status bit lvds if interrupt enable bit lvie = 1. note on entering the reduced-power mode, th e lvif is not cleared by the vreg. table 14-4. vreg ? reset sources reset source local enable power-on reset always active low-voltage reset available only in full-performance mode table 14-5. vreg ? interrupt vectors interrupt source local enable low voltage interrupt (lvi) lvie = 1; available only in full-performance mode chapter 14 dual output voltage regulator (vreg3v3v2) mc9s12e256 data sheet, rev. 1.08 444 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 445 chapter 15 background debug module (bdmv4) 15.1 introduction this section describes th e functionality of the background debug module (bdm) sub-bl ock of the hcs12 core platform. a block diagram of the bdm is shown in figure 15-1 . figure 15-1. bdm block diagram the background debug module (bdm) s ub-block is a single-wire, bac kground debug system implemented in on-chip hardware for minimal cpu intervention. all interfacing with the bdm is done via the bkgd pin. bdmv4 has enhanced capability for maintaining s ynchronization between the target and host while allowing more flexibility in clock ra tes. this includes a sync signal to show the clock rate and a handshake signal to indicate when an operation is complete. the sy stem is backwards compatible with older external interfaces. enbdm sdv 16-bit shift register bkgd clocks data address host system bus interface and control logic instruction decode and execution standard bdm firmware lookup table clksw bdmact entag trace chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 446 freescale semiconductor 15.1.1 features ? single-wire communication wi th host development system ? bdmv4 (and bdm2): enhanced capability for allowing more flexibility in clock rates ? bdmv4: sync command to determine communication rate ? bdmv4: go_until command ? bdmv4: hardware handshake prot ocol to increase the performan ce of the serial communication ? active out of reset in special single-chip mode ? nine hardware commands using free cycles, if available, for minimal cpu intervention ? hardware commands not requiring active bdm ? 15 firmware commands execute from the standard bdm firmware lookup table ? instruction tagging capability ? software control of bdm operation during wait mode ? software selectable clocks ? when secured, hardware commands are allowed to access the register space in special single-chip mode, if the flash and eeprom erase tests fail. 15.1.2 modes of operation bdm is available in all operating modes but must be enabled before firmware commands are executed. some system peripherals may have a control bit wh ich allows suspending the peripheral function during background debug mode. 15.1.2.1 regular run modes all of these operations refer to the part in run mode . the bdm does not provide controls to conserve power during run mode. ? normal operation general operation of the bdm is available and operates the same in all normal modes. ? special single-chip mode in special single-chip mode, background operation is enabled and active out of reset. this allows programming a system with blank memory. ? special peripheral mode bdm is enabled and active immediately out of rese t. bdm can be disabled by clearing the bdmact bit in the bd m status (bdmsts) register. the bdm serial system should not be used in special peripheral mode. ? emulation modes general operation of the bdm is available and operates the same as in normal modes. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 447 15.1.2.2 secure mode operation if the part is in secure mode, the operation of the bdm is reduced to a sm all subset of its regular run mode operation. secure operation prevents access to fl ash or eeprom other than allowing erasure. 15.2 external signal description a single-wire interface pin is used to communicate with the bdm system. two additional pins are used for instruction tagging. these pins ar e part of the multiplexed external bus interface (mebi) sub-block and all interfacing between the mebi and bdm is done within the core in terface boundary. functional descriptions of the pins are provided below for completeness. ? bkgd ? background interface pin ? taghi ? high byte instruction tagging pin ?taglo ? low byte instruction tagging pin ? bkgd and taghi share the same pin. ?taglo and lstrb share the same pin. note generally these pins are shared as described, but it is best to check chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? to make certain. all mcus at the time of this writing have followed this pin sharing scheme. 15.2.1 bkgd ? background interface pin debugging control logic communicates with external devices serially via the single-wire background interface pin (bkgd). during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the de dicated serial interface pin for the background debug mode. 15.2.2 taghi ? high byte instruction tagging pin this pin is used to tag th e high byte of an instruction. when instru ction tagging is on, a l ogic 0 at the falling edge of the external clock (eclk) ta gs the high half of the instruction wo rd being read into the instruction queue. 15.2.3 taglo ? low byte instruction tagging pin this pin is used to tag the low byte of an instruct ion. when instruction tagging is on and low strobe is enabled, a logic 0 at the falling edge of the external clock (eclk) tags th e low half of the instruction word being read into the instruction queue. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 448 freescale semiconductor 15.3 memory map and register definition a summary of the registers associ ated with the bdm is shown in figure 15-2 . registers are accessed by host-driven communications to the bdm hardwa re using read_bd and write_bd commands. detailed descriptions of the registers and associat ed bits are given in the subsections that follow. 15.3.1 module memory map table 15-1. bdm memory map register address use access reserved ? bdm status register (bdmsts) r/w reserved ? bdm ccr holding register (bdmccr) r/w 7 bdm internal register position (bdminr) r 8? reserved ? chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 449 15.3.2 register descriptions register name bit 7654321bit 0 reservedrxxxxxx0 0 w bdmsts r enbdm bdmact entag sdv trace clksw unsec 0 w reserved rxxxxxxxx w reserved rxxxxxxxx w reservedrxxxxxxxx w reservedrxxxxxxxx w bdmccr r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w bdminr r 0 reg14 reg13 reg12 reg11 0 0 0 w reservedr00000000 w reserved r00000000 w reserved rxxxxxxxx w reserved rxxxxxxxx w = unimplemented, reserved = implemented (do not alter) x = indeterminate 0 = always read zero figure 15-2. bdm register summary chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 450 freescale semiconductor 15.3.2.1 bdm status register (bdmsts) read: all modes th rough bdm operation write: all modes but subject to the following: ? bdmact can only be set by bdm hardware upon entr y into bdm. it can only be cleared by the standard bdm firmware lookup ta ble upon exit from bdm active mode. ? clksw can only be written via bdm hardware or standard bdm firm ware write commands. ? all other bits, while writable via bdm hardwa re or standard bdm fi rmware write commands, should only be altered by the bdm hardware or standard firmware lookup table as part of bdm command execution. ? enbdm should only be se t via a bdm hardware command if the bdm firmware commands are needed. (this does not apply in special single-chip mode). 76543210 r enbdm bdmact entag sdv trace clksw unsec 0 w reset: special single-chip mode: special peripheral mode: all other modes: 1 1 0 0 0 1 enbdm is read as "1" by a debugging environment in special si ngle-chip mode when the device is not secured or secured but fully erased (flash and eeprom).this is because the enbdm bit is set by the standard firmware before a bdm command can be fully transmitted and executed. 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 2 unsec is read as "1" by a debugging environment in special si ngle-chip mode when the device is secured and fully erased, else it is "0" and can only be read if not secure (see also bit description). 0 0 0 0 = unimplemented or reserved = implemented (do not alter) figure 15-3. bdm status register (bdmsts) note: table 15-2. bdmsts field descriptions field description 7 enbdm enable bdm ? this bit controls whether the bdm is enabled or disabled. when enabled, bdm can be made active to allow firmware commands to be executed. when disabled, bdm cannot be made active but bdm hardware commands are allowed. 0bdm disabled 1 bdm enabled note: enbdm is set by the firmware immediately out of reset in special single-chip mode. in secure mode, this bit will not be set by the firmware until after the eeprom and flash erase verify tests are complete. 6 bdmact bdm active status ? this bit becomes set upon entering bdm. the standard bdm firmware lookup table is then enabled and put into the memory map. bdmact is cl eared by a carefully timed store instruction in the standard bdm firmware as part of the exit sequence to return to user code and remove the bdm memory from the map. 0 bdm not active 1 bdm active chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 451 5 entag tagging enable ? this bit indicates whether instruction tagging in enabled or disabled. it is set when the taggo command is executed and cleared when bdm is entered. the serial system is disabled and the tag function enabled 16 cycles after this bit is written. bdm cannot process serial commands while tagging is active. 0 tagging not enabled or bdm active 1 tagging enabled 4 sdv shift data valid ? this bit is set and cleared by the bdm hardwar e. it is set after data has been transmitted as part of a firmware read command or after data has been re ceived as part of a firmware write command. it is cleared when the next bdm command has been received or bdm is exited. sdv is used by the standard bdm firmware to control program flow execution. 0 data phase of command not complete 1 data phase of command is complete 3 trace trace1 bdm firmware command is being executed ? this bit gets set when a bdm trace1 firmware command is first recognized. it will stay set as long as continuous back-to-back trace1 commands are executed. this bit will get cleared when the next co mmand that is not a trace1 command is recognized. 0 trace1 command is not being executed 1 trace1 command is being executed 2 clksw clock switch ? the clksw bit controls which clock the bdm operat es with. it is only writable from a hardware bdm command. a 150 cycle delay at the clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be ac tive. the start of the next bdm command uses the new clock for timing subsequent bdm communications. ta b l e 1 5 - 3 shows the resulting bdm clock source based on the clksw and the pllsel (pll select from the clock and reset generator) bits. note: the bdm alternate clock source can only be selected when clksw = 0 and pllsel = 1. the bdm serial interface is now fully synchronized to the alternate clock source, when enabled. this eliminates frequency restriction on the alternate clock which was required on previous versions. refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? to determine which clock connects to the alternate clock source input. note: if the acknowledge function is turned on, changing the clksw bit will cause the ack to be at the new rate for the write command which changes it. 1 unsec unsecure ? this bit is only writable in special single-chip mode from the bdm secure firmware and always gets reset to zero. it is in a zero state as secure mode is entered so that the secure bdm firmware lookup table is enabled and put into the memory map along with the standard bdm firmware lookup table. the secure bdm firmware lookup tabl e verifies that the on-chip eeprom and flash eeprom are erased. this being the case, the unsec bit is set and the bdm progra m jumps to the start of the standard bdm firmware lookup table and the secure bdm firmware lookup table is turned off. if the erase test fails, the unsec bit will not be asserted. 0 system is in a secured mode 1 system is in a unsecured mode note: when unsec is set, security is off and the user can change the state of the secure bits in the on-chip flash eeprom. note that if the us er does not change the state of the bits to ?unsecured? mode, the system will be secured again when it is next taken out of reset. table 15-3. bdm clock sources pllsel clksw bdmclk 0 0 bus clock 0 1 bus clock 1 0 alternate clock (refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? to determine the alternate clock source) 1 1 bus clock dependent on the pll table 15-2. bdmsts field descriptions (continued) field description chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 452 freescale semiconductor 15.3.2.2 bdm ccr holdi ng register (bdmccr) read: all modes write: all modes note when bdm is made active, the cpu stor es the value of the ccr register in the bdmccr register. however, out of special single-chip reset, the bdmccr is set to 0xd8 and not 0xd0 wh ich is the reset value of the ccr register. when entering background debug mode, the bdm ccr holdi ng register is used to save the contents of the condition code register of the user?s program. it is also used for temporary st orage in the standard bdm firmware mode. the bdm ccr hol ding register can be written to modify the ccr value. 15.3.2.3 bdm internal register position register (bdminr) read: all modes write: never 76543210 r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w reset00000000 figure 15-4. bdm ccr holding register (bdmccr) 76543210 r 0 reg14 reg13 reg12 reg11 0 0 0 w reset00000000 = unimplemented or reserved figure 15-5. bdm internal register position (bdminr) table 15-4. bdminr field descriptions field description 6:3 reg[14:11] internal register map position ? these four bits show the state of th e upper five bits of the base address for the system?s relocatable register block. bdminr is a s hadow of the initrg register which maps the register block to any 2k byte space within the first 32k bytes of the 64k byte address space. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 453 15.4 functional description the bdm receives and executes commands from a host vi a a single wire serial interface. there are two types of bdm commands, namely, hardwa re commands and firmware commands. hardware commands are used to read and write target system memory locations and to enter active background debug mode, see section 15.4.3, ?bdm hardware commands .? target system memory includes all memory that is accessible by the cpu. firmware commands are used to re ad and write cpu resources and to exit from active background debug mode, see section 15.4.4, ?standard bdm firmware commands .? the cpu resources referred to are the accumulator (d), x index re gister (x), y index register (y), stac k pointer (sp), and pr ogram counter (pc). hardware commands can be execut ed at any time and in any m ode excluding a few exceptions as highlighted, see section 15.4.3, ?bdm hardware commands .? firmware commands can only be executed when the system is in active background debug mode (bdm). 15.4.1 security if the user resets into special si ngle-chip mode with the system se cured, a secured mode bdm firmware lookup table is brought into the map overlapping a por tion of the standard bdm firmware lookup table. the secure bdm firmware verifies that the on- chip eeprom and flash eeprom are erased. this being the case, the unsec bit will get set. the bdm program jumps to the start of the standard bdm firmware and the secured mode bdm firmware is tu rned off and all bdm commands are allowed. if the eeprom or flash do not verify as erased, the bdm firmware sets the enbdm bit, without asserting unsec, and the firmware enters a loop. this causes the bdm hardware commands to become enabled, but does not enable the firmware co mmands. this allows the bdm hardware to be used to erase the eeprom and flash. after execution of the secure firmware, regardless of the results of the erase tests, the cpu registers, initee and ppage, will no longer be in their reset state. 15.4.2 enabling and activating bdm the system must be in active bdm to execute sta ndard bdm firmware comma nds. bdm can be activated only after being enabled. bdm is enabled by settin g the enbdm bit in the bdm status (bdmsts) register. the enbdm bit is set by writing to the bd m status (bdmsts) register, via the single-wire interface, using a hardware command such as write_bd_byte. after being enabled, bdm is activated by one of the following 1 : ? hardware background command ? bdm external instruction tagging mechanism ? cpu bgnd instruction ? breakpoint sub-block?s force or tag mechanism 2 1. bdm is enabled and active immediately out of special single-chip reset. 2. this method is only available on systems t hat have a a breakpoint or a debug sub-block. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 454 freescale semiconductor when bdm is activated, the cpu finishes executing th e current instruction and then begins executing the firmware in the standard bdm firmware lookup ta ble. when bdm is activated by the breakpoint sub-block, the type of brea kpoint used determines if bdm becomes active before or after execution of the next instruction. note if an attempt is made to activate bdm before being enabled, the cpu resumes normal instruction execution af ter a brief delay. if bdm is not enabled, any hardware background commands issued are ignored by the bdm and the cpu is not delayed. in active bdm, the bdm registers and standard bdm firmware lookup table are mapped to addresses 0xff00 to 0xffff. bdm registers are mapped to addresses 0xff00 to 0xff07. the bdm uses these registers which are readable anytime by the bdm. ho wever, these registers are not readable by user programs. 15.4.3 bdm hardware commands hardware commands are used to read and write target system memory locations and to enter active background debug mode. target system memory includes all memory that is accessible by the cpu such as on-chip ram, eeprom, flash eeprom, i/o and control registers, and all external memory. hardware commands are executed with minimal or no cpu intervention and do not require the system to be in active bdm for execution, alt hough they can continue to be executed in this mode. when executing a hardware command, the bdm sub-block waits for a free cpu bus cycle so that the background access does not disturb the running application program. if a free cycle is not found within 128 clock cycles, the cpu is momentarily frozen so that the bdm can stea l a cycle. when the bdm finds a free cycle, the operation does not intrude on normal cpu operation provide d that it can be completed in a single cycle. however, if an operation requires multiple cycles the cpu is frozen until the operation is complete, even though the bdm found a free cycle. the bdm hardware commands are listed in table 15-5 . table 15-5. hardware commands command opcode (hex) data description background 90 none enter background mode if firmware is enabled. if enabled, an ack will be issued when the part enters active background mode. ack_enable d5 none enable handshake. iss ues an ack pulse after the command is executed. ack_disable d6 none disable handshake. this command does not issue an ack pulse. read_bd_byte e4 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table in map. odd address data on low byte; even address data on high byte. read_bd_word ec 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table in map. must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table out of map. odd address data on low byte; even address data on high byte. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 455 note: if enabled, ack will occur when data is ready for transmission for all bdm read commands and will occur after the write is complete for all bdm write commands. the read_bd and write_bd commands allow access to the bdm register loca tions. these locations are not normally in the system memory map but shar e addresses with the application in memory. to distinguish between physical memory locations that share the same a ddress, bdm memory resources are enabled just for the read_bd and write_bd acce ss cycle. this allows the bdm to access bdm locations unobtrusively, even if the addresses conf lict with the application memory map. 15.4.4 standard bdm firmware commands firmware commands are used to acc ess and manipulate cpu re sources. the system must be in active bdm to execute standard bdm firmware commands, see section 15.4.2, ?enabling and activating bdm .? normal instruction execution is suspended whil e the cpu executes the firmware located in the standard bdm firmware lookup table. the hardwa re command background is the usual way to activate bdm. as the system enters active bdm, the standard bdm firmware lookup table a nd bdm registers become visible in the on-chip memory map at 0xff00?0xffff, and the cpu begins executing the standard bdm firmware. the standard bdm firmware watches for se rial commands and executes them as they are received. the firmware commands are shown in table 15-6 . read_word e8 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table out of map. must be aligned access. write_bd_byte c4 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table in map. odd address data on low byte; even address data on high byte. write_bd_word cc 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table in map. must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table out of map. odd address data on low byte; even address data on high byte. write_word c8 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table out of map. must be aligned access. table 15-5. hardware commands (continued) command opcode (hex) data description chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 456 freescale semiconductor 15.4.5 bdm command structure hardware and firmware bdm commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the comm and. all the read commands return 16 bits of data despite the byte or word implication in the command name. note 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. if reading an even address, the va lid data will appear in the msb. if reading an odd address, the valid data will appear in the lsb. note 16-bit misaligned reads and writes ar e not allowed. if attempted, the bdm will ignore the least significant bit of the address and will assume an even address from the remaining bits. table 15-6. firmware commands command 1 1 if enabled, ack will occur when data is ready for transmission for all bdm read commands and will occur after the write is complete for all bdm write commands. opcode (hex) data description read_next 62 16-bit data out increment x by 2 (x = x + 2), then read word x points to. read_pc 63 16-bit data out read program counter. read_d 64 16-bit data out read d accumulator. read_x 65 16-bit data out read x index register. read_y 66 16-bit data out read y index register. read_sp 67 16-bit data out read stack pointer. write_next 42 16-bit data in increment x by 2 (x = x + 2), then write word to location pointed to by x. write_pc 43 16-bit data in write program counter. write_d 44 16-bit data in write d accumulator. write_x 45 16-bit data in write x index register. write_y 46 16-bit data in write y index register. write_sp 47 16-bit data in write stack pointer. go 08 none go to user program. if enabled, ack will occur when leaving active background mode. go_until 2 2 both wait (with clocks to the s12 cpu core disabled) and st op disable the ack function. the go_until command will not get an acknowledge if one of these two cp u instructions occurs before the ?until? instruction. this can be a problem for any instruction that uses ack, but go_until is a lot mo re difficult for the develo pment tool to time-out. 0c none go to user program. if enabled, ack will occur upon returning to active background mode. trace1 10 none execute one user instruction then return to active bdm. if enabled, ack will occur upon returning to active background mode. taggo 18 none enable tagging and go to user pr ogram. there is no ack pulse related to this command. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 457 for hardware data read commands, the external hos t must wait 150 bus clock cycles after sending the address before attempting to obtain the read data. this is to be certain th at valid data is available in the bdm shift register, ready to be shifted out. for hard ware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before atte mpting to send a new command. this is to avoid disturbing the bdm shif t register before the write has been complete d. the 150 bus clock cycle delay in both cases includes the maximum 128 cycle de lay that can be incurred as the bdm waits for a free cycle before stealing a cycle. for firmware read commands, the ex ternal host should wait 44 bus cloc k cycles after sending the command opcode and before attempting to obtain the read data. this incl udes the potential of an extra 7 cycles when the access is external with a narrow bus access (+1 cycle) and / or a stretch (+1, 2, or 3 cycles), (7 cycles could be needed if both occur). the 44 cycle wait al lows enough time for the requested data to be made available in the bdm shift regist er, ready to be shifted out. note this timing has increased from prev ious bdm modules due to the new capability in which the bdm serial inte rface can potentially run faster than the bus. on previous bdm modules this extra time could be hidden within the serial time. for firmware write commands, the exte rnal host must wait 32 bu s clock cycles after se nding the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the external host should wait 64 bus clock cycles after a trace1 or go command before starting any new serial command. this is to allow the cpu to exit gracefully from the st andard bdm firmware lookup table and resume execution of the user code. disturbing the bdm shift register prematurely may adversely affect the exit from the sta ndard bdm firmware lookup table. note if the bus rate of the target proces sor is unknown or coul d be changing, it is recommended that the ack (acknowledge function) be used to indicate when an operation is complete. when using ack, the delay times are automated. figure 15-6 represents the bdm command structure. the comm and blocks illustrate a series of eight bit times starting with a falling edge. th e bar across the top of the blocks i ndicates that the bkgd line idles in the high state. the time for an 8-bit command is 8 16 target clock cycles. 1 1. target clock cycles are cycles measured us ing the target mcu?s se rial clock rate. see section 15.4.6, ?bdm serial interface ,? and section 15.3.2.1, ?bdm st atus register (bdmsts) ,? for information on how serial clock rate is selected. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 458 freescale semiconductor figure 15-6. bdm command structure 15.4.6 bdm serial interface the bdm communicates with external devices serially via the bkgd pin. during reset, this pin is a mode select input which select s between normal and special modes of ope ration. after reset, this pin becomes the dedicated serial interface pin for the bdm. the bdm serial interface is timed using the clock se lected by the clksw bit in the status register see section 15.3.2.1, ?bdm status register (bdmsts) .? this clock will be referred to as the target clock in the following explanation. the bdm serial interface uses a cl ocking scheme in which the extern al host generates a falling edge on the bkgd pin to indicate the start of each bit time. this falling edge is sent for every bit whether data is transmitted or received. data is tran sferred most significant bit (msb) fi rst at 16 target clock cycles per bit. the interface times out if 512 clock cycles occur between falling edges from the host. the bkgd pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. it is assumed that there is an external pull- up and that drivers connecte d to bkgd do not typically drive the high level. because r-c rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive bkgd to a logic 1. the source of this speedup pulse is the host for transmit cases and the target for receive cases. the timing for host-to-target is shown in figure 15-7 and that of target-to-host in figure 15-8 and figure 15-9 . all four cases begin when the host drives th e bkgd pin low to generate a falling edge. because the host and target are operating from separate cl ocks, it can take the target system up to one full clock cycle to recognize this edge. th e target measures dela ys from this perceive d start of the bit time while the host measures delays from the point it actua lly drove bkgd low to start the bit up to one target hardware hardware firmware firmware go, 44-bc bc = bus clock cycles command address 150-bc delay next delay 8 bits at 16 tc/bit 16 bits at 16 tc/bit 16 bits at 16 tc/bit command address data next data read write read write trace command next command data 64-bc delay next command 150-bc delay 32-bc delay command command command command data next command tc = target clock cycles chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 459 clock cycle earlier. synchronization be tween the host and target is establ ished in this manner at the start of every bit time. figure 15-7 shows an external host transmit ting a logic 1 and transmitting a logic 0 to the bkgd pin of a target system. the host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. ten target clock cycles later, the targ et senses the bit level on the bkgd pin. internal glitch detect logic requires the pin be driven high no later that eight targ et clock cycles after the falling edge for a logic 1 transmission. because the host drives the high speedup pulses in th ese two cases, the rising e dges look like digitally driven signals. figure 15-7. bdm host-to-target serial bit timing the receive cases ar e more complicated. figure 15-8 shows the host receiving a logic 1 from the target system. because the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target. the host holds the bkgd pin low long enough for the target to recognize it (at least two targ et clock cycles). the host must release the low drive before the targ et drives a brief high speedup pulse se ven target clock cycles after the perceived start of the bit time. the host should sample the bit level about 10 target clock cycles after it started the bit time. earliest start of next bit target senses bit 10 cycles synchronization uncertainty clock target system host transmit 1 host transmit 0 perceived s tart of bit time chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 460 freescale semiconductor figure 15-8. bdm target-to-host serial bit timing (logic 1) figure 15-9 shows the host receiving a logic 0 from the ta rget. because the host is asynchronous to the target, there is up to a one clock-cy cle delay from the host-generated fa lling edge on bkgd to the start of the bit time as perceived by the targ et. the host initiates the bit time but the target finishes it. because the target wants the host to receive a l ogic 0, it drives the bkgd pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 target clock cycles after starting the bit time. figure 15-9. bdm target-to-host serial bit timing (logic 0) high-impedance earliest start of next bit r-c rise 10 cycles 10 cycles host samples bkgd pin perceived start of bit time bkgd pin clock target system host drive to bkgd pin target system speedup pulse high-impedance high-impedance earliest start of next bit clock target sys. host drive to bkgd pin bkgd pin perceived start of bit time 10 cycles 10 cycles host samples bkgd pin target sys. drive and speedup pulse speedup pulse high-impedance chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 461 15.4.7 serial interface ha rdware handshake protocol bdm commands that require cpu exec ution are ultimately treated at the mcu bus rate. because the bdm clock source can be asynchronously related to the bus frequency, when clksw = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the cpu. the alternative is to alwa ys wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be r unning. this sub-section will describe the hardware handshake protocol. the hardware handshake prot ocol signals to the host controller when an issued command was successfully executed by the target. this protocol is implemented by a 16 serial cl ock cycle low pulse followed by a brief speedup pulse in the bkgd pin. this pulse is ge nerated by the target mc u when a command, issued by the host, has been successfully executed (see figure 15-10 ). this pulse is referr ed to as the ack pulse. after the ack pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (background, go, go_until, or trace1). the ack pulse is not issued earlier than 32 serial clock cycles after the bdm command was issued. th e end of the bdm command is assumed to be the 16th tick of the last bit. this minimum delay assures enough time for the host to pe rceive the ack pulse. note also that, there is no upper limit for the dela y between the command and the related ack pulse, because the command execut ion depends upon the cpu bus frequency, which in some cases could be very slow compared to the serial communication rate. this protocol allows a great flexibility for the pod designers, because it does not rely on any accurate time measurement or short response time to any event in the serial communication. figure 15-10. target acknowledge pulse (ack) note if the ack pulse was issued by the ta rget, the host assumes the previous command was executed. if the cpu enters wait or stop prior to executing a hardware command, the ack pulse will not be issued meaning that the bdm command was not execute d. after entering wait or stop mode, the bdm command is no longer pending. 16 cycles bdm clock (target mcu) target transmits pulse ack high-impedance bkgd pin minimum delay from the bdm command 32 cycles earliest start of next bit speedup pulse 16th tick of the last commad bit high-impedance chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 462 freescale semiconductor figure 15-11 shows the ack handshake prot ocol in a command level ti ming diagram. the read_byte instruction is used as an example. first, the 8-bit instruction opcode is sent by the host, followed by the address of the memory locat ion to be read. the target bdm decodes the instruction. a bus cycle is grabbed (free or stolen) by the bdm a nd it executes the read_byte operati on. having retrieved the data, the bdm issues an ack pulse to the host controller, indica ting that the addressed byte is ready to be retrieved. after detecting the ack pulse, the host initiates the byte retrieval process. note that data is sent in the form of a word and the host needs to determine which is the appropria te byte based on whether the address was odd or even. figure 15-11. handshake protocol at command level differently from the normal bit tran sfer (where the host initiates the transmission), the serial interface ack handshake pulse is initiate d by the target mcu by issuing a falling edge in the bkgd pin. the hardware handshake protocol in figure 15-10 specifies the timing when the bkgd pin is being driven, so the host should follow this timing constr aint in order to avoid the risk of an electrica l conflict in the bkgd pin. note the only place the bkgd pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). other ?highs? are pulled rather than driven. ho wever, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. the ack handshake protocol does not support nested ack pulses. if a bdm command is not acknowledge by an ack pulse, the host needs to abort th e pending command first in order to be able to issue a new bdm command. when the cpu enters wait or stop while the host issues a command that requires cpu execution (e.g., write_by te), the target discards the incoming command due to the wait or stop being detected. therefore, the co mmand is not acknowledged by the target, which means that the ack pulse will not be issued in this case . after a certain ti me the host should decide to abort the ack sequence in order to be free to issue a new command. therefore, the pr otocol should provide a mechanism in which a command, and theref ore a pending ack, could be aborted. note differently from a regular bdm comm and, the ack pulse does not provide a time out. this means that in the case of a wait or stop instruction being executed, the ack would be prevented from being issued. if not aborted, the ack would remain pending inde finitely. see the handshake abort procedure described in section 15.4.8, ?hardware handshake abort procedure .? read_byte bdm issues the bkgd pin byte address bdm executes the read_byte command host target host target bdm decodes the command ack pulse (out of scale) host target (2) bytes are retrieved new bdm command chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 463 15.4.8 hardware handshake abort procedure the abort procedure is based on th e sync command. in order to abor t a command, which had not issued the corresponding ack pulse, th e host controller should generate a low pulse in the bkgd pin by driving it low for at least 128 serial clock cycles and then driving it high for one seri al clock cycle, providing a speedup pulse. by detecting this long low pulse in the bkgd pin, the ta rget executes the sync protocol, see section 15.4.9, ?sync ? request timed reference pulse ,? and assumes that the pending command and therefore the related ack pulse , are being aborted. therefore, af ter the sync protocol has been completed the host is free to issue new bdm commands. although it is not recommended, th e host could abort a pending bdm co mmand by issuing a low pulse in the bkgd pin shorter than 128 serial clock cycles, wh ich will not be interpreted as the sync command. the ack is actually aborted when a falling edge is perceived by the target in the bkgd pin. the short abort pulse should have at least 4 clock cycles keeping the bkgd pin low, in order to allow the falling edge to be detected by the target. in this case, the ta rget will not execute the sync protocol but the pending command will be aborted al ong with the ack pulse. the potential pr oblem with this abort procedure is when there is a conflict between th e ack pulse and the short abort pulse. in this case, the target may not perceive the abort pulse. the worst case is wh en the pending command is a read command (i.e., read_byte). if the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. in this case, host and target will run out of synchronism. however, if the command to be aborted is not a read command the short abort pulse could be used. af ter a command is aborted the target assumes the next falling edge, after the abort pulse, is the first bit of a new bdm command. note the details about the short abort pulse are being provided only as a reference for the reader to better understand th e bdm internal behavior. it is not recommended that this procedure be used in a real application. because the host knows the target serial clock freque ncy, the sync command (u sed to abort a command) does not need to consider the lower possible target frequency. in this case, the host could issue a sync very close to the 128 serial clock cycles length. providing a small overhea d on the pulse length in order to assure the sync pulse will not be misinterpreted by the target. see section 15.4.9, ?sync ? request timed reference pulse .? figure 15-12 shows a sync command being issued after a read_byte, which aborts the read_byte command. note that, afte r the command is aborted a new command could be issued by the host computer. note figure 15-12 does not represent the signals in a true timing scale chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 464 freescale semiconductor figure 15-12. ack abort procedure at the command level figure 15-13 shows a conflict between the ack pulse and the sync request pulse. this conflict could occur if a pod device is connected to the target bk gd pin and the target is al ready in debug active mode. consider that the target cpu is executing a pending bdm command at th e exact moment the pod is being connected to the bkgd pin. in this case, an ack pulse is issued along with the sync command. in this case, there is an electrical conflict between the ack speedup pulse and the sync pulse. because this is not a probable situation, the protocol does not prevent this conflict from happening. figure 15-13. ack pulse and sync request conflict note this information is being provided so th at the mcu integrator will be aware that such a conflict could eventually occur. the hardware handshake protocol is enabled by the ack_enable and disa bled by the ack_disable bdm commands. this provides back wards compatibility with the ex isting pod devices which are not able to execute the hardware hands hake protocol. it also allows fo r new pod devices, that support the hardware handshake protocol, to fr eely communicate with the target de vice. if desired, without the need for waiting for the ack pulse. read_byte read_status bkgd pin memory address new bdm command new bdm command host target host target host target sync response from the target (out of scale) bdm decode and starts to executes the read_byte cmd read_byte cmd is aborted by the sync request (out of scale) bdm clock (target mcu) target mcu drives to bkgd pin bkgd pin 16 cycles speedup pulse high-impedance host drives sync to bkgd pin ack pulse host sync request pulse at least 128 cycles electrical conflict host and target drive to bkgd pin chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 465 the commands are described as follows: ? ack_enable ? enables the hardwa re handshake protocol. the ta rget will issue the ack pulse when a cpu command is executed by the cpu. the ack_enable comma nd itself also has the ack pulse as a response. ? ack_disable ? disables the ack pulse protocol. in this case, the host needs to use the worst case delay time at the appropr iate places in the protocol. the default state of the bdm after reset is hardware handshake protocol disabled. all the read commands will ack (if enabled) when the data bus cy cle has completed and the data is then ready for reading out by the bkgd se rial pin. all the write commands will ack (if en abled) after the data has been received by the bdm through the bkgd serial pin and when the data bus cycle is complete. see section 15.4.3, ?bdm hardware commands ,? and section 15.4.4, ?standard bdm firmware commands ,? for more information on the bdm commands. the ack_enable sends an ack pulse when the command has been co mpleted. this feature could be used by the host to evaluate if the target supports th e hardware handshake protocol. if an ack pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. if the target does not s upport the hardware handshake protocol the ack pulse is not issued. in this case, the ack_enable command is ignored by the target because it is not recognized as a valid command. the background command will issue an ack pulse when the cpu changes from normal to background mode. the ack pulse related to this co mmand could be aborted using the sync command. the go command will issue an ack pulse when th e cpu exits from background mode. the ack pulse related to this command could be aborted using the sync command. the go_until command is equivalent to a go comm and with exception that the ack pulse, in this case, is issued when the cpu enters into background mode. this command is an alternative to the go command and should be used when the host wants to trace if a breakpoint match occurs and causes the cpu to enter active background mode. note that the ack is issued when ever the cpu enters bdm, which could be caused by a breakpoint ma tch or by a bgnd instruction bei ng executed. the ack pulse related to this command could be a borted using the sync command. the trace1 command has the related ack pulse is sued when the cpu enters background active mode after one instruction of the application pr ogram is executed. the ack pulse related to this command could be aborted using the sync command. the taggo command will not issue an ack pulse because this would interfere with the tagging function shared on the same pin. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 466 freescale semiconductor 15.4.9 sync ? request timed reference pulse the sync command is unlike other bdm commands because the host does not necessarily know the correct communication sp eed to use for bdm communications until after it has analyzed the response to the sync command. to issue a sync command, the host should perform the following steps: 1. drive the bkgd pin low for at least 128 cycles at the lowest possible bdm serial communication frequency (the lowest serial comm unication frequency is determined by the crystal oscillator or the clock chosen by clksw.) 2. drive bkgd high for a brief speedup pulse to get a fast rise time (this sp eedup pulse is typically one cycle of the host clock.) 3. remove all drive to the bkgd pin so it reverts to high impedance. 4. listen to the bkgd pin for the sync response pulse. upon detecting the sync request from the host, the target performs the following steps: 1. discards any incomplete comm and received or bit retrieved. 2. waits for bkgd to return to a logic 1. 3. delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. drives bkgd low for 128 cycles at the current bdm serial co mmunication frequency. 5. drives a one-cycle high speedup pulse to force a fast rise time on bkgd. 6. removes all drive to the bkgd pi n so it reverts to high impedance. the host measures the low time of this 128 cycle sync response pul se and determines the correct speed for subsequent bdm communications. typically, the host can determin e the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. as soon as the sync request is detected by the target , any partially received co mmand or bit retrieved is discarded. this is referred to as a soft-reset, equivalent to a time-out in the serial communication. after the sync response, the target will consider the next fa lling edge (issued by the host) as the start of a new bdm command or the start of new sync request. another use of the sync command pulse is to abor t a pending ack pulse. the be havior is exactly the same as in a regular sync command. note that one of the possible causes for a command to not be acknowledged by the target is a host- target synchronization problem. in this case, the command may not have been understood by the ta rget and so an ack response pulse will not be issued. 15.4.10 instruction tracing when a trace1 command is issued to the bdm in active bdm, the cpu exits the standard bdm firmware and executes a single instruct ion in the user code. as soon as th is has occurred, the cpu is forced to return to the standard bdm firmware and the bd m is active and ready to receive a new command. if the trace1 command is issued again, the next user instruction will be executed. this facilitates stepping or tracing through the user code one instruction at a time. chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 467 if an interrupt is pending when a trace1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. upon return to standard bdm firm ware execution, the program counter points to the first instruction in the interrupt service routine. 15.4.11 instruction tagging the instruction queue and cycle-by-cycle cpu activity are reconstructible in re al time or from trace history that is captured by a logic analyzer. however, the reconstructed queue cannot be used to stop the cpu at a specific instruction. this is because execution already has begun by the time an operation is visible outside the system. a separate instruct ion tagging mechanism is provided for this purpose. the tag follows program information as it adva nces through the instruction queue. when a tagged instruction reaches the head of the queue, the cpu en ters active bdm rather than executing the instruction. note tagging is disabled when bdm become s active and bdm serial commands are not processed while tagging is active. executing the bdm taggo command configures two system pins for tagging. the taglo signal shares a pin with the lstrb signal, and the taghi signal shares a pin with the bkgd signal. table 15-7 shows the functions of the two tagging pins. the pins operate independently, that is the state of one pin does not affect the f unction of the other. the presence of logi c level 0 on either pin at the fall of the external clock (eclk) perfor ms the indicated function. high taggi ng is allowed in all modes. low tagging is allowed only when low st robe is enabled (lstrb is allowe d only in wide expanded modes and emulation expanded narrow mode). 15.4.12 serial comm unication time-out the host initiates a host-to-target serial transmis sion by generating a falling edge on the bkgd pin. if bkgd is kept low for more than 128 target clock cycles, the target understa nds that a sync command was issued. in this case, the target will keep wai ting for a rising edge on bkgd in order to answer the sync request pulse. if the rising edge is not detected, the target will keep waiting forever without any time-out limit. consider now the case where the host returns bkgd to logic one before 128 cycles. this is interpreted as a valid bit transmission, and not as a sync request. the target will keep waiting for another falling edge marking the start of a new bi t. if, however, a new falli ng edge is not detected by the target within 512 clock cycles since the last falli ng edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the mcu. this is referred to as a soft-reset. table 15-7. tag pin function taghi taglo tag 11no tag 10low byte 0 1 high byte 0 0 both bytes chapter 15 background debug module (bdmv4) mc9s12e256 data sheet, rev. 1.08 468 freescale semiconductor if a read command is issued but the data is not retr ieved within 512 serial cloc k cycles, a soft-reset will occur causing the command to be disreg arded. the data is not available fo r retrieval after the time-out has occurred. this is the expected behavior if the hands hake protocol is not enab led. however, consider the behavior where the bdc is running in a frequency much greater than the cpu frequency. in this case, the command could time out before the data is ready to be retrieved. in order to allow the data to be retrieved even with a large clock frequenc y mismatch (between bdc and cpu) when the hardware handshake protocol is enabled, the time out be tween a read command and the data re trieval is disabled. therefore, the host could wait for more then 512 serial clock cycles and continue to be ab le to retrieve the data from an issued read command. however, as soon as the hands hake pulse (ack pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 5 12 clock cycles. therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ack pul se had been issued. after that period, the read command is discarded and the data is no longer avai lable for retrieval. any falling edge of the bkgd pin after the time-out pe riod is considered to be a new command or a sync request. note that whenever a part ially issued command, or partially retrie ved data, has occurred the time out in the serial communication is active. this means that if a time frame higher than 512 serial clock cycles is observed between two consecu tive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. the next falling edge of the bkgd pin, af ter a soft-reset has occurr ed, is considered by the target as the start of a new bdm comma nd, or the start of a sync request pulse. 15.4.13 operation in wait mode the bdm cannot be used in wait mode if th e system disables th e clocks to the bdm. there is a clearing mechanism associated with the wa it instruction when the clocks to the bdm (cpu core platform) are disable d. as the clocks restart from wait mode , the bdm receives a soft reset (clearing any command in progress) and the ac k function will be disabled. this is a change from previous bdm modules. 15.4.14 operation in stop mode the bdm is completely shutdown in stop mode. there is a clearing mechanism associated with the st op instruction. stop must be enabled and the part must go into stop mode for this to occur. as the cl ocks restart from stop m ode, the bdm receives a soft reset (clearing any command in prog ress) and the ack function will be disabled. this is a change from previous bdm modules. mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 469 chapter 16 debug module (dbgv1) 16.1 introduction this section describes the functi onality of the debug (dbg) sub-bl ock of the hcs12 core platform. the dbg module is designed to be fully compat ible with the existing bkp_hcs12_a module (bkp mode) and furthermore provides an on -chip trace buffer with flexible tr iggering capability (dbg mode). the dbg module provides for non-in trusive debug of application soft ware. the dbg m odule is optimized for the hcs12 16-bit architecture. 16.1.1 features the dbg module in bkp mode includ es these distinctive features: ? full or dual breakpoint mode ? compare on address and data (full) ? compare on either of two addresses (dual) ? bdm or swi breakpoint ? enter bdm on breakpoint (bdm) ? execute swi on breakpoint (swi) ? tagged or forced breakpoint ? break just before a specific inst ruction will begin execution (tag) ? break on the first instruction boundary after a match occurs (force) ? single, range, or page address compares ? compare on address (single) ? compare on address 256 byte (range) ? compare on any 16k page (page) ? at forced breakpoints compare address on read or write ? high and/or low byte data compares ? comparator c can provide an additional tag or force breakpoint (enhancement for bkp mode) chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 470 freescale semiconductor the dbg in dbg mode includes these distinctive features: ? three comparators (a, b, and c) ? dual mode, comparators a and b used to compare addresses ? full mode, comparator a compares address and comparator b compares data ? can be used as trigger and/or breakpoint ? comparator c used in loop1 captur e mode or as additional breakpoint ? four capture modes ? normal mode, change-of-flow information is captured ba sed on trigger specification ? loop1 mode, comparator c is dynamically upda ted to prevent redundant change-of-flow storage. ? detail mode, address and data for all cycles ex cept program fetch (p) and free (f) cycles are stored in trace buffer ? profile mode, last instruction address executed by cpu is returned when trace buffer address is read ? two types of breakpoint or debug triggers ? break just before a specific inst ruction will begin execution (tag) ? break on the first instruction boundary after a match occurs (force) ? bdm or swi breakpoint ? enter bdm on breakpoint (bdm) ? execute swi on breakpoint (swi) ? nine trigger modes for comparators a and b ?a ? a or b ? a then b ? a and b, where b is data (full mode) ? a and not b, where b is data (full mode) ? event only b, store data ? a then event only b, store data ? inside range, a address b ? outside range, address < or address > b ? comparator c provides an additiona l tag or force breakpoint when ca pture mode is not configured in loop1 mode. ? sixty-four word (16 bits wide) trace buffer for storing change-of-f low information, event only data and other bus information. ? source address of taken conditional branches (l ong, short, bit-conditional, and loop constructs) ? destination address of indexed jmp, jsr, and call instruction. ? destination address of rti, rts, and rtc instructions ? vector address of in terrupts, except for swi and bdm vectors chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 471 ? data associated with event b trigger modes ? detail report mode stores address and data for all cycles ex cept program (p) and free (f) cycles ? current instruction addres s when in profiling mode ? bgnd is not considered a change-of-flow (cof) by the debugger 16.1.2 modes of operation there are two main modes of operation: breakpoint m ode and debug mode. each one is mutually exclusive of the other and selected via a so ftware programmable control bit. in the breakpoint mode there are two sub-modes of operation: ? dual address mode, where a match on either of two addresses will cause the system to enter background debug mode (bdm) or initia te a software interrupt (swi). ? full breakpoint mode, where a match on address and data will cause the system to enter background debug mode (bdm) or initia te a software interrupt (swi). in debug mode, there are several sub-modes of operation. ? trigger modes there are many ways to create a l ogical trigger. the trigger can be used to capture bus information either starting from the trigger or ending at the trigger. types of triggers (a and b are registers): ? a only ? a or b ? a then b ? event only b (data capture) ? a then event only b (data capture) ? a and b, full mode ? a and not b, full mode ? inside range ? outside range ? capture modes there are several capture modes. these determin e which bus information is saved and which is ignored. ? normal: save change-o f-flow program fetches ? loop1: save change-of-flow progr am fetches, ignoring duplicates ? detail: save all bus operations except program and free cycles ? profile: poll target from external device 16.1.3 block diagram figure 16-1 is a block diagram of this module in breakpoint mode. figure 16-2 is a block diagram of this module in debug mode. chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 472 freescale semiconductor figure 16-1. dbg block diagram in bkp mode comparator compare block register block comparator comparator comparator comparator comparator expansion addresses expansion addresses address high address low data high data low address high address low comparator comparator read data high read data low . . . . . . . . . . . . clocks and bkp control control signals signals control block breakpoint modes and generation of swi, force bdm, and tags expansion address address write data read data read/write control control bits control signals results signals bkp0h bkp0l bkp0x bkpct0 bkp1x bkpct1 bkp1l bkp1h write bkp read data bus data bus data/address high mux data/address low mux chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 473 figure 16-2. dbg block diagram in dbg mode 16.2 external signal description the dbg sub-module relies on the external bus interf ace (generally the mebi) when the dbg is matching on the external bus. the tag pins in table 16-1 (part of the mebi) may also be a part of the breakpoint operation. table 16-1. external system pins associated with dbg and mebi pin name pin functions description bkgd/modc/ tag h i tag h i when instruction tagging is on, a 0 at the falling edge of e tags the high half of the instruction word being read into the instruction queue. pe3/lstrb / taglo tag l o in expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the fa lling edge of e tags the low half of the instruction word being read into the instruction queue. tag force address bus match_a control read data bus read/write store mcu in bdm m u x pointer register match_b m u x event only write data bus trace buffer dbg read data bus dbg mode enable m u x write data bus read data bus read/write match_c loop1 detail m u x profile capture mode cpu program counter control comparator a address/data/control comparator b comparator c registers tracer buffer control logic change-of-flow indicators or profiling data 64 x 16 bit word trace buffer profile capture register last instruction address bus clock instruction last cycle chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 474 freescale semiconductor 16.3 memory map and register definition a summary of the registers associated with the dbg sub-block is shown in figure 16-3 . detailed descriptions of the register s and bits are given in the subsections that follow. 16.3.1 module memory map 16.3.2 register descriptions this section consists of the dbg regi ster descriptions in address order. most of the register bits can be written to in either bkp or dbg mode, although they may not have any effect in one of the modes. however, the only bits in the dbg module that can be writ ten while the debugger is armed (arm = 1) are dbgen and arm table 16-2. dbgv1 memory map address offset use access debug control register (dbgc1) r/w debug status and control register (dbgsc) r/w debug trace buffer register high (dbgtbh) r debug trace buffer register low (dbgtbl) r 4 debug count register (dbgcnt) r 5 debug comparator c extended register (dbgccx) r/w 6 debug comparator c register high (dbgcch) r/w debug comparator c register low (dbgccl) r/w 8 debug control register 2 (dbgc2) / (bkpct0) r/w 9 debug control register 3 (dbgc3) / (bkpct1) r/w a debug comparator a extended re gister (dbgcax) / (/bkp0x) r/w b debug comparator a register high (dbgcah) / (bkp0h) r/w debug comparator a register low (dbgcal) / (bkp0l) r/w debug comparator b extended re gister (dbgcbx) / (bkp1x) r/w e debug comparator b register high (dbgcbh) / (bkp1h) r/w f debug comparator b register low (dbgcbl) / (bkp1l) r/w name 1 bit 7654321bit 0 dbgc1 r dbgen arm trgsel begin dbgbrk 0 capmod w dbgsc raf bf cf 0 trg w = unimplemented or reserved figure 16-3. dbg register summary chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 475 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w dbgtbl rbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w dbgcnt rtbf 0 cnt w dbgccx (2 ) r pagsel extcmp w dbgcch (2) r bit 15 14 13 12 11 10 9 bit 8 w dbgccl (2) r bit 7654321bit 0 w dbgc2 bkpct0 r bkaben full bdm tagab bkcen tagc rwcen rwc w dbgc3 bkpct1 r bkambh bkambl bkbmbh bkbmbl rwaen rwa rwben rwb w dbgcax bkp0x r pagsel extcmp w dbgcah bkp0h r bit 15 14 13 12 11 10 9 bit 8 w dbgcal bkp0l r bit 7654321bit 0 w dbgcbx bkp1x r pagsel extcmp w dbgcbh bkp1h r bit 15 14 13 12 11 10 9 bit 8 w dbgcbl bkp1l r bit 7654321bit 0 w 1 the dbg module is designed for backwards compatibility to ex isting bkp modules. register and bit names have changed from the bkp module. this column shows the dbg register na me, as well as the bkp register name for reference. 2 comparator c can be used to enhance the bkp mode by providing a third breakpoint. name 1 bit 7654321bit 0 = unimplemented or reserved figure 16-3. dbg register summary (continued) chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 476 freescale semiconductor 16.3.2.1 debug control register 1 (dbgc1) note all bits are used in dbg mode only. note this register cannot be written if bkp mode is enabled (bkaben in dbgc2 is set). 76543210 r dbgen arm trgsel begin dbgbrk 0 capmod w reset00000000 = unimplemented or reserved figure 16-4. debug control register (dbgc1) table 16-3. dbgc1 field descriptions field description 7 dbgen dbg mode enable bit ? the dbgen bit enables the dbg module for use in dbg mode. this bit cannot be set if the mcu is in secure mode. 0 dbg mode disabled 1 dbg mode enabled 6 arm arm bit ? the arm bit controls whether the debugger is comparing and storing data in the trace buffer. see section 16.4.2.4, ?arming the dbg module ,? for more information. 0 debugger unarmed 1 debugger armed note: this bit cannot be set if the dbgen bit is not also being set at the same time. for example, a write of 01 to dbgen[7:6] will be interp reted as a write of 00. 5 trgsel trigger selection bit ? the trgsel bit controls the triggering condition for comparators a and b in dbg mode. it serves essentially the same function as the ta gab bit in the dbgc2 register does in bkp mode. see section 16.4.2.1.2, ?trigger selection ,? for more information. trgsel may also determine the type of breakpoint based on comparator a and b if enabled in dbg mode (dbgbrk = 1). please refer to section 16.4.3.1, ?breakpoint based on comparator a and b .? 0 trigger on any compare address match 1 trigger before opcode at compare address gets executed (tagged-type) 4 begin begin/end trigger bit ? the begin bit controls whether the trigger begins or ends storing of data in the trace buffer. see section 16.4.2.8.1, ?storing with begin-trigger ,? and section 16.4.2.8.2, ?storing with end-trigger ,? for more details. 0 trigger at end of stored data 1 trigger before storing data chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 477 3 dbgbrk dbg breakpoint enable bit ? the dbgbrk bit controls whether the debugger will request a breakpoint based on comparator a and b to the cpu upon completion of a tracing session. please refer to section 16.4.3, ?breakpoints ,? for further details. 0 cpu break request not enabled 1 cpu break request enabled 1:0 capmod capture mode field ? see ta bl e 1 6 - 4 for capture mode field definitions. in loop1 mode, the debugger will automatically inhibit redundant entries into capture memo ry. in detail mode, the debugger is storing address and data for all cycles except program fetc h (p) and free (f) cycles. in profile mode, the debugger is returning the address of the last instruction executed by the cpu on each access of trace buffer address. refer to section 16.4.2.6, ?capture modes ,? for more information. table 16-4. capmod encoding capmod description 00 normal 01 loop1 10 detail 11 profile table 16-3. dbgc1 field descriptions (continued) field description chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 478 freescale semiconductor 16.3.2.2 debug status and control register (dbgsc) 76543210 raf bf cf 0 trg w reset00000000 = unimplemented or reserved figure 16-5. debug status and control register (dbgsc) table 16-5. dbgsc field descriptions field description 7 af trigger a match flag ? the af bit indicates if trigger a match co ndition was met since arming. this bit is cleared when arm in dbgc1 is written to a 1 or on any write to this register. 0 trigger a did not match 1 trigger a match 6 bf trigger b match flag ? the bf bit indicates if trigger b match condition was met since arming.this bit is cleared when arm in dbgc1 is written to a 1 or on any write to this register. 0 trigger b did not match 1 trigger b match 5 cf comparator c match flag ? the cf bit indicates if comparator c match condition was met since arming.this bit is cleared when arm in dbgc1 is written to a 1 or on any write to this register. 0 comparator c did not match 1 comparator c match 3:0 trg trigger mode bits ? the trg bits select the trigger mode of the dbg module as shown ta b l e 1 6 - 6 . see section 16.4.2.5, ?trigger modes ,? for more detail. table 16-6. trigger mode encoding trg value meaning 0000 a only 0001 a or b 0010 a then b 0011 event only b 0100 a then event only b 0101 a and b (full mode) 0110 a and not b (full mode) 0111 inside range 1000 outside range 1001 1111 reserved (defaults to a only) chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 479 16.3.2.3 debug trace buffer register (dbgtb) 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w resetuuuuuuuu = unimplemented or reserved figure 16-6. debug trace buffer register high (dbgtbh) 76543210 rbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w resetuuuuuuuu = unimplemented or reserved figure 16-7. debug trace buffer register low (dbgtbl) table 16-7. dbgtb field descriptions field description 15:0 trace buffer data bits ? the trace buffer data bits contain the data of the trace buffer. this register can be read only as a word read. any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace bu ffer address. the same is true for word reads while the debugger is armed. in addition, this register may appear to contain incorrect data if it is not read with the same capture mode bit settings as when the trace buffer data was recorded (see section 16.4.2.9, ?reading data from trace buffer ?). because reads will reflect the contents of th e trace buffer ram, the reset state is undefined. chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 480 freescale semiconductor 16.3.2.4 debug count register (dbgcnt) 76543210 r tbf 0 cnt w reset00000000 = unimplemented or reserved figure 16-8. debug count register (dbgcnt) table 16-8. dbgcnt field descriptions field description 7 tbf trace buffer full ? the tbf bit indicates that the trace buffer has stored 64 or more words of data since it was last armed. if this bit is set, then all 64 words will be valid data, regardless of the va lue in cnt[5:0]. the tbf bit is cleared when arm in dbgc1 is written to a 1. 5:0 cnt count value ? the cnt bits indicate the number of va lid data words stored in the trace buffer. table 16-9 shows the correlation between the cnt bits and the number of valid data words in t he trace buffer. when the cnt rolls over to 0, the tbf bit will be set and incrementing of cnt will continue if dbg is in end-trigger mode. the dbgcnt register is cleared when arm in dbgc1 is written to a 1. table 16-9. cnt decoding table tbf cnt description 0 000000 no data valid 0 000001 1 word valid 0 000010 .. .. 111110 2 words valid .. .. 62 words valid 0 111111 63 words valid 1 000000 64 words valid; if begin = 1, the arm bit will be cleared. a breakpoint will be generated if dbgbrk = 1 1 000001 .. .. 111111 64 words valid, oldest data has been overwritten by most recent data chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 481 16.3.2.5 debug comparator c extended register (dbgccx) 76543210 r pagsel extcmp w reset00000000 figure 16-9. debug comparator c extended register (dbgccx) table 16-10. dbgccx field descriptions field description 7:6 pagsel page selector field ? in both bkp and dbg mode, pagsel selects the type of paging as shown in ta b l e 1 6 - 1 1 . dpage and epage are not yet implemented so the value in bit 7 will be ignored (i.e., pagsel values of 10 and 11 will be interpreted as values of 00 and 01, respectively). 5:0 extcmp comparator c extended compare bits ? the extcmp bits are used as comparison address bits as shown in table 16-11 along with the appropriate ppage, dpag e, or epage signal from the core. note: comparator c can be used when the dbg module is configured for bkp mode. extended addressing comparisons for comparator c use pagsel and will opera te differently to the way that comparator a and b operate in bkp mode. table 16-11. pagsel decoding 1 1 see figure 16-10 . pagsel description extcmp comment 00 normal (64k) not used no paged memory 01 ppage (256 ? 16k pages) extcmp[5:0] is compared to address bits [21:16] 2 2 current hcs12 implementations have ppage limited to 6 bits. therefore, extcmp[5:4] should be set to 00. ppage[7:0] / xab[21:14] becomes address bits [21:14] 1 10 3 3 data page (dpage) and extra page (epage) are reserved for implementation on devices that support paged data and extra space. dpage (reserved) (256 ? 4k pages) extcmp[3:0] is compared to address bits [19:16] dpage / xab[21:14] becomes address bits [19:12] 11 2 epage (reserved) (256 ? 1k pages) extcmp[1:0] is compared to address bits [17:16] epage / xab[21:14] becomes address bits [17:10] chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 482 freescale semiconductor 16.3.2.6 debug comparator c register (dbgcc) dbgcxx dbgcxh[15:12] pagsel extcmp bit 15 bit 14 bit 13 bit 12 76 0 5 0 4 3 2 1 bit 0 see note 1 portk/xab xab21 xab20 xab19 xab18 xab17 xab16 xab15 xab14 ppage pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 see note 2 notes: 1. in bkp and dbg mode, pagsel selects the type of paging as shown in table 16-11 . 2. current hcs12 implementations are limited to six ppage bits, pix[5:0]. therefore, extcmp[5:4] = 00. figure 16-10. comparator c extended comparison in bkp/dbg mode 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset00000000 = unimplemented or reserved figure 16-11. debug comparator c register high (dbgcch) 76543210 rbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000 = unimplemented or reserved figure 16-12. debug comparator c register low (dbgccl) table 16-12. dbgcc field descriptions field description 15:0 comparator c compare bits ? the comparator c compare bits cont rol whether comparator c will compare the address bus bits [15:0] to a logic 1 or logic 0. see table 16-13 . 0 compare corresponding address bit to a logic 0 1 compare corresponding address bit to a logic 1 note: this register will be cleared automatically wh en the dbg module is armed in loop1 mode. bkp/dbg mode chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 483 16.3.2.7 debug control register 2 (dbgc2) figure 16-13. debug control register 2 (dbgc2) table 16-13. comparator c compares pagsel extcmp compare h igh-byte compare x0 no compare dbgcch[7:0] = ab[15:8] x1 extcmp[5:0] = xab[21 :16] dbgcch[7:0] = xab[15:14],ab[13:8] 76543210 r bkaben 1 1 when bkaben is set (bkp mode), all bits in dbgc2 are available. when bkaben is cleared and dbg is used in dbg mode, bits full and tagab have no meaning. full bdm tagab bkcen 2 2 these bits can be used in bkp mode and db g mode (when capture mode is not set in loop1) to provide a third breakpoint. tag c 2 rwcen 2 rwc 2 w reset00000000 table 16-14. dbgc2 field descriptions field description 7 bkaben breakpoint using comp arator a and b enable ? this bit enables the breakpoint capability using comparator a and b, when set (bkp mode) the dbgen bit in dbgc1 cannot be set. 0 breakpoint module off 1 breakpoint module on 6 full full breakpoint mode enable ? this bit controls whether the breakpoint module is in dual mode or full mode. in full mode, comparator a is used to match add ress and comparator b is used to match data. see section 16.4.1.2, ?full breakpoint mode ,? for more details. 0 dual address mode enabled 1 full breakpoint mode enabled 5 bdm background debug mode enable ? this bit determines if the breakpoint causes the system to enter background debug mode (bdm) or initiate a software interrupt (swi). 0 go to software interrupt on a break request 1 go to bdm on a break request 4 tag a b comparator a/b tag select ? this bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executab le opcode (tagged). non-execut ed opcodes cannot cause a tagged breakpoint. 0 on match, break at the next instruction boundary (force) 1 on match, break if/when the instruct ion is about to be executed (tagged) 3 bkcen breakpoint comparator c enable bit ? this bit enables the breakpoint capability using comparator c. 0 comparator c disabled for breakpoint 1 comparator c enabled for breakpoint note: this bit will be cleared automatically when the dbg module is armed in loop1 mode. 2 tag c comparator c tag select ? this bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executab le opcode (tagged). non-execut ed opcodes cannot cause a tagged breakpoint. 0 on match, break at the next instruction boundary (force) 1 on match, break if/when the instruct ion is about to be executed (tagged) chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 484 freescale semiconductor 16.3.2.8 debug control register 3 (dbgc3) figure 16-14. debug control register 3 (dbgc3) 1 rwcen read/write comparator c enable bit ? the rwcen bit controls whether read or write comparison is enabled for comparator c. rwcen is not useful for tagged breakpoints. 0 read/write is not used in comparison 1 read/write is used in comparison 0 rwc read/write comparator c value bit ? the rwc bit controls whether read or write is used in compare for comparator c. the rwc bit is not used if rwcen = 0. 0 write cycle will be matched 1 read cycle will be matched 76543210 r bkambh 1 1 in dbg mode, bkambh:bkambl has no meaning and are forced to 0?s. bkambl 1 bkbmbh 2 2 in dbg mode, bkbmbh:bkbmbl are used in full mode to qualify data. bkbmbl 2 rwaen rwa rwben rwb w reset00000000 table 16-15. dbgc3 field descriptions field description 7:6 bkamb[h:l] breakpoint mask high byte for first address ? in dual or full mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the first address breakpoint. the functionality is as given in ta b l e 1 6 - 1 6 . the x:0 case is for a full address compare. when a prog ram page is selected, the full address compare will be based on bits for a 20-bit compare. the registers us ed for the compare are {d bgcax[5:0], dbgcah[5:0], dbgcal[7:0]}, where dbgax[5:0] corresponds to ppag e[5:0] or extended address bits [19:14] and cpu address [13:0]. when a program page is not selected, the fu ll address compare will be based on bits for a 16-bit compare. the registers used for the compare are {d bgcah[7:0], dbgcal[7:0]} which corresponds to cpu address [15:0]. note: this extended address compare scheme causes an aliasing problem in bkp mode in which several physical addresses may match with a single logical address. this problem may be avoided by using dbg mode to generate breakpoints. the 1:0 case is not sensible because it would ignor e the high order address and compare the low order and expansion addresses. logic forces this case to compar e all address lines (effectively ignoring the bkambh control bit). the 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. this only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if dbgcax compares. table 16-14. dbgc2 field descriptions (continued) field description chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 485 5:4 bkbmb[h:l] breakpoint mask high by te and low byte of data (second address) ? in dual mode, these bits may be used to mask (disable) the comparison of the high a nd/or low bytes of the second address breakpoint. the functionality is as given in table 16-17 . the x:0 case is for a full address compare. when a prog ram page is selected, the full address compare will be based on bits for a 20-bit compare. the registers us ed for the compare are {d bgcbx[5:0], dbgcbh[5:0], dbgcbl[7:0]} where dbgcbx[5:0] corresponds to ppag e[5:0] or extended addre ss bits [19:14] and cpu address [13:0]. when a program page is not selected, the fu ll address compare will be based on bits for a 16-bit compare. the registers used for the compare are {d bgcbh[7:0], dbgcbl[7:0]} which corresponds to cpu address [15:0]. note: this extended address compare scheme causes an aliasing problem in bkp mode in which several physical addresses may match with a single logical address. this problem may be avoided by using dbg mode to generate breakpoints. the 1:0 case is not sensible because it would ignor e the high order address and compare the low order and expansion addresses. logic forces this case to compar e all address lines (effectively ignoring the bkbmbh control bit). the 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. this only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if dbgcbx compares. in full mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data breakpoint. the functionality is as given in table 16-18 . 3 rwaen read/write comparator a enable bit ? the rwaen bit controls whether read or write comparison is enabled for comparator a. see section 16.4.2.1.1, ?read or write comparison ,? for more information. this bit is not useful for tagged operations. 0 read/write is not used in comparison 1 read/write is used in comparison 2 rwa read/write comparator a value bit ? the rwa bit controls whether read or write is used in compare for comparator a. the rwa bit is not used if rwaen = 0. 0 write cycle will be matched 1 read cycle will be matched 1 rwben read/write comparator b enable bit ? the rwben bit controls whether read or write comparison is enabled for comparator b. see section 16.4.2.1.1, ?read or write comparison ,? for more information. this bit is not useful for tagged operations. 0 read/write is not used in comparison 1 read/write is used in comparison 0 rwb read/write comparator b value bit ? the rwb bit controls whether read or write is used in compare for comparator b. the rwb bit is not used if rwben = 0. 0 write cycle will be matched 1 read cycle will be matched note: rwb and rwben are not used in full mode. table 16-16. breakpoint mask bits for first address bkambh:bkambl address compare dbgcax dbgcah dbgcal x:0 full address compare yes 1 1 if ppage is selected. ye s ye s 0:1 256 byte address range yes 1 ye s n o 1:1 16k byte address range yes 1 no no table 16-15. dbgc3 field descriptions (continued) field description chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 486 freescale semiconductor table 16-17. breakpoint mask bits for second address (dual mode) bkbmbh:bkbmbl address compare dbgcbx dbgcbh dbgcbl x:0 full address compare yes 1 1 if ppage is selected. ye s ye s 0:1 256 byte address range yes 1 ye s n o 1:1 16k byte address range yes 1 no no table 16-18. breakpoint mask bits for data breakpoints (full mode) bkbmbh:bkbmbl data compare dbgcbx dbgcbh dbgcbl 0:0 high and low byte compare no 1 1 expansion addresses for breakpoint b are not applicable in this mode. ye s ye s 0:1 high byte no 1 ye s n o 1:0 low byte no 1 no yes 1:1 no compare no 1 no no chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 487 16.3.2.9 debug comparator a extended register (dbgcax) 76543210 r pagsel extcmp w reset00000000 figure 16-15. debug comparator a extended register (dbgcax) table 16-19. dbgcax field descriptions field description 7:6 pagsel page selector field ? if dbgen is set in dbgc1, then pagsel selects the type of paging as shown in ta b l e 1 6 - 2 0 . dpage and epage are not yet implemented so the value in bit 7 will be ignored (i.e., pagsel values of 10 and 11 will be interpreted as values of 00 and 01, respectively). in bkp mode, pagsel has no meaning and extcmp[5:0] are compared to address bits [19:14] if the address is in the flash/rom memory space. 5:0 extcmp comparator a extended compare bits ? the extcmp bits are used as comparison address bits as shown in table 16-20 along with the appropriate ppage, dpag e, or epage signal from the core. table 16-20. comparator a or b compares mode extcmp compare high-byte compare bkp 1 1 see figure 16-16 . not flash/rom access no compare dbgcxh[7:0] = ab[15:8] flash/rom access extcmp[5:0] = xab[19:14] dbgcxh[5:0] = ab[13:8] dbg 2 2 see figure 16-10 (note that while this figure provides extended comparis ons for comparator c, the figure also pertains to comparators a and b in dbg mode only). pagsel = 00 no compar e dbgcxh[7:0] = ab[15:8] pagsel = 01 extcmp[5:0] = xab[21:1 6] dbgcxh[7:0] = xab[ 15:14], ab[13:8] pagsel extcmp dbgcxx 0 0 54321bit 0 see note 1 portk/xab xab21 xab20 xab19 xab18 xab17 xab16 xab15 xab14 ppage pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 see note 2 notes: 1. in bkp mode, pagsel has no functionality. therefore, set pagsel to 00 (reset state). 2. current hcs12 implementations are limited to six ppage bits, pix[5:0]. figure 16-16. comparators a and b extended comparison in bkp mode bkp mode chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 488 freescale semiconductor 16.3.2.10 debug comparator a register (dbgca) 16.3.2.11 debug comparator b extended register (dbgcbx) 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset00000000 figure 16-17. debug comparator a register high (dbgcah) 76543210 r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000 figure 16-18. debug comparator a register low (dbgcal) table 16-21. dbgca field descriptions field description 15:0 15:0 comparator a compare bits ? the comparator a compare bits contro l whether comparator a compares the address bus bits [15:0] to a logic 1 or logic 0. see ta b l e 1 6 - 2 0 . 0 compare corresponding address bit to a logic 0 1 compare corresponding address bit to a logic 1 76543210 r pagsel extcmp w reset00000000 figure 16-19. debug comparator b extended register (dbgcbx) table 16-22. dbgcbx field descriptions field description 7:6 pagsel page selector field ? if dbgen is set in dbgc1, then pagsel selects the type of paging as shown in ta b l e 1 6 - 1 1 . dpage and epage are not yet implemented so the value in bit 7 will be ignored (i.e., pagsel values of 10 and 11 will be interpreted as values of 00 and 01, respectively.) in bkp mode, pagsel has no meaning and extcmp[5:0] are compared to address bits [19:14] if the address is in the flash/rom memory space. 5:0 extcmp comparator b extended compare bits ? the extcmp bits are used as comparison address bits as shown in table 16-11 along with the appropriate ppage, dpage, or epage signal from the core. also see table 16-20 . chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 489 16.3.2.12 debug comparator b register (dbgcb) 16.4 functional description this section provides a complete functional descri ption of the dbg module. the dbg module can be configured to run in either of two modes, bkp or dbg. bkp mode is enable d by setting bkaben in dbgc2. dbg mode is enabled by se tting dbgen in dbgc1. setting bkaben in dbgc2 overrides the dbgen in dbgc1 and prevents dbg mode. if the part is in secure mode, dbg mode cannot be enabled. 16.4.1 dbg operating in bkp mode in bkp mode, the dbg will be fully backwards co mpatible with the existi ng bkp_st12_a module. the dbgc2 register has four additional bits that were not available on existi ng bkp_st12_a modules. as long as these bits are written to eith er all 1s or all 0s, they should be transparent to the user. all 1s would enable comparator c to be used as a breakpoint, but tagging would be enabled. th e match address register would be all 0s if not modified by the user. ther efore, code executing at address 0x0000 would have to occur before a breakpoint base d on comparator c would happen. the dbg module in bkp mode supports two modes of op eration: dual address m ode and full breakpoint mode. within each of these modes, forced or tagge d breakpoint types can be used. forced breakpoints occur at the next instruction bounda ry if a match occurs and tagged breakpoints allow for breaking just before the tagged instructi on executes. the action taken upon a successful match can be to either place the cpu in background debug mode or to initiate a software interrupt. 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset00000000 figure 16-20. debug comparator b register high (dbgcbh) 76543210 r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000 figure 16-21. debug comparator b register low (dbgcbl) table 16-23. dbgcb field descriptions field description 15:0 15:0 comparator b compare bits ? the comparator b compare bits contro l whether comparator b compares the address bus bits [15:0] or data bus bits [15:0] to a logic 1 or logic 0. see table 16-20 . 0 compare corresponding address bit to a logic 0, compares to data if in full mode 1 compare corresponding address bit to a logic 1, compares to data if in full mode chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 490 freescale semiconductor the breakpoint can operate in dual address mode or full breakpoint mode. each of these modes is discussed in the subsections below. 16.4.1.1 dual address mode when dual address mode is enabled, two address brea kpoints can be set. each breakpoint can cause the system to enter background debug mode or to initiate a software interr upt based upon the state of bdm in dbgc2 being logic 1 or logic 0, resp ectively. bdm requests have a higher priority than swi requests. no data breakpoints are al lowed in this mode. tagab in dbgc2 selects whether th e breakpoint mode is forced or tagged. the bkxmbh:l bits in dbgc3 select whether or not the breakpoint is matched exactly or is a range breakpoint. they also select whether the address is matched on the high byte, lo w byte, both bytes, and/or memory expansion. the rwx and rwxen bits in dbgc3 select whether the t ype of bus cycle to match is a read, write, or read/write when performing forced breakpoints. 16.4.1.2 full breakpoint mode full breakpoint mode requires a match on address and da ta for a breakpoint to occur. upon a successful match, the system will enter backgr ound debug mode or initiate a softwa re interrupt based upon the state of bdm in dbgc2 being l ogic 1 or logic 0, respectively. bdm reque sts have a higher priority than swi requests. r/w matches are al so allowed in this mode. tagab in dbgc2 selects whether th e breakpoint mode is forced or tagged. when tagab is set in dbgc2, only addresses are compared and data is ignored. the bkambh:l bits in dbgc3 select whether or not the breakpoint is ma tched exactly, is a range breakpoin t, or is in page space. the bkbmbh:l bits in dbgc3 select whether the data is matched on the high byte, low byt e, or both bytes. rwa and rwaen bits in dbgc 2 select whether the type of bus cycle to match is a read or a write when performing forced breakpoin ts. rwb and rwben bits in dbgc2 are not used in full breakpoint mode. note the full trigger mode is designed to be used for either a word access or a byte access, but not both at the same time. confusing trigger operation (seemingly false triggers or no trigge r) can occur if the trigger address occurs in the user program as both byte and word accesses. 16.4.1.3 breakpoint priority breakpoint operation is first determ ined by the state of the bdm modul e. if the bdm module is already active, meaning the cpu is executing out of bdm firmware, breakpoints are not allowed. in addition, while executing a bdm trace command, tagging into bdm is not allowed. if bdm is not active, the breakpoint will give priority to bdm requests over swi requests. this condition applies to both forced and tagged breakpoints. in all cases, bdm related breakpoints will have priority ove r those generated by th e breakpoint sub-block. this priority includes brea kpoints enabled by the taglo and taghi external pins of the system that interface with the bdm directly and whose signal information passes through and is used by the breakpoint sub-block. chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 491 note bdm should not be entered from a br eakpoint unless the enable bit is set in the bdm. even if the enable bit in the bdm is cleared, the cpu actually executes the bdm firmware code. it checks the enable and returns if enable is not set. if the bd m is not serviced by the monitor then the breakpoint would be re-asserted wh en the bdm returns to normal cpu flow. there is no hardware to enforce restri ction of breakpoint operation if the bdm is not enabled. when program control re turns from a tagged breakpoi nt through an rti or a bdm go command, it will return to the instruct ion whose tag generated the breakpoint. unless breakpoints are di sabled or modified in the service routine or active bdm sessi on, the instruction will be tagged again and the breakpoint will be repeat ed. in the case of bdm br eakpoints, this situation can also be avoided by executing a trace1 command before the go to increment the program flow past the tagged instruction. 16.4.1.4 using comparator c in bkp mode the original bkp_st12_a module supports two brea kpoints. the dbg_st12_a module can be used in bkp mode and allow a third brea kpoint using comparator c. four additional bits, bkcen, tagc, rwcen, and rwc in dbgc2 in conjunction with addi tional comparator c addr ess registers, dbgccx, dbgcch, and dbgccl allow the user to set up a third breakpoint. using pa gsel in dbgccx for expanded memory will work differently than the way paged memory is done using comparator a and b in bkp mode. see section 16.3.2.5, ?debug comparator c extended register (dbgccx) ,? for more information on using comparator c. 16.4.2 dbg operating in dbg mode enabling the dbg module in dbg mode, allows the armi ng, triggering, and storing of data in the trace buffer and can be used to cause cpu breakpoints. th e dbg module is made up of three main blocks, the comparators, trace buffer contro l logic, and the trace buffer. note in general, there is a latency between the triggering even t appearing on the bus and being detected by the dbg circuitry. in ge neral, tagged triggers will be more predictable than forced triggers. 16.4.2.1 comparators the dbg contains three comp arators, a, b, and c. comparator a co mpares the core address bus with the address stored in dbgcah and dbgc al. comparator b compares the co re address bus with the address stored in dbgcbh and dbg cbl except in full mode, where it compar es the data buses to the data stored in dbgcbh and dbgcbl. comparator c can be used as a breakpoint generator or as the address comparison unit in the loop1 mode. matches on comparat or a, b, and c are signaled to the trace buffer chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 492 freescale semiconductor control (tbc) block. when pagsel = 01, register s dbgcax, dbgcbx, and dbgccx are used to match the upper addresses as shown in table 16-11 . note if a tagged-type c breakpoint is se t at the same address as an a/b tagged-type trigger (includi ng the initial entry in an inside or outside range trigger), the c breakpoint will have pr iority and the trigger will not be recognized. 16.4.2.1.1 read or write comparison read or write comparisons are useful only with trgsel = 0, because only opc odes should be tagged as they are ?read? from memory. rwaen and rwben are ignored when trgsel = 1. in full modes (?a and b? and ?a and not b?) rw aen and rwa are used to select read or write comparisons for both comparators a and b. table 16-24 shows the effect for rwaen, rwa, and rw on the dbgcb comparison conditions. the rwben and rwb bits are not used and are ignored in full modes. 16.4.2.1.2 trigger selection the trgsel bit in dbgc1 is used to determine the triggering cond ition in dbg mode. trgsel applies to both trigger a and b except in the event only tr igger modes. by setting trgsel, the comparators a and b will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged instruction executes (tagged-type trigger). with the trgsel bit cleared, a comparator match forces a trigger when the matching conditi on occurs (force-type trigger). note if the trgsel is set, the address stor ed in the comparator match address registers must be an opcode a ddress for the trigger to occur. 16.4.2.2 trace buffer control (tbc) the tbc is the main controller for the dbg module. its functi on is to decide whether data should be stored in the trace buffer based on the trigger mode and th e match signals from the comparator. the tbc also determines whether a request to break the cpu should occur. table 16-24. read or write comparison logic table rwaen bit rwa bit rw signal comment 0 x 0 write data bus 0 x 1 read data bus 1 0 0 write data bus 1 0 1 no data bus compare since rw=1 1 1 0 no data bus compare since rw=0 1 1 1 read data bus chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 493 16.4.2.3 begin- and end-trigger the definitions of begin- a nd end-trigger as used in th e dbg module are as follows: ? begin-trigger: storage in trace buffer occurs after the trigger a nd continues until 64 locations are filled. ? end-trigger: storage in trace buffer occurs until th e trigger, with the least recent data falling out of the trace buffer if more than 64 words are collected. 16.4.2.4 arming the dbg module in dbg mode, arming occurs by setting dbgen and ar m in dbgc1. the arm bit in dbgc1 is cleared when the trigger condition is met in end-trigger mode or when the trace bu ffer is filled in begin-trigger mode. the tbc logic determ ines whether a trigger c ondition has been met based on the trigger mode and the trigger selection. 16.4.2.5 trigger modes the dbg module supports nine trigger modes. the trigger modes are encoded as shown in table 16-6 . the trigger mode is used as a qualifier for either star ting or ending the storing of data in the trace buffer. when the match condition is met, th e appropriate flag a or b is set in dbgsc. arming the dbg module clears the a, b, and c flags in dbgsc. in all tri gger modes except for the event-only modes and detail capture mode, change-of-flow addre sses are stored in the trace buffer. in the event-only modes only the value on the data bus at the trigger event b will be stored. in detail capture mode address and data for all cycles except program fetch (p) and fr ee (f) cycles are stored in trace buffer. 16.4.2.5.1 a only in the a only trigger mode, if the match condition for a is met, the a flag in dbgsc is set and a trigger occurs. 16.4.2.5.2 a or b in the a or b trigger mode, if th e match condition for a or b is met, the corresponding flag in dbgsc is set and a trigger occurs. 16.4.2.5.3 a then b in the a then b trigger mode, the match condition for a must be met before th e match condition for b is compared. when the match condition for a or b is met, the corresponding flag in dbgsc is set. the trigger occurs only after a then b have matched. note when tagging and using a then b, if addresses a and b ar e close together, then b may not complete the trigger sequence. this occurs when a and b are in the instruction queue at the same time. basically the a trigger has not yet occurred, so the b instru ction is not tagged. genera lly, if address b is at chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 494 freescale semiconductor least six addresses higher than address a (or b is lower than a) and there are not changes of flow to put these in the queue at the same time, then this operation should trigger properly. 16.4.2.5.4 event-only b (store data) in the event-only b trigger mode, if the match conditi on for b is met, the b flag in dbgsc is set and a trigger occurs. the event-only b tri gger mode is considered a begin-tr igger type and the begin bit in dbgc1 is ignored. event-only b is incompatible with instruction ta gging (trgsel = 1), and thus the value of trgsel is i gnored. please refer to section 16.4.2.7, ?storage memory ,? for more information. this trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority. trgsel and begin will not be ignored and this trigger mode will behave as if it were ?b only?. 16.4.2.5.5 a then event -only b (store data) in the a then event-only b trigge r mode, the match condition for a must be met before the match condition for b is compared, after the a match has occurred, a trigger occurs each time b matches. when the match condition for a or b is met, the corresponding flag in dbgsc is set. the a then event-only b trigger mode is considered a begin-trigger t ype and begin in dbgc1 is ignore d. trgsel in dbgc1 applies only to the match condition for a. please refer to section 16.4.2.7, ?storage memory ,? for more information. this trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority. trgsel and begin will not be ignored and this trigger mode will be the same as a then b. 16.4.2.5.6 a and b (full mode) in the a and b trigger mode, comparator a compares to the address bus and co mparator b compares to the data bus. in the a and b trigge r mode, if the match c ondition for a and b happen on the same bus cycle, both the a and b flags in the dbgsc re gister are set and a trigger occurs. if trgsel = 1, only matches from comp arator a are used to determine if the trigger condition is met and comparator b matches are ignore d. if trgsel = 0, full-word data matches on an odd address boundary (misaligned access) do not work unless the access is to a ram that manages misaligned accesses in a single clock cycle (which is typical of ram modules used in hcs12 mcus). 16.4.2.5.7 a and not b (full mode) in the a and not b trigger mode, comparator a compares to the a ddress bus and comparator b compares to the data bus. in the a and not b trigger mode, if the match condition for a and not b happen on the same bus cycle, both the a and b flags in dbgsc are set and a trigger occurs. if trgsel = 1, only matches from comp arator a are used to determine if the trigger condition is met and comparator b matches are ignored. as described in section 16.4.2.5.6, ?a and b (full mode) ,? full-word data compares on misaligned accesses will not match expected data (a nd thus will cause a trigger in this mode) unless the access is to a ram that mana ges misaligned accesses in a single clock cycle. chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 495 16.4.2.5.8 inside range (a address b) in the inside range trigger mode, if the match c ondition for a and b happen on the same bus cycle, both the a and b flags in dbgsc are set and a trigger occurs. if a match c ondition on only a or only b occurs no flags are set. if trgsel = 1, the inside range is accurate only to word boundaries. if trgsel = 0, an aligned word access which straddles the range boundary w ill cause a trigger only if the aligned address is within the range. 16.4.2.5.9 outside range (a ddress < a or address > b) in the outside range trigger mode, if the match c ondition for a or b is met, the corresponding flag in dbgsc is set and a trigger occurs. if trgsel = 1, the outsi de range is accurate only to word boundaries. if trgsel = 0, an aligned word acc ess which straddles the range boundary will cause a trigger only if the aligned address is outside the range. 16.4.2.5.10 control bit priorities the definitions of some of the control bits are incompatible with each other. table 16-25 and the notes associated with it summarize how these incompatibilities are managed: ? read/write comparisons are not compatible wi th trgsel = 1. therefore, rwaen and rwben are ignored. ? event-only trigger modes are always considered a begin-type trigger. see section 16.4.2.8.1, ?storing with begin-trigger ,? and section 16.4.2.8.2, ?storing with end-trigger .? ? detail capture mode has priority over the event- only trigger/capture modes. therefore, event-only modes have no meaning in detail mode and thei r functions default to similar trigger modes. table 16-25. resolution of mode conflicts mode normal / loop1 detail tag force tag force a only a or b a then b event-only b 1 1, 3 3 a then event-only b 2 4 4 a and b (full mode) 5 5 a and not b (full mode) 5 5 inside range 6 6 outside range 6 6 1 ? ignored ? same as force 2 ? ignored for comparator b 3 ? reduces to effectively ?b only? 4 ? works same as a then b 5 ? reduces to effectively ?a only? ? b not compared 6 ? only accurate to word boundaries chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 496 freescale semiconductor 16.4.2.6 capture modes the dbg in dbg mode can operate in four capture modes. these modes are described in the following subsections. 16.4.2.6.1 normal mode in normal mode, the dbg module uses comparator a and b as triggering de vices. change-of-flow information or data will be stored depending on trg in dbgsc. 16.4.2.6.2 loop1 mode the intent of loop1 mode is to preven t the trace buffer from being filled entirely with duplicate information from a looping construct such as delays using the dbne inst ruction or polling loops using brset/brclr instructions. im mediately after address in formation is placed in the trace buffer, the dbg module writes this value into the c comparator and the c comparator is placed in ignore address mode. this will prevent duplicate address entries in the trace buffer resulting from repeated bit-conditional branches. comparator c will be cl eared when the arm bit is set in loop1 mode to prevent the previous contents of the register from interfering with loop1 mode operation. breakpoi nts based on comparator c are disabled. loop1 mode only inhibits duplicate sour ce address entries that would typi cally be stored in most tight looping constructs. it will not inhibit repeated entries of destination addresses or vector addresses, because repeated entries of these would most likely indicate a bug in the user?s code that the dbg module is designed to help find. note in certain very tight loops , the source address will have already been fetched again before the c comparator is update d. this results in the source address being stored twice before further duplicate entries are suppressed. this condition occurs with branch-on-bit inst ructions when the branch is fetched by the first p-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second p cycle. see examples below: loop incx ; 1-byte instruction fetched by 1st p-cycle of brclr brclr cmptmp,#$0c,loop ; the brclr instruction also will be fetched by 1st p-cycle of brclr loop2 brn * ; 2-byte instruction fetched by 1st p-cycle of dbne nop ; 1-byte instruction fetched by 2nd p-cycle of dbne dbne a,loop2 ; this instruction also fetched by 2nd p-cycle of dbne note loop1 mode does not support paged memory, and inhi bits duplicate entries in the trace buffer based solely on the cpu address. there is a remote possibility of an errone ous address match if pr ogram flow alternates between paged and unpaged memory space. chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 497 16.4.2.6.3 detail mode in the detail mode, address and data for all cycles ex cept program fetch (p) and fr ee (f) cycles are stored in trace buffer. this mode is intended to supply a dditional information on inde xed, indirect addressing modes where storing only the destina tion address would not pr ovide all information re quired for a user to determine where his code was in error. 16.4.2.6.4 profile mode this mode is intended to allow a host computer to poll a running targ et and provide a hi stogram of program execution. each read of the trace buffe r address will return the address of the last instruction executed. the dbgcnt register is not incremente d and the trace buffer does not get filled. the arm bit is not used and all breakpoints and all other debug functions will be disabled. 16.4.2.7 storage memory the storage memory is a 64 words deep by 16-bits wide dual port ram array. th e cpu accesses the ram array through a single memory location window (d bgtbh:dbgtbl). the dbg module stores trace information in the ram array in a circular buffer format . as data is read via the cpu, a pointer into the ram will increment so that the next cpu read will receive fres h information. in all trigger modes except for event-only and detail capture mode, the data stored in the trace buffer will be change-of-flow addresses. change-of-flow addresses are defined as follows: ? source address of conditional branches (long, short, brset, and l oop constructs) taken ? destination address of indexed jmp, jsr, and call instruction ? destination address of rti, rts, and rtc instructions ? vector address of interrupts except for swi and bdm vectors in the event-only trigger modes only th e 16-bit data bus valu e corresponding to the ev ent is stored. in the detail capture mode, address and then data are stored for all cycles ex cept program fetch (p) and free (f) cycles. 16.4.2.8 storing data in memory storage buffer 16.4.2.8.1 storing with begin-trigger storing with begin-trigger can be used in all trigge r modes. when dbg mode is enabled and armed in the begin-trigger mode, data is not stored in the trace buffer until the trigger condition is me t. as soon as the trigger condition is met, the dbg m odule will remain armed until 64 word s are stored in the trace buffer. if the trigger is at the address of the change-of-flow instruction the change-of-flow associated with the trigger event will be stored in the trace buffer. 16.4.2.8.2 storing with end-trigger storing with end-trigger cannot be used in event- only trigger modes. when dbg mode is enabled and armed in the end-trigger mode, data is stored in the trace buffer until the trigger condition is met. when the trigger condition is met, the dbg module will become de-armed and no more data will be stored. if chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 498 freescale semiconductor the trigger is at the address of a ch ange-of-flow address the trigger even t will not be stored in the trace buffer. 16.4.2.9 reading data from trace buffer the data stored in the trace buffer can be read using either the backgr ound debug module (bdm) module or the cpu provided the dbg module is enabled and not armed. the trace buffer data is read out first-in first-out. by reading cnt in dbgcnt the number of valid words can be determined. cnt will not decrement as data is read from dbgtbh:dbgtb l. the trace buffer data is read by reading dbgtbh:dbgtbl with a 16-bit read. each time dbgt bh:dbgtbl is read, a pointer in the dbg will be incremented to allow reading of the next word. reading the trace buffer while the dbg module is armed will return invalid data and no shifting of the ram pointer will occur. note the trace buffer should be read with the dbg module enabled and in the same capture mode that the data was recorded. the contents of the trace buffer counter register (dbgcnt) are re solved differently in detail mode verses the other modes and may lead to incorrect interpretation of the trace buffer data. 16.4.3 breakpoints there are two ways of getting a breakpoint in dbg mode. one is based on the trigger condition of the trigger mode using comparator a a nd/or b, and the other is using co mparator c. external breakpoints generated using the taghi and taglo external pins are disabled in dbg mode. 16.4.3.1 breakpoint based on comparator a and b a breakpoint request to the cpu ca n be enabled by setting dbgbrk in dbgc1. the value of begin in dbgc1 determines when the breakpoint request to th e cpu will occur. when begin in dbgc1 is set, begin-trigger is selected and the breakpoint request will not occur unt il the trace buffe r is filled with 64 words. when begin in dbgc1 is cleared, end-trigger is selected and the breakpoi nt request will occur immediately at the trigger cycle. there are two types of breakpoint requests suppor ted by the dbg module, tagged and forced. tagged breakpoints are associated with opcode addresses and allow breaking just before a specific instruction executes. forced breakpoints are not associated with opcode addresse s and allow breaking at the next instruction boundary. the type of breakpoint based on comparators a an d b is determined by trgsel in the dbgc1 register (trgsel = 1 for tagged breakpoint, trgsel = 0 for forced breakpoint). table 16-26 illustrates the type of breakpoint that will occur based on the debug run. chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 499 16.4.3.2 breakpoint based on comparator c a breakpoint request to the cpu can be created if bkcen in dbgc2 is set. breakpoints based on a successful comparator c match can be accomplished re gardless of the mode of operation for comparator a or b, and do not affect the status of the arm bit. tagc in dbgc2 is used to select either tagged or forced breakpoint requests for comp arator c. breakpoints based on comp arator c are disabled in loop1 mode. note because breakpoints cannot be disabled when the dbg is armed, one must be careful to avoid an ?infinite breakpoint loop? when using tagged-type c breakpoints while the dbg is armed. if bdm breakpoints are selected, executing a trace1 instruction before the go instruction is the recommended way to avoi d re-triggering a breakpoint if one does not wish to de-arm the dbg. if swi breakpoint s are selected, disarming the dbg in the swi interrupt service routine is the recommended way to avoid re-triggering a breakpoint. 16.5 resets the dbg module is disabled after reset. the dbg module cannot cause a mcu reset. 16.6 interrupts the dbg contains one interrupt sour ce. if a breakpoint is requested and bdm in dbgc2 is cleared, an swi interrupt will be generated. table 16-26. breakpoint setup begin trgsel dbgbrk type of debug run 0 0 0 fill trace buffer until trigger address (no cpu breakpoint ? keep running) 0 0 1 fill trace buffer until trigger address, then a forced breakpoint request occurs 0 1 0 fill trace buffer until trigger opcode is about to execute (no cpu breakpoint ? keep running) 0 1 1 fill trace buffer until trigger opcode about to execute, then a tagged breakpoint request occurs 1 0 0 start trace buffer at trigger address (no cpu breakpoint ? keep running) 1 0 1 start trace buffer at trigger address, a forced breakpoint request occurs when trace buffer is full 1 1 0 start trace buffer at trigger opcode (no cpu breakpoint ? keep running) 1 1 1 start trace buffer at trigger opcode, a forced breakpoint request occurs when trace buffer is full chapter 16 debug module (dbgv1) mc9s12e256 data sheet, rev. 1.08 500 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 501 chapter 17 interrupt (intv1) 17.1 introduction this section describes the functiona lity of the interrupt (int) sub- block of the s12 core platform. a block diagram of the interrupt sub-block is shown in figure 17-1 . figure 17-1. intv1 block diagram hprio (optional) int priority decoder vector request interrupts reset flags write data bus hprio vector xmask imask qualified interrupt input registers interrupts and control registers highest priority i-interrupt read data bus wakeup vector address interrupt pending chapter 17 interrupt (intv1) mc9s12e256 data sheet, rev. 1.08 502 freescale semiconductor the interrupt sub-block decodes the priority of all system exception requests a nd provides the applicable vector for processing the exception. the int supports i-bit maskable and x-bit maskable interrupts, a non-maskable unimplemented opcod e trap, a non-maskable software interrupt (swi) or background debug mode request, and three system reset vector requests. all interrupt related exception requests are managed by the interrupt sub-block (int). 17.1.1 features the int includes these features: ? provides two to 122 i-bit maskable interrupt vectors (0xff00?0xfff2) ? provides one x-bit maskable interrupt vector (0xfff4) ? provides a non-maskable software interrupt (s wi) or background debug mode request vector (0xfff6) ? provides a non-maskable unimplemented opcode trap (trap) vector (0xfff8) ? provides three system reset vectors (0xfffa?0xfffe) (res et, cmr, and cop) ? determines the appropriate vector and drives it onto the address bus at the appropriate time ? signals the cpu that interrupts are pending ? provides control registers whic h allow testing of interrupts ? provides additional input signals which preven ts requests for servicing i and x interrupts ? wakes the system from stop or wa it mode when an appropriate in terrupt occurs or whenever xirq is active, even if xirq is masked ? provides asynchronous path for all i and x interrupts, (0xff00?0xfff4) ? (optional) selects and stores th e highest priority i interrupt ba sed on the value written into the hprio register 17.1.2 modes of operation the functionality of the in t sub-block in various mode s of operation is discusse d in the subsections that follow. ? normal operation the int operates the same in all normal modes of operation. ? special operation interrupts may be tested in special modes th rough the use of the interrupt test registers. ? emulation modes the int operates the same in emul ation modes as in normal modes. ? low power modes see section 17.4.1, ?low-power modes ,? for details chapter 17 interrupt (intv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 503 17.2 external signal description most interfacing with the interrupt sub-block is done within the core. however, the interrupt does receive direct input from the multiplexed external bus in terface (mebi) sub-block of the core for the irq and xirq pin data. 17.3 memory map and register definition detailed descriptions of the registers and associat ed bits are given in the subsections that follow. 17.3.1 module memory map 17.3.2 register descriptions table 17-1. int memory map address offset use access 0x0015 interrupt test cont rol register (itcr) r/w 0x0016 interrupt test registers (itest) r/w 0x001f highest priority interrupt (optional) (hprio) r/w address name bit 7 6 5 4 3 2 1 bit 0 0x0015 itcr r0 0 0 wrtint adr3 adr2 adr1 adr0 w 0x0016 itest r inte intc inta int8 int6 int4 int2 int0 w 0x001f hprio (optional) r psel7 psel6 psel5 psel4 psel3 psel2 psel1 0 w = unimplemented or reserved figure 17-2. int register summary chapter 17 interrupt (intv1) mc9s12e256 data sheet, rev. 1.08 504 freescale semiconductor 17.3.2.1 interrupt test control register read: see individual bit descriptions write: see individua l bit descriptions 76543210 r0 0 0 wrtint adr3 adr2 adr1 adr0 w reset00001111 = unimplemented or reserved figure 17-3. interrupt test control register (itcr) table 17-2. itcr field descriptions field description 4 wrtint write to the interrupt test registers read: anytime write: only in special modes and with i-bit mask and x-bit mask set. 0 disables writes to the test registers; reads of the te st registers will return the state of the interrupt inputs. 1 disconnect the interrupt inputs from the priority decod er and use the values writte n into the itest registers instead. note: any interrupts which are pending at the time that wrti nt is set will remain until they are overwritten. 3:0 adr[3:0] test register select bits read: anytime write: anytime these bits determine which test register is selected on a read or write. the hexadecimal value written here will be the same as the upper nibble of the lower byte of the vector selects. that is, an ?f ? written into adr[3:0] will select vectors 0xfffe?0xfff0 while a ?7? writte n to adr[3:0] will select vectors 0xff7e?0xff70. chapter 17 interrupt (intv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 505 17.3.2.2 interrupt test registers read: only in special modes. reads will return either the state of th e interrupt inputs of the interrupt sub-block (wrtint = 0) or the valu es written into the test register s (wrtint = 1). re ads will always return 0s in normal modes. write: only in special modes and wi th wrtint = 1 and ccr i mask = 1. 76543210 r inte intc inta int8 int6 int4 int2 int0 w reset00000000 figure 17-4. interrupt test registers (itest) table 17-3. itest field descriptions field description 7:0 int[e:0] interrupt test bits ? these registers are used in special modes for testing the interrupt logic and priority independent of the system configuration. each bit is used to force a specific interrupt vector by writing it to a logic 1 state. bits are named inte through int0 to in dicate vectors 0xffxe through 0xffx0. these bits can be written only in special modes and only with the wrtint bit set (logic 1) in the interrupt test control register (itcr). in addition, i interrupts must be masked using the i bit in the ccr. in this state, the interrupt input lines to the interrupt sub-block will be disconnected and inte rrupt requests will be generated only by this register. these bits can also be read in special modes to view that an interrupt requested by a system block (such as a peripheral block) has reached the int module. there is a test register implemented fo r every eight interrupts in the overall system. all of the test registers share the same address and are individually selected using the val ue stored in the adr[3:0] bits of the interrupt test control register (itcr). note: when adr[3:0] have the value of 0x000f, only bits 2:0 in the itest register will be accessible. that is, vectors higher than 0xfff4 cannot be tested using the test registers and bits 7:3 will always read as a logic 0. if adr[3:0] point to an un implemented test register, writes will have no effect and reads will always return a logic 0 value. chapter 17 interrupt (intv1) mc9s12e256 data sheet, rev. 1.08 506 freescale semiconductor 17.3.2.3 highest priority i interrupt (optional) read: anytime write: only if i mask in ccr = 1 17.4 functional description the interrupt sub-block processes all exception re quests made by the cpu. these exceptions include interrupt vector requests and reset vector requests. each of these ex ception types and their overall priority level is discussed in the subsections below. 17.4.1 low-power modes the int does not contain any user-c ontrolled options for reducing pow er consumption. the operation of the int in low-power modes is disc ussed in the following subsections. 17.4.1.1 operation in run mode the int does not contain any options for reducing power in run mode. 17.4.1.2 operation in wait mode clocks to the int can be shut off during system wait mode and the asynchronous interrupt path will be used to generate the wake-up signal upon r ecognition of a valid interrupt or any xirq request. 17.4.1.3 operation in stop mode clocks to the int can be shut off during system st op mode and the asynchronous interrupt path will be used to generate the wake-up signal upon r ecognition of a valid interrupt or any xirq request. 76543210 r psel7 psel6 psel5 psel4 psel3 psel2 psel1 0 w reset11110010 = unimplemented or reserved figure 17-5. highest priority i interrupt register (hprio) table 17-4. hprio field descriptions field description 7:1 psel[7:1] highest priority i interrupt select bits ? the state of these bits determines which i-bit maskable interrupt will be promoted to highest priority (of the i-bit maskable interrup ts). to promote an interrupt, the user writes the least significant byte of the associated interrupt vector address to this register. if an unimplemented vector address or a non i-bit masked vector address (value higher than 0x00f2) is written, irq (0xfff2) will be the default highest priority interrupt. chapter 17 interrupt (intv1) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 507 17.5 resets the int supports three system reset exception reque st types: normal system reset or power-on-reset request, crystal monitor reset request , and cop watchdog reset request. the type of reset exception request must be decoded by the system and the proper request made to the core . the int will then provide the service routine address for th e type of reset requested. 17.6 interrupts as shown in the block diagram in figure 17-1 , the int contains a re gister block to provi de interrupt status and control, an optional highest priority i interrupt (hprio) block, and a priority decoder to evaluate whether pending interrupts are va lid and assess their priority. 17.6.1 interrupt registers the int registers are accessible only in special modes of operation and f unction as described in section 17.3.2.1, ?interrupt test control register ,? and section 17.3.2.2, ?interrupt test registers ,? previously. 17.6.2 highest priority i-bit maskable interrupt when the optional hprio block is implemented, the us er is allowed to promote a single i-bit maskable interrupt to be the highest priority i interrupt. th e hprio evaluates all interr upt exception requests and passes the hprio vector to the priori ty decoder if the highest priority i interrupt is acti ve. rti replaces the promoted interrupt source. 17.6.3 interrupt priority decoder the priority decoder evaluates all interrupts pending and determines thei r validity and pr iority. when the cpu requests an interrupt vector, the decoder will pr ovide the vector for the highest priority interrupt request. because the vector is not supplied until the cpu requests it, it is possible that a higher priority interrupt request could override the or iginal exception that caused the cp u to request the vector. in this case, the cpu will receive the highest priority vector and the system will process this exception instead of the original request. note care must be taken to ensure that all exception requests remain active until the system begins execution of the app licable service routine; otherwise, the exception request ma y not be processed. if for any reason the interrupt s ource is unknown (e.g., an interrupt re quest becomes in active after the interrupt has been recognized but prior to the vector request), the vector address will default to that of the last valid interrupt that existed during the particular interrupt sequence. if th e cpu requests an interrupt vector when there has never been a pending interrupt request, the int wi ll provide the software interrupt (swi) vector address. chapter 17 interrupt (intv1) mc9s12e256 data sheet, rev. 1.08 508 freescale semiconductor 17.7 exception priority the priority (from highest to lowest) and address of all exception vectors issu ed by the int upon request by the cpu is shown in table 17-5 . table 17-5. exception vector map and priority vector address source 0xfffe?0xffff system reset 0xfffc?0xfffd crystal monitor reset 0xfffa?0xfffb cop reset 0xfff8?0xfff9 unimplemented opcode trap 0xfff6?0xfff7 software interrupt inst ruction (swi) or bdm vector request 0xfff4?0xfff5 xirq signal 0xfff2?0xfff3 irq signal 0xfff0?0xff00 device-specific i-bit maskable interrupt sources (priority in descending order) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 509 chapter 18 multiplexed external bus interface (mebiv3) 18.1 introduction this section describes the functionality of the multiplexed external bus interface (meb i) sub-block of the s12 core platform. the functionality of the module is closely coupled with the s12 cpu and the memory map controller (mmc) sub-blocks. figure 18-1 is a block diagram of the mebi. in figure 18-1 , the signals on the right hand side represent pins that are accessible externally. on so me chips, these may not all be bonded out. the mebi sub-block of the core se rves to provide access and/or visibility to internal core data manipulation operations including timing reference information at the exte rnal boundary of the core and/or system. depending upon the system operati ng mode and the state of bits with in the control registers of the mebi, the internal 16-bit read and write data operations w ill be represented in 8-bit or 16-bit accesses externally. using control informati on from other blocks within the sy stem, the mebi will determine the appropriate type of data access to be generated. 18.1.1 features the block name includes these distinctive features: ? external bus controller with f our 8-bit ports a,b, e, and k ? data and data direction registers for ports a, b, e, and k when used as general-purpose i/o ? control register to enable/disable alternate functions on ports e and k ? mode control register ? control register to enable/disable pul l resistors on ports a, b, e, and k ? control register to enable/disable reduced output drive on ports a, b, e, and k ? control register to confi gure external clock behavior ? control register to configure irq pin operation ? logic to capture and synchronize external interrupt pin inputs chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 510 freescale semiconductor figure 18-1. mebi block diagram pe[7:2]/noacc/ pe1/irq pe0/xirq bkgd/modc/taghi pk[7:0]/e cs /xcs /x[19:14] pa[7:0]/a[15:8]/ d[15:8]/d[7:0] port k port a pb[7:0]/a[7:0]/ d[7:0] port b port e bkgd regs ext bus i/f ctl addr[19:0] data[15:0] (control) internal bus eclk ctl irq ctl addr addr data addr data pipe ctl cpu pipe info irq interrupt xirq interrupt bdm tag info ipipe1/modb/clkto ipipe0/moda/ eclk/ lstrb /taglo r/w tag ctl control signal(s) data signal ( unidirectional) data bus (unidirectional) data bus (bidirectional) data signal (bidirectional) mode chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 511 18.1.2 modes of operation ? normal expanded wide mode ports a and b are configured as a 16-bit multiplexed address and data bus and port e provides bus control and status signals . this mode allows 16-bit external memory and periphera l devices to be interfaced to the system. ? normal expanded narrow mode ports a and b are configured as a 16-bit address bus a nd port a is multiplexed with 8-bit data. port e provides bus control and status signals. th is mode allows 8-bit external memory and peripheral devices to be in terfaced to the system. ? normal single-chip mode there is no external expansion bus in this mode. the processor progr am is executed from internal memory. ports a, b, k, and most of e are available as general-purpose i/o. ? special single-chip mode this mode is generally used for debugging single-chip opera tion, boot-strapping, or security related operations. the active bac kground mode is in control of cp u execution and bdm firmware is waiting for additional serial commands through the bkgd pin. there is no external expansion bus after reset in this mode. ? emulation expanded wide mode developers use this mode for emulation systems in which the users target application is normal expanded wide mode. ? emulation expanded narrow mode developers use this mode for emulation systems in which the users target application is normal expanded narrow mode. ? special test mode ports a and b are configured as a 16-bit multiplexed address and data bus and port e provides bus control and status signals. in special test mode, th e write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset. ? special peripheral mode this mode is intended for freescale semiconduct or factory testing of the system. the cpu is inactive and an external (tester) bus master drives address, data, and bus control signals. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 512 freescale semiconductor 18.2 external signal description in typical implementations, the mebi sub-block of the core interfaces di rectly with external system pins. some pins may not be bonded out in all implementations. table 18-1 outlines the pin names a nd functions and gives a brief description of th eir operation reset state of these pins and associ ated pull-ups or pull-downs is dependent on the mode of operation and on the integration of this block at the chip level (chip dependent). . table 18-1. external system pins associated with mebi pin name pin functions description bkgd/modc/ tag h i modc at the rising edge on reset , the state of this pin is registered into the modc bit to set the mode. (this pin always has an internal pullup.) bkgd pseudo open-drain communication pin for the single-wire background debug mode. there is an internal pull-up resistor on this pin. tag h i when instruction tagging is on, a 0 at the falling edge of e tags the high half of the instruction word being read into the instruction queue. pa7/a15/d15/d7 thru pa0/a8/d8/d0 pa7?pa0 general-purpose i/o pins, see porta and ddra registers. a15?a8 high-order address lines multiplexed during eclk low. outputs except in special peripheral mode where they are inputs from an external tester system. d15?d8 high-order bidirectional data lines multiplexed during eclk high in expanded wide modes, special peripheral mode, and visible internal accesses (ivis = 1) in emulation expanded narrow mode. direction of data transfer is generally indicated by r/w . d15/d7 thru d8/d0 alternate high-order and low-order bytes of the bidirectional data lines multiplexed during eclk high in expanded narrow modes and narrow accesses in wide modes. direction of data transfer is generally indicated by r/w . pb7/a7/d7 thru pb0/a0/d0 pb7?pb0 general-purpose i/o pins, see portb and ddrb registers. a7?a0 low-order address lines multiplexed during eclk low. outputs except in special peripheral mode where they are inputs from an external tester system. d7?d0 low-order bidirectional data lines multiplexed during eclk high in expanded wide modes, special peripheral mode, and visible internal accesses (with ivis = 1) in emulation expanded narrow mode. direction of data transfer is generally indicated by r/w . pe7/noacc pe7 general-purpose i/o pin, see porte and ddre registers. noacc cpu no access output. i ndicates whether the current cycle is a free cycle. only available in expanded modes. pe6/ipipe1/ modb/clkto modb at the rising edge of reset , the state of this pin is registered into the modb bit to set the mode. pe6 general-purpose i/o pin, see porte and ddre registers. ipipe1 instruction pipe status bit 1, enabled by pipoe bit in pear. clkto system clock test output. only available in special modes. pipoe = 1 overrides this function. the enable for this function is in the clock module. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 513 detailed descriptions of these pins can be found in chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? . pe5/ipipe0/moda moda at the rising edge on reset , the state of this pin is registered into the moda bit to set the mode. pe5 general-purpose i/o pin, see porte and ddre registers. ipipe0 instruction pipe status bit 0, enabled by pipoe bit in pear. pe4/eclk pe4 general-purpose i/o pin, see porte and ddre registers. eclk bus timing reference clock, can operate as a free-running clock at the system clock rate or to produce one low-high clock per visible access, with the high period stretched for slow accesses. eclk is controlled by the neclk bit in pear, the ivis bit in mode, and the estr bit in ebictl. pe3/lstrb / taglo pe3 general-purpose i/o pin, see porte and ddre registers. lstrb low strobe bar, 0 indicates valid data on d7?d0. sz8 in special peripheral mode, this pin is an input indicating the size of the data transfer (0 = 16-bit; 1 = 8-bit). tag l o in expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of e tags the low half of the instruction word being read into the instruction queue. pe2/r/w pe2 general-purpose i/o pin, see porte and ddre registers. r/w read/write, indicates the direction of internal data transfers. this is an output except in special peripheral mode where it is an input. pe1/irq pe1 general-purpose input-only pin, can be read even if irq enabled. irq maskable interrupt request, can be level sensitive or edge sensitive. pe0/xirq pe0 general-purpose input-only pin. xirq non-maskable interrupt input. pk7/ecs pk7 general-purpose i/o pin, see portk and ddrk registers. ecs emulation chip select pk6/xcs pk6 general-purpose i/o pin, see portk and ddrk registers. xcs external data chip select pk5/x19 thru pk0/x14 pk5?pk0 general-purpose i/o pins, see portk and ddrk registers. x19?x14 memory expansion addresses table 18-1. external system pins associated with mebi (continued) pin name pin functions description chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 514 freescale semiconductor 18.3 memory map and register definition a summary of the registers associated with the mebi sub-block is shown in table 18-2 . detailed descriptions of the registers and bits are given in the subsections that follow. on most chips the registers are mappable. therefore, the upper bits may not be all 0s as shown in the table and descriptions. 18.3.1 module memory map table 18-2. mebi memory map address offset use access 0x0000 port a data register (porta) r/w 0x0001 port b data register (portb) r/w 0x0002 data direction register a (ddra) r/w 0x0003 data direction register b (ddrb) r/w 0x0004 reserved r 0x0005 reserved r 0x0006 reserved r 0x0007 reserved r 0x0008 port e data register (porte) r/w 0x0009 data direction register e (ddre) r/w 0x000a port e assignment register (pear) r/w 0x000b mode register (mode) r/w 0x000c pull control register (pucr) r/w 0x000d reduced drive register (rdriv) r/w 0x000e external bus interface control register (ebictl) r/w 0x000f reserved r 0x001e irq control register (irqcr) r/w 0x00032 port k data register (portk) r/w 0x00033 data direction register k (ddrk) r/w chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 515 18.3.2 register descriptions addressname bit 765432 1bit 0 0x0000 porta r bit 765432 1bit 0 w 0x0001 portb r bit 765432 1bit 0 w 0x0002 ddra r bit 765432 1bit 0 w 0x0003 ddrb r bit 765432 1bit 0 w 0x0004 reserved r0 00000 0 0 w 0x0005 reserved r0 00000 0 0 w 0x0006 reserved r0 00000 0 0 w 0x0007 reserved r0 00000 0 0 w 0x0008 porte r bit 765432 bit 1 bit 0 w 0x0009 ddre r bit 76543bit 2 00 w 0x000a pear r noacce 0 pipoe neclk lstre rdwe 00 w 0x000b mode r modc modb moda 0 ivis 0 emk eme w 0x000c pucr r pupke 00 pupee 00 pupbe pupae w 0x000d rdriv r rdrk 00 rdpe 00 rdpb rdpa w 0x000e ebictl r0 00000 0 estr w 0x000f reserved r0 00000 0 0 w 0x001e irqcr r irqe irqen 0000 0 0 w 0x0032 portk r bit 765432 1bit 0 w 0x0033 ddrk r bit 765432 1bit 0 w = unimplemented or reserved figure 18-2. mebi register summary chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 516 freescale semiconductor 18.3.2.1 port a data register (porta) read: anytime when register is in the map write: anytime when register is in the map port a bits 7 through 0 are associated with addres s lines a15 through a8 respectively and data lines d15/d7 through d8/d0 respectively. when this port is not used for external addresses such as in single-chip mode, these pins can be used as genera l-purpose i/o. data dire ction register a (ddra) determines the primary direction of each pin. ddra also determines the source of data for a read of porta. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. note to ensure that you read the value pr esent on the porta pins, always wait at least one cycle after wr iting to the ddra register before reading from the porta register. 76543210 r bit 7654321bit 0 w reset00000000 s i n g l e c h i p pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 expanded wide, emulation narrow with ivis, and peripheral ab/db15 ab/db14 ab/db13 ab/db12 ab/db11 ab/db10 ab/db9 ab/db8 expanded narrow ab15 and db15/db7 ab14 and db14/db6 ab13 and db13/db5 ab12 and db12/db4 ab11 and db11/db3 ab10 and db10/db2 ab9 and db9/db1 ab8 and db8/db0 figure 18-3. port a data register (porta) chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 517 18.3.2.2 port b data register (portb) read: anytime when register is in the map write: anytime when register is in the map port b bits 7 through 0 are associated with address lines a7 through a0 respectively and data lines d7 through d0 respectively. when this port is not used for external addresses, such as in single-chip mode, these pins can be used as general- purpose i/o. data direction register b (ddrb) determines the primary direction of each pin. ddrb also determines the source of data for a read of portb. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. note to ensure that you read the value pr esent on the portb pins, always wait at least one cycle after wr iting to the ddrb register before reading from the portb register. 76543210 r bit 7654321bit 0 w reset00000000 single chip pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 expanded wide, emulation narrow with ivis, and peripheral ab/db7 ab/db6 ab/db5 ab/db4 ab/db3 ab/db2 ab/db1 ab/db0 expanded narrow ab7 ab6 ab5 ab4 ab3 ab2 ab1 ab0 figure 18-4. port a data register (portb) chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 518 freescale semiconductor 18.3.2.3 data direction register a (ddra) read: anytime when register is in the map write: anytime when register is in the map this register controls the data di rection for port a. when port a is ope rating as a general-purpose i/o port, ddra determines the primary direction for each port a pin. a 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impeda nce input. the value in a ddr bit also affects the source of data for re ads of the corresponding porta register. if the ddr bit is 0 (input) the buffered pin input state is read. if the ddr bit is 1 (output) the associated por t data register bit state is read. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. it is reset to 0x00 so the ddr does not override the th ree-state control signals. 76543210 r bit 7654321bit 0 w reset00000000 figure 18-5. data direct ion register a (ddra) table 18-3. ddra fi eld descriptions field description 7:0 ddra data direction port a 0 configure the corresponding i/o pin as an input 1 configure the corresponding i/o pin as an output chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 519 18.3.2.4 data direction register b (ddrb) read: anytime when register is in the map write: anytime when register is in the map this register controls the data di rection for port b. when port b is ope rating as a general-purpose i/o port, ddrb determines the primary direction for each port b pin. a 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impeda nce input. the value in a ddr bit also affects the source of data for reads of the corresponding portb register. if th e ddr bit is 0 (input) the buffered pin input state is read. if the ddr bit is 1 (output) the associated por t data register bit state is read. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. it is reset to 0x00 so the ddr does not override the th ree-state control signals. 76543210 r bit 7654321bit 0 w reset00000000 figure 18-6. data direct ion register b (ddrb) table 18-4. ddrb fi eld descriptions field description 7:0 ddrb data direction port b 0 configure the corresponding i/o pin as an input 1 configure the corresponding i/o pin as an output chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 520 freescale semiconductor 18.3.2.5 reserved registers these register locations are not used (reserved). all unused registers and bits in this block return logic 0s when read. writes to these registers have no effect. these registers are not in the on-c hip map in special peripheral mode. 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 18-7. reserved register 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 18-8. reserved register 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 18-9. reserved register 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 18-10. reserved register chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 521 18.3.2.6 port e data register (porte) read: anytime when register is in the map write: anytime when register is in the map port e is associated with external bus control signa ls and interrupt inputs. th ese include mode select (modb/ipipe1, moda/ipipe 0), e clock, size (lstrb /taglo ), read/write (r/w ), irq , and x irq . when not used for one of these spec ific functions, port e pi ns 7:2 can be used as general-purpose i/o and pins 1:0 can be used as general- purpose input. the port e a ssignment register (pear) selects the function of each pin and ddre determines whether each pin is an input or output when it is configured to be general-purpose i/o. ddre also determines the source of data for a read of porte. some of these pins have software selectable pull resistors. irq and xirq can only be pulled up whereas the polarity of the pe7, pe4, pe3, and pe2 pull resistor s are determined by chip integration. please refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? ( section 1.3.2, ?signal properties summary? ) to determine the polarity of th ese resistors. a single control bi t enables the pull devices for all of these pins when they are configured as inputs. this register is not in the on-chip map in special peripheral mode or in expanded modes when the eme bit is set. therefore, these ac cesses will be echoed externally. note it is unwise to write porte and dd re as a word access. if you are changing port e pins from be ing inputs to outputs, th e data may have extra transitions during the write. it is best to initialize porte before enabling as outputs. note to ensure that you read the value present on the porte pins, always wait at least one cycle after writing to the ddre register before reading from the porte register. 76543210 r bit 765432 bit 1 bit 0 w reset000000uu alternate pin function noacc modb or ipipe1 or clkto moda or ipipe0 eclk lstrb or taglo r/w irq xirq = unimplemented or reserved u = unaffected by reset figure 18-11. port e data register (porte) chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 522 freescale semiconductor 18.3.2.7 data direction register e (ddre) read: anytime when register is in the map write: anytime when register is in the map data direction register e is associat ed with port e. for bits in port e th at are configured as general-purpose i/o lines, ddre determines the prim ary direction of each of these pins . a 1 causes the associated bit to be an output and a 0 causes the associated bit to be an input. port e bit 1 (associated with irq ) and bit 0 (associated with xirq ) cannot be configured as outputs. port e, bits 1 and 0, can be read regardless of whether the alternate interrupt functi on is enabled. the value in a ddr bit also affects the source of data for reads of the corresponding porte register. if the ddr bit is 0 (input) the buffered pin input state is read. if the ddr bit is 1 (output) the associ ated port data register bit state is read. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. also, it is not in the map in expanded modes while the eme control bit is set. 76543210 r bit 76 5 4 3bit 2 00 w reset00000000 = unimplemented or reserved figure 18-12. data direction register e (ddre) table 18-5. ddre field descriptions field description 7:2 ddre data direction port e 0 configure the corresponding i/o pin as an input 1 configure the corresponding i/o pin as an output note: it is unwise to write porte and ddre as a word acce ss. if you are changing port e pins from inputs to outputs, the data may have extra transitions during the wr ite. it is best to initialize porte before enabling as outputs. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 523 18.3.2.8 port e assignment register (pear) read: anytime (provided this register is in the map). write: each bit has specifi c write conditions. please refe r to the descriptions of each bit on the following pages. port e serves as general-purpose i/o or as system and bus control signals . the pear register is used to choose between the general-purpose i/o function and th e alternate control functions. when an alternate control function is selected, the a ssociated ddre bits are overridden. the reset condition of this register depends on the mode of operation because bus control signals are needed immediately after reset in so me modes. in normal si ngle-chip mode, no extern al bus control signals are needed so all of port e is c onfigured for general-purpose i/o. in normal expanded modes, only the e clock is configured for its alternat e bus control function and the other bits of port e are configured for general-purpose i/o. as the reset vect or is located in external memory , the e clock is required for this access. r/w is only needed by the system when there ar e external writable resources. if the normal expanded system needs any other bus control signals, pear would n eed to be written before any access that needed the additional signals. in special test and emulation modes, ipipe1, ipipe0, e, lstrb , and r/w are configured out of reset as bus control signals. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. 76543210 r noacce 0 pipoe neclk lstre rdwe 00 w reset special single chip00000000 special test00101100 peripheral0 0000000 emulation expanded narrow 1 0101100 emulation expanded wide 10101100 normal single chip00010000 normal expanded narrow 00000000 normal expanded wide00000000 = unimplemented or reserved figure 18-13. port e assignment register (pear) chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 524 freescale semiconductor table 18-6. pear field descriptions field description 7 noacce cpu no access output enable normal: write once emulation: write never special: write anytime 1 the associated pin (port e, bit 7) is general-purpose i/o. 0 the associated pin (port e, bit 7) is output and indicates whet her the cycle is a cpu free cycle. this bit has no effect in single-chip or special peripheral modes. 5 pipoe pipe status signal output enable normal: write once emulation: write never special: write anytime. 0 the associated pins (port e, bits 6:5) are general-purpose i/o. 1 the associated pins (port e, bits 6:5) are outp uts and indicate the stat e of the instruction queue this bit has no effect in single-chip or special peripheral modes. 4 neclk no external e clock normal and special: write anytime emulation: write never 0 the associated pin (port e, bit 4) is the external e clock pin. external e clock is free-running if estr = 0 1 the associated pin (port e, bit 4) is a general-purpose i/o pin. external e clock is available as an output in all modes. 3 lstre low strobe (lstrb ) enable normal: write once emulation: write never special: write anytime. 0 the associated pin (port e, bit 3) is a general-purpose i/o pin. 1 the associated pin (port e, bit 3) is configured as the lstrb bus control output. if bdm tagging is enabled, tag l o is multiplexed in on the rising edge of eclk and lstrb is driven out on the falling edge of eclk. this bit has no effect in single-chip, peripheral, or normal expanded narrow modes. note: lstrb is used during external writes. after reset in normal expanded mode, lstrb is disabled to provide an extra i/o pin. if lstrb is needed, it should be enabled before any external writes. external reads do not normally need lstrb because all 16 data bits can be driven even if the system only needs 8 bits of data. 2 rdwe read/write enable normal: write once emulation: write never special: write anytime 0 the associated pin (port e, bit 2) is a general-purpose i/o pin. 1 the associated pin (port e, bit 2) is configured as the r/w pin this bit has no effect in single-chip or special peripheral modes. note: r/w is used for external writes. after reset in normal expanded mode, r/w is disabled to provide an extra i/o pin. if r/w is needed it should be enabled before any external writes. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 525 18.3.2.9 mode register (mode) read: anytime (provided this register is in the map). write: each bit has specific write conditions. please refer to the descriptions of each bit on the following pages. the mode register is used to establish the opera ting mode and other miscel laneous functions (i.e., internal visibility and em ulation of port e and k). in special peripheral mode, this register is not accessi ble but it is reset as show n to system configuration features. changes to bits in the mode regi ster are delayed one cycle after the write. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. 76543210 r modc modb moda 0 ivis 0 emk eme w reset special single chip00000000 emulation expanded narrow 00101011 special test01001000 emulation expanded wide 01101011 normal single chip10000000 normal expanded narrow 10100000 peripheral11000000 normal expanded wide11100000 = unimplemented or reserved figure 18-14. mode register (mode) table 18-7. mode field descriptions field description 7:5 mod[c:a] mode select bits ? these bits indicate the current operating mode. if moda = 1, then modc, modb, and moda are write never. if modc = moda = 0, then modc, mo db, and moda are writable with t he exception that you cannot change to or from special peripheral mode if modc = 1, modb = 0, and moda = 0, then modc is write never. modb and moda are write once, except that you cannot change to special peripheral mode. from normal single-chip, only normal expanded narrow and normal expanded wide modes are available. see ta bl e 1 8 - 8 and table 18-16 . chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 526 freescale semiconductor 3 ivis internal visibility (for both read and write accesses) ? this bit determines whether internal accesses generate a bus cycle that is vi sible on the external bus. normal: write once emulation: write never special: write anytime 0 no visibility of internal bus operations on external bus. 1 internal bus operations are visible on external bus. 1 emk emulate port k normal: write once emulation: write never special: write anytime 0 portk and ddrk are in the memory map so port k can be used for general-purpose i/o. 1 if in any expanded mode, portk and ddrk are removed from the memory map. in single-chip modes, portk and ddrk are always in the map regardless of the state of this bit. in special peripheral mode, portk and ddrk are never in the map regardless of the state of this bit. 0 eme emulate port e normal and emulation: write never special: write anytime 0 porte and ddre are in the memory map so port e can be used for general-purpose i/o. 1 if in any expanded mode or special peripheral mode, porte and ddre are removed from the memory map. removing the registers from the map allows the user to emulate the function of these registers externally. in single-chip modes, porte and ddre are always in the map regardless of the state of this bit. table 18-8. modc, modb, and moda write capability a a no writes to the mod bits are allowed while operating in a secure mode. for more details, refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? . modc modb moda mode modx write capability 0 0 0 special single chip modc, modb, and moda write anytime but not to 110 b b if you are in a special single-chip or special test mode and yo u write to this register, changing to normal single-chip mode, t hen one allowed write to this register remains. if you write to normal expanded or emulation mode, then no writes remain. 0 0 1 emulation narrow no write 0 1 0 special test modc, modb, and moda write anytime but not to 110 2 0 1 1 emulation wide no write 1 0 0 normal single chip modc write never, modb and moda write once but not to 110 1 0 1 normal expanded narrow no write 1 1 0 special peripheral no write 1 1 1 normal expanded wide no write table 18-7. mode field descriptions (continued) field description chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 527 18.3.2.10 pull control register (pucr) read: anytime (provided this register is in the map). write: anytime (provided this register is in the map). this register is used to select pull resistors for the pins associated with the core ports. pull resistors are assigned on a per-port basi s and apply to any pin in the correspondi ng port that is currently configured as an input. the polarity of these pull resistors is determined by chip inte gration. please refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? to determine the polarity of these resistors. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. note these bits have no effect when the as sociated pin(s) are outputs. (the pull resistors are inactive.) 76543210 r pupke 00 pupee 00 pupbe pupae w reset 1 10010000 1. the default value of this param eter is shown. please refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? to determine the actual reset state of this register. = unimplemented or reserved figure 18-15. pull control register (pucr) table 18-9. pucr field descriptions field description 7 pupke pull resistors port k enable 0 port k pull resistors are disabled. 1 enable pull resistors for port k input pins. 4 pupee pull resistors port e enable 0 port e pull resistors on bits 7, 4:0 are disabled. 1 enable pull resistors for port e input pins bits 7, 4:0. note: pins 5 and 6 of port e have pull resistors which are only enabled during reset. this bit has no effect on these pins. 1 pupbe pull resistors port b enable 0 port b pull resistors are disabled. 1 enable pull resistors for all port b input pins. 0 pupae pull resistors port a enable 0 port a pull resistors are disabled. 1 enable pull resistors for all port a input pins. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 528 freescale semiconductor 18.3.2.11 reduced dri ve register (rdriv) read: anytime (provided this register is in the map) write: anytime (provided this register is in the map) this register is used to select reduced drive for the pins associated with the core ports. this gives reduced power consumption and reduced rfi with a slight incr ease in transition time (d epending on loading). this feature would be used on ports whic h have a light loading. the reduced drive function is independent of which function is being used on a particular port. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. 76543210 r rdrk 00 rdpe 00 rdpb rdpa w reset00000000 = unimplemented or reserved figure 18-16. reduced drive register (rdriv) table 18-10. rdriv field descriptions field description 7 rdrk reduced drive of port k 0 all port k output pins have full drive enabled. 1 all port k output pins have reduced drive enabled. 4 rdpe reduced drive of port e 0 all port e output pins have full drive enabled. 1 all port e output pins have reduced drive enabled. 1 rdpb reduced drive of port b 0 all port b output pins have full drive enabled. 1 all port b output pins have reduced drive enabled. 0 rdpa reduced drive of ports a 0 all port a output pins have full drive enabled. 1 all port a output pins have reduced drive enabled. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 529 18.3.2.12 external bus interfac e control register (ebictl) read: anytime (provided this register is in the map) write: refer to individual bit descriptions below the ebictl register is used to control miscellaneous functions (i.e., stretching of external e clock). this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. 76543210 r0000000 estr w reset: peripheral all other modes 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 = unimplemented or reserved figure 18-17. external bus interface control register (ebictl) table 18-11. ebictl field descriptions field description 0 estr e clock stretches ? this control bit determines whether the e clock behaves as a simple free-running clock or as a bus control signal that is ac tive only for external bus cycles. normal and emulation: write once special: write anytime 0 e never stretches (always free running). 1 e stretches high during stretched external accesses and remains low during non-visible internal accesses. this bit has no effect in single-chip modes. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 530 freescale semiconductor 18.3.2.13 reserved register this register location is not used (res erved). all bits in this register re turn logic 0s when read. writes to this register have no effect. this register is not in the on-chip memory map in expanded and special periphera l modes. therefore, these accesses will be echoed externally. 18.3.2.14 irq control register (irqcr) read: see individual b it descriptions below write: see individual bi t descriptions below 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 18-18. reserved register 76543210 r irqe irqen 000000 w reset01000000 = unimplemented or reserved figure 18-19. irq control register (irqcr) table 18-12. irqcr field descriptions field description 7 irqe irq select edge sensitive only special modes: read or write anytime normal and emulation modes: read anytime, write once 0 irq configured for low level recognition. 1 irq configured to respond only to falling edges. fa lling edges on the irq pin will be detected anytime irqe = 1 and will be cleared only upon a reset or the servicing of the irq interrupt. 6 irqen external irq enable normal, emulation, and special modes: read or write anytime 0 external irq pin is disconnected from interrupt logic. 1 external irq pin is connected to interrupt logic. note: when irqen = 0, the edge detect latch is disabled. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 531 18.3.2.15 port k data register (portk) read: anytime write: anytime this port is associated with the internal memory e xpansion emulation pins. when the port is not enabled to emulate the internal memory expa nsion, the port pins are used as general-purpose i/o. when port k is operating as a general-purpos e i/o port, ddrk determines the primar y direction for each port k pin. a 1 causes the associated port pin to be an output and a 0 causes the asso ciated pin to be a high-impedance input. the value in a ddr bit also affects the s ource of data for reads of the corresponding portk register. if the ddr bit is 0 (input) the buffered pin input is read. if the ddr bit is 1 (output) the output of the port data register is read. this register is not in the map in peripheral or expanded modes while the emk control bit in mode register is set. therefore, thes e accesses will be echoed externally. when inputs, these pins can be selected to be high impedance or pulled up, based upon the state of the pupke bit in the pucr register. 76543210 r bit 7654321bit 0 w reset00000000 alternate pin function ecs xcs xab19 xab18 xab17 xab16 xab15 xab14 figure 18-20. port k data register (portk) table 18-13. portk field descriptions field description 7 port k, bit 7 port k, bit 7 ? this bit is used as an emulation chip select signal for the emulation of the internal memory expansion, or as general-purpose i/o, depending upon the state of the emk bit in the mode register. while this bit is used as a chip select, the exte rnal bit will return to its de-asserted state (v dd ) for approximately 1/4 cycle just after the negative edge of eclk, unless the exte rnal access is stretched and eclk is free-running (estr bit in ebictl = 0). see chapter 19, ?module mapping control (mmcv4)? for additional details on when this signal will be active. 6 port k, bit 6 port k, bit 6 ? this bit is used as an external chip select signal for most external accesses that are not selected by ecs (see chapter 19, ?module mapping control (mmcv4)? for more details), depending upon the state the of the emk bit in the mode r egister. while this bit is used as a chip select, the external pin will return to its de-asserted state (v dd ) for approximately 1/4 cycle just after the negative edge of eclk, unless the external access is stretched and eclk is free-running (estr bit in ebictl = 0). 5:0 port k, bits 5:0 port k, bits 5:0 ? these six bits are used to determine which flash/rom or external memory array page is being accessed. they can be viewed as expanded addresses xab19?xab14 of the 20-bit address used to access up to1m byte internal flash/rom or external memory array. alternatively, these bits can be used for general-purpose i/o depending upon the state of the emk bit in the mode register. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 532 freescale semiconductor 18.3.2.16 port k data di rection register (ddrk) read: anytime write: anytime this register determines the primary direction for each port k pin configured as ge neral-purpose i/o. this register is not in the map in peripheral or expanded modes while the emk control bit in mode register is set. therefore, these accesse s will be echoed externally. 76543210 r bit 7654321bit 0 w reset00000000 figure 18-21. port k data direction register (ddrk) table 18-14. ddrk field descriptions field description 7:0 ddrk data direction port k bits 0 associated pin is a high-impedance input 1 associated pin is an output note: it is unwise to write portk and ddrk as a word acce ss. if you are changing port k pins from inputs to outputs, the data may have extra transitions during the wr ite. it is best to initialize portk before enabling as outputs. note: to ensure that you read the correct value from the po rtk pins, always wait at least one cycle after writing to the ddrk register before reading from the portk register. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 533 18.4 functional description 18.4.1 detecting access type from external signals the external signals lstrb , r/w , and ab0 indicate the type of bus access that is ta king place. accesses to the internal ram module are the only type of access that would produce lstrb = ab0 = 1, because the internal ram is specifically designed to allow mi saligned 16-bit accesses in a single cycle. in these cases the data for the address that was accessed is on the low half of the data bus and the data for address + 1 is on the high half of the data bus. this is summarized in table 18-15 . 18.4.2 stretched bus cycles in order to allow fast intern al bus cycles to coexist in a system with slower external memory resources, the hcs12 supports the concept of stretched bus cycles (module timing reference cl ocks for timers and baud rate generators are not affected by th is stretching). control bits in the misc register in the mmc sub-block of the core specify the amount of stretch (0, 1, 2, or 3 periods of the internal bus-rate clock). while stretching, the cpu state machines are all held in their current state. at this point in the cpu bus cycle, write data would already be driven onto the data bus so the length of tim e write data is valid is extended in the case of a stretched bus cycle. read data would not be captured by the system until the e clock falling edge. in the case of a stre tched bus cycle, read data is not require d until the specified se tup time before the falling edge of the st retched e clock. the ch ip selects, and r/w signals remain valid during the period of stretching (throughout the st retched e high time). note the address portion of the bus cycle is not stretched . table 18-15. access type vs. bus control pins lstrb ab0 r/w type of access 1 0 1 8-bit read of an even address 0 1 1 8-bit read of an odd address 1 0 0 8-bit write of an even address 0 1 0 8-bit write of an odd address 0 0 1 16-bit read of an even address 1 1 1 16-bit read of an odd address (low/high data swapped) 0 0 0 16-bit write to an even address 1 1 0 16-bit write to an odd address (low/high data swapped) chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 534 freescale semiconductor 18.4.3 modes of operation the operating mode out of reset is determined by th e states of the modc, mo db, and moda pins during reset ( table 18-16 ). the modc, modb, and moda bits in the mode register show the current operating mode and provide limite d mode switching during operation. the states of the modc, modb, and moda pins are latched into these bits on the rising edge of the reset signal. there are two basic types of operating modes: 1. normal modes: some registers and bits are protected against accidental changes. 2. special modes: allow greater access to protected control registers and bits for special purposes such as testing. a system development and debug feat ure, background debug mode (bdm), is available in all modes. in special single-chip mode, bdm is active immediately after reset. some aspects of port e are not mode dependent. bit 1 of port e is a genera l purpose input or the irq interrupt input. irq can be enabled by bits in the cpu?s condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. bit 0 of port e is a general purpose input or the xirq interrupt input. xirq can be enabled by bits in the cpu? s condition codes register but it is inhibited at reset so this pin is in itially configured as a simple input with a pull-up. the estr bit in the ebictl register is set to on e by reset in any user mode. this assure s that the reset vect or can be fetched even if it is located in an ex ternal slow memory device. the pe 6/modb/ipipe1 and pe5/moda/ipipe0 pins act as high-impedance m ode select inputs during reset. the following paragraphs discuss th e default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis. table 18-16. mode selection modc modb moda mode description 0 0 0 special single chip, bdm allowed and active. bdm is allowed in all other modes but a serial command is required to make bdm active. 0 0 1 emulation expanded narrow, bdm allowed 0 1 0 special test (expanded wide), bdm allowed 0 1 1 emulation expanded wide, bdm allowed 1 0 0 normal single chip, bdm allowed 1 0 1 normal expanded narrow, bdm allowed 1 1 0 peripheral; bdm allowed but bus operations would cause bus conflicts (must not be used) 1 1 1 normal expanded wide, bdm allowed chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 535 18.4.3.1 normal operating modes these modes provide three operating configurations. background debug is available in all three modes, but must first be enabled for so me operations by means of a bdm background command, then activated. 18.4.3.1.1 normal single-chip mode there is no external expansion bus in this mode. all pins of ports a, b and e are configured as general purpose i/o pins port e bits 1 and 0 are available as general purpose i nput only pins with internal pull resistors enabled. all other pins of port e are bidire ctional i/o pins that are initially configured as high-impedance inputs with internal pull resist ors enabled. ports a and b are configured as high-impedance inputs with their in ternal pull resistors disabled. the pins associated with po rt e bits 6, 5, 3, and 2 cannot be configured for their alternate functions ipipe1, ipipe0, lstrb , and r/w while the mcu is in single chip modes. in single chip modes, the associated control bits pipoe, lstre, and rdwe are reset to zero. writing the opposite stat e into them in single chip mode does not change the operati on of the associated port e pins. in normal single chip mode, the mode register is writable one time. this allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. port e, bit 4 can be configured for a free-running e clock output by clearing neclk=0. typically the only use for an e clock output while the mcu is in single chip modes would be to get a constant speed clock for use in the external application system. 18.4.3.1.2 normal expanded wide mode in expanded wide modes, ports a a nd b are configured as a 16-bit mult iplexed address a nd data bus and port e bit 4 is configured as the e clock output signal. these signals al low external memo ry and peripheral devices to be interfaced to the mcu. port e pins other than pe4/eclk are configured as general purpose i/ o pins (initially high-impedance inputs with internal pull resistors enabled). contro l bits pipoe, neclk, lstre, and rdwe in the pear register can be used to configure port e pins to act as bus control outputs instead of general purpose i/o pins. it is possible to enab le the pipe status signals on port e bits 6 and 5 by setti ng the pipoe bit in pear, but it would be unusual to do so in this mode. develo pment systems where pipe status signals are monitored would typically use the special variation of this mode. the port e bit 2 pin can be reconfigured as the r/w bus control signal by writing ?1? to the rdwe bit in pear. if the expanded system include s external devices that can be written, such as ram, the rdwe bit would need to be set before any attempt to write to an external location. if there are no writable resources in the external system, pe2 can be left as a general purpose i/o pin. the port e bit 3 pin can be reconfigured as the lstrb bus control signal by writi ng ?1? to the lstre bit in pear. the default condition of this pin is a general purpose i nput because the lstrb function is not needed in all expande d wide applications. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 536 freescale semiconductor the port e bit 4 pin is initially configured as eclk output with stretch. the e clock output function depends upon the settings of the necl k bit in the pear register, the iv is bit in the mode register and the estr bit in the ebictl register. the e clock is avai lable for use in external select decode logic or as a constant speed clock for use in the external application system. 18.4.3.1.3 normal expanded narrow mode this mode is used for lower cost production systems that use 8-bit wide external eproms or rams. such systems take extra bus cycles to access 16-bit locati ons but this may be prefer red over the extra cost of additional external memory devices. ports a and b are configured as a 16-bi t address bus and port a is multiplexed with data. internal visibility is not available in this mode becau se the internal cycles would need to be split into two 8-bit cycles. since the pear register can only be written one time in this mode, use care to set all bits to the desired states during the si ngle allowed write. the pe3/lstrb pin is always a general purpose i/o pin in normal expanded narrow mode. although it is possible to write the lstre bit in pear to ?1? in this mode, the st ate of lstre is ove rridden and port e bit 3 cannot be reconf igured as the lstrb output. it is possible to enab le the pipe status signals on port e bits 6 and 5 by setti ng the pipoe bit in pear, but it would be unusual to do so in this mode. lstrb would also be needed to fully understand system activity. development systems wher e pipe status signals are monito red would typically use special expanded wide mode or occasionally special expanded narrow mode. the pe4/eclk pin is initially configured as eclk output with stretch. the e clock output function depends upon the settings of the necl k bit in the pear register, the iv is bit in the mode register and the estr bit in the ebictl register . in normal expanded narrow mode, th e e clock is available for use in external select decode logic or as a constant speed clock for use in the exte rnal application system. the pe2/r/w pin is initially configured as a general purpose input with an intern al pull resistor enabled but this pin can be r econfigured as the r/w bus control signal by writing ?1? to the rdwe bit in pear. if the expanded narrow system include s external devices that can be wr itten such as ram, the rdwe bit would need to be set before any attempt to write to an external location. if there are no writable resources in the external system, pe2 can be left as a general purpose i/o pin. 18.4.3.1.4 emulation expanded wide mode in expanded wide modes, ports a a nd b are configured as a 16-bit mult iplexed address a nd data bus and port e provides bus control and status signals. these signals allow external memo ry and peripheral devices to be interfaced to the mcu. these signals can also be used by a logic analyzer to monitor the progress of application programs. the bus control related pins in port e (p e7/noacc, pe6/modb/ipipe1, pe5/moda/ipipe0, pe4/eclk, pe3/lstrb /taglo , and pe2/r/w ) are all configured to serve their bus control output functions rather than general purpose i/o. notice that writes to the bus control enable bits in the pear register in emulation mode are restricted. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 537 18.4.3.1.5 emulation expanded narrow mode expanded narrow modes are intended to allow connec tion of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit exte rnal data bus. accesses to internal resources that have been mapped external (i.e., porta, portb, ddra, ddrb, porte, ddre, pear, pucr, rdriv) will be ac cessed with a 16-bit data bus on ports a and b. accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using port a as an 8-bit data bus. in ternal operations continue to use fu ll 16-bit data paths. they are only visible externally as 16-bit information if ivis=1. ports a and b are configured as multiplexed addres s and data output ports. during external accesses, address a15, data d15 and d7 are a ssociated with pa7, address a0 is associated with pb0 and data d8 and d0 are associated with pa0. during internal visi ble accesses and accesses to internal resources that have been mapped external, address a15 and data d15 is associated with pa7 and address a0 and data d0 is associated with pb0. the bus control related pins in port e (p e7/noacc, pe6/modb/ipipe1, pe5/moda/ipipe0, pe4/eclk, pe3/lstrb /taglo , and pe2/r/w ) are all configured to serve their bus control output functions rather than general purpose i/o. notice that writes to the bus control enable bits in the pear register in emulation mode are restricted. the main difference between special modes and normal modes is that some of the bus control and system control signals cannot be wr itten in emulation modes. 18.4.3.2 special operating modes there are two special operating mode s that correspond to normal operati ng modes. these operating modes are commonly used in factory testing and system development. 18.4.3.2.1 special sing le-chip mode when the mcu is reset in this mode, the backgr ound debug mode is enabled a nd active. the mcu does not fetch the reset vector and execute application code as it would in other m odes. instead the active background mode is in control of cpu execution a nd bdm firmware is waiti ng for additional serial commands through the bkgd pin. when a serial comm and instructs the mcu to return to normal execution, the system wi ll be configured as described below unle ss the reset states of internal control registers have been changed through backgr ound commands after the mcu was reset. there is no external expansion bus af ter reset in this mode. ports a and b are initially simp le bidirectional i/o pins that are configured as high-impedance inputs with internal pull resistors disabled; however, writing to the mode select bits in the mode register (which is allowed in special modes) can change this after reset. all of the port e pins (except pe4/eclk) are initia lly configured as general purpose high-impedance inputs with internal pull resistors enabled. pe4/eclk is configured as the e clock output in this mode. the pins associated with po rt e bits 6, 5, 3, and 2 cannot be configured for their alternate functions ipipe1, ipipe0, lstrb , and r/w while the mcu is in single chip modes. in single chip modes, the associated chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 538 freescale semiconductor control bits pipoe, lstre and rdwe are reset to zero. writing the opposite value into these bits in single chip mode does not change the ope ration of the associated port e pins. port e, bit 4 can be configured for a free-running e clock output by clearing neclk=0. t ypically the only use for an e clock output while the mcu is in single chip modes would be to get a constant speed clock for use in the external application system. 18.4.3.2.2 special test mode in expanded wide modes, ports a a nd b are configured as a 16-bit mult iplexed address a nd data bus and port e provides bus control and status signals. in sp ecial test mode, the write protection of many control bits is lifted so that they can be thoroughl y tested without needi ng to go through reset. 18.4.3.3 test operating mode there is a test operating mode in whic h an external master, such as an i.c. tester, can control the on-chip peripherals. 18.4.3.3.1 peripheral mode this mode is intended for factory testing of the mcu. in this mode, the cpu is inactive and an external (tester) bus master drives address, data and bus contro l signals in through ports a, b and e. in effect, the whole mcu acts as if it wa s a peripheral under control of an external cpu. this allows faster testing of on-chip memory and peripherals than previous testing methods. since th e mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the mcu into a different mode. background debugging s hould not be used while th e mcu is in spec ial peripheral mode as internal bus conflicts between bdm and the external master can cause impr oper operation of both functions. 18.4.4 internal visibility internal visibility is available when the mcu is operating in expanded wide m odes or emulation narrow mode. it is not available in single- chip, peripheral or normal expanded na rrow modes. internal visibility is enabled by setting the ivis bit in the mode register. if an internal access is made while e, r/w , and lstrb are configured as bus c ontrol outputs and internal visibility is off (ivis =0), e will remain lo w for the cycle, r/w will remain high, and address, data and the lstrb pins will remain at their previous state. when internal visibility is enabled (ivis=1), certain internal cycles will be blocked from going external. during cycles when the bdm is selected, r/w will remain high, da ta will maintain its previous state, and address and lstrb pins will be updated with the internal value. during cpu no access cycles when the bdm is not driving, r/w will remain high, and a ddress, data and the lstrb pins will remain at their previous state. note when the system is operating in a secu re mode, internal visibility is not available (i.e., ivis = 1 has no effect). also, the ipipe signals will not be visible, regardless of operating mode. ipipe1?ipipe 0 will display 0es if chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 539 they are enabled. in addition, the mod bits in the mode control register cannot be written. 18.4.5 low-power options the mebi does not contain any user-controlled opt ions for reducing power consumption. the operation of the mebi in low-power modes is di scussed in the following subsections. 18.4.5.1 operation in run mode the mebi does not contain any options for reducing pow er in run mode; however, the external addresses are conditioned to reduce power in single-chip m odes. expanded bus modes will increase power consumption. 18.4.5.2 operation in wait mode the mebi does not contain any options for reducing power in wait mode. 18.4.5.3 operation in stop mode the mebi will cease to function after execution of a cpu stop instruction. chapter 18 multiplexed external bus interface (mebiv3) mc9s12e256 data sheet, rev. 1.08 540 freescale semiconductor mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 541 chapter 19 module mapping control (mmcv4) 19.1 introduction this section describes the functiona lity of the module mapping control (mmc) sub-block of the s12 core platform. the block diagram of the mmc is shown in figure 19-1 . figure 19-1. mmc block diagram the mmc is the sub-module which controls memory ma p assignment and selection of internal resources and external space. internal buses be tween the core and memories and be tween the core a nd peripherals is controlled in this module. the memory expansion is generated in this module. mmc mode information registers cpu write data bus cpu address bus cpu control stop, wait address decode cpu read data bus ebi alternate address bus ebi alternate write data bus ebi alternate read data bus security clocks, reset read & write enables alternate address bus (bdm) alternate write data bus (bdm) alternate read data bus (bdm) core select (s) port k interface memory space select(s) peripheral select bus control secure bdm_unsecure mmc_secure internal memory expansion chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 542 freescale semiconductor 19.1.1 features ? registers for mapping of address space for on-chip ram, eeprom, and flash (or rom) memory blocks and associated registers ? memory mapping control and selection based upon address decode a nd system operating mode ? core address bus control ? core data bus control and multiplexing ? core security state decoding ? emulation chip select signal generation (ecs ) ? external chip select signal generation (xcs ) ? internal memory expansion ? external stretch and rom mapping cont rol functions via the misc register ? reserved registers for test purposes ? configurable system memory opti ons defined at integration of co re into the system-on-a-chip (soc). 19.1.2 modes of operation some of the registers operate diff erently depending on the mode of ope ration (i.e., normal expanded wide, special single chip, etc.). this is best understood from the regi ster descriptions. 19.2 external signal description all interfacing with the mmc sub-block is done within the core, it has no external signals. 19.3 memory map and register definition a summary of the registers associated with the mmc sub-block is shown in figure 19-2 . detailed descriptions of the register s and bits are given in the subsections that follow. chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 543 19.3.1 module memory map table 19-1. mmc memory map address offset register access 0x0010 initialization of internal ram position register (initrm) r/w 0x0011 initialization of internal registers position register (initrg) r/w 0x0012 initialization of internal eepr om position register (initee) r/w 0x0013 miscellaneous system control register (misc) r/w reserved ? . . . . ? reserved ? . . . . ? 0x001c memory size register 0 (memsiz0) r 0x001d memory size register 1 (memsiz1) r . . . . 0x0030 program page index register (ppage) r/w reserved ? chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 544 freescale semiconductor 19.3.2 register descriptions name bit 7654321bit 0 initrm r ram15 ram14 ram13 ram12 ram11 00 ramhal w initrg r 0 reg14 reg13 reg12 reg11 000 w initee r ee15 ee14 ee13 ee12 ee11 00 eeon w miscr0000 exstr1 exstr0 romhm romon w mtstorbit 7654321bit 0 w mtst1rbit 7654321bit 0 w memsiz0 r reg_sw0 0 eep_sw1 eep_sw 0 0 ram_sw2 ram_sw1 ram_sw0 w memsiz1 r rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0 w ppage r 0 0 pix5 pix4 pix3 pix2 pix1 pix0 w reservedr00000000 w = unimplemented figure 19-2. mmc register summary chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 545 19.3.2.1 initialization of internal ram position register (initrm) read: anytime write: once in normal and emulati on modes, anytime in special modes note writes to this register take one cycle to go into effect. this register initializes the position of the inte rnal ram within the on-chip system memory map. 19.3.2.2 initialization of internal registers position register (initrg) read: anytime write: once in normal and emulation modes and anytime in special modes this register initializes the positi on of the internal regist ers within the on-chip system memory map. the registers occupy either a 1k byte or 2k byte space and can be mapped to any 2k byte space within the first 32k bytes of the system?s address space. 76543210 r ram15 ram14 ram13 ram12 ram11 00 ramhal w reset00001001 = unimplemented or reserved figure 19-3. initialization of internal ram position register (initrm) table 19-2. initrm field descriptions field description 7:3 ram[15:11] internal ram map position ? these bits determine the upper five bits of the ba se address for the system?s internal ram array. 0 ramhal ram high-align ? ramhal specifies the alignment of the internal ram array. 0 aligns the ram to the lowest address (0x0000) of the mappable space 1 aligns the ram to the higher address (0xffff) of the mappable space 76543210 r0 reg14 reg13 reg12 reg11 000 w reset00000000 = unimplemented or reserved figure 19-4. initialization of internal registers position register (initrg) table 19-3. initrg field descriptions field description 6:3 reg[14:11] internal register map position ? these four bits in combination with the leading zero supplied by bit 7 of initrg determine the upper five bits of the base address for the system?s internal registers (i.e., the minimum base address is 0x0000 and the maximum is 0x7fff). chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 546 freescale semiconductor 19.3.2.3 initialization of internal eeprom position register (initee) read: anytime write: the eeon bit can be written to any time on al l devices. bits e[11:15] ar e ?write anytime in all modes? on most devices. on some devices, bits e[11 :15] are ?write once in normal and emulation modes and write anytime in special modes?. see chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? to determine the actual write access rights. note writes to this register take one cycle to go into effect. this register initializes the position of the internal eeprom within the on-chip system memory map. 76543210 r ee15 ee14 ee13 ee12 ee11 00 eeon w reset 1 ???????? 1. the reset state of this register is cont rolled at chip integration. please refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? to determine the actual reset state of this register. = unimplemented or reserved figure 19-5. initialization of internal eeprom posi tion register (initee) table 19-4. initee field descriptions field description 7:3 ee[15:11] internal eeprom map position ? these bits determine th e upper five bits of the base address for the system?s internal eeprom array. 0 eeon enable eeprom ? this bit is used to enable the eeprom memory in the memory map. 0 disables the eeprom from the memory map. 1 enables the eeprom in the memory map at the address selected by ee[15:11]. chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 547 19.3.2.4 miscellaneous system control register (misc) read: anytime write: as stated in each bit description note writes to this register take one cycle to go into effect. this register initializes mi scellaneous control functions. 76543210 r0000 exstr1 exstr0 romhm romon w reset: expanded or emulation 0000110? 1 reset: peripheral or single chip 00001101 reset: special test00001100 1. the reset state of this bit is determined at the chip integration level. = unimplemented or reserved figure 19-6. miscellaneous system control register (misc) table 19-5. misc field descriptions field description 3:2 exstr[1:0] external access stretch bits 1 and 0 write: once in normal and emulation modes and anytime in special modes this two-bit field determines the amount of clock stretc h on accesses to the external address space as shown in ta b l e 1 9 - 6 . in single chip and peripheral modes these bits have no meaning or effect. 1 romhm flash eeprom or rom only in second half of memory map write: once in normal and emulation modes and anytime in special modes 0 the fixed page(s) of flash eeprom or rom in the lower half of the memory map can be accessed. 1 disables direct access to the flash eeprom or rom in the lower half of the memory map. these physical locations of the flash eeprom or rom remain accessible through t he program page window. 0 romon romon ? enable flash eeprom or rom write: once in normal and emulation modes and anytime in special modes this bit is used to enable the flash eeprom or rom memory in the memory map. 0 disables the flash eeprom or rom from the memory map. 1 enables the flash eeprom or rom in the memory map. table 19-6. external stretch bit definition stretch bit exstr1 stretch bit exstr 0 number of e clocks stretched 00 0 01 1 10 2 11 3 chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 548 freescale semiconductor 19.3.2.5 reserved test register 0 (mtst0) read: anytime write: no effect ? this register loca tion is used for internal test purposes. 19.3.2.6 reserved test register 1 (mtst1) read: anytime write: no effect ? this register loca tion is used for internal test purposes. 76543210 r00000000 w reset00000000 = unimplemented or reserved figure 19-7. reserved test register 0 (mtst0) 76543210 r00000000 w reset00010000 = unimplemented or reserved figure 19-8. reserved test register 1 (mtst1) chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 549 19.3.2.7 memory size register 0 (memsiz0) read: anytime write: writes have no effect reset: defined at chip integration, see chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? . the memsiz0 register reflects the state of the register, eeprom a nd ram memory space configuration switches at the core boundary which are configured at system integration. this register allows read visibility to the stat e of these switches. 76543210 r reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 w reset???????? = unimplemented or reserved figure 19-9. memory size register 0 (memsiz0) table 19-7. memsiz0 field descriptions field description 7 reg_sw0 allocated system register space 0 allocated system register space size is 1k byte 1 allocated system register space size is 2k byte 5:4 eep_sw[1:0] allocated system eepr om memory space ? the allocated system eeprom memory space size is as given in ta bl e 1 9 - 8 . 2 ram_sw[2:0] allocated system ram memory space ? the allocated system ram memory space size is as given in ta b l e 1 9 - 9 . table 19-8. allocated eeprom memory space eep_sw1:eep_sw0 allocated eeprom space 00 0k byte 01 2k bytes 10 4k bytes 11 8k bytes table 19-9. allocated ram memory space ram_sw2:ram_sw0 allocated ram space ram mappable region initrm bits used ram reset base address 1 000 2k bytes 2k bytes ram[15:11] 0x0800 001 4k bytes 4k bytes ram[15:12] 0x0000 010 6k bytes 8k bytes 2 ram[15:13] 0x0800 011 8k bytes 8k bytes ram[15:13] 0x0000 chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 550 freescale semiconductor note as stated, the bits in this register provide read visibility to the system physical memory space allocations defi ned at system inte gration. the actual array size for any gi ven type of memory block ma y differ from the allocated size. please refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for actual sizes. 19.3.2.8 memory size register 1 (memsiz1) read: anytime write: writes have no effect reset: defined at chip integration, see chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? . the memsiz1 register reflects the state of th e flash or rom physical memory space and paging switches at the core boundary which are configured at system integration. this register allows read visibility to the stat e of these switches. 100 10k bytes 16k bytes 2 ram[15:14] 0x1800 101 12k bytes 16k bytes 2 ram[15:14] 0x1000 110 14k bytes 16k bytes 2 ram[15:14] 0x0800 111 16k bytes 16k bytes ram[15:14] 0x0000 1 the ram reset base address is based on the re set value of the init rm register, 0x0009. 2 alignment of the allocated ram space within the ram mappable region is dependent on the value of ramhal. 76543210 r rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0 w reset???????? = unimplemented or reserved figure 19-10. memory size register 1 (memsiz1) table 19-10. memsiz1 field descriptions field description 7:6 rom_sw[1:0] allocated system flash or rom physical memory space ? the allocated system flash or rom physical memory space is as given in table 19-11 . 1:0 pag_sw[1:0] allocated off-chip flash or rom memory space ? the allocated off-chip flash or rom memory space size is as given in table 19-12 . table 19-9. allocated ram memory space (continued) ram_sw2:ram_sw0 allocated ram space ram mappable region initrm bits used ram reset base address 1 chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 551 note as stated, the bits in this register provide read visibility to the system memory space and on-chip/off-chip pa rtitioning allocations defined at system integration. the actual array size for any given type of memory block may differ from the allocated size. please refer to chapter 1, ?mc9s12e256 device overvi ew (mc9s12e256dgv1)? for actual sizes. 19.3.2.9 program page index register (ppage) read: anytime write: determined at chip integrati on. generally it?s: ?write anytime in all modes;? on some devices it will be: ?write only in speci al modes.? check specific device doc umentation to determine which applies. reset: defined at chip integration as either 0x00 (paired with write in any mode) or 0x3c (paired with write only in special modes), see chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? . table 19-11. allocated flash/rom physical memory space rom_sw1:rom_sw0 allocated flash or rom space 00 0k byte 01 16k bytes 10 48k bytes (1) 11 64k bytes (1) notes: 1. the romhm software bit in the misc r egister determines the accessibility of the flash/rom memory space. please refer to section 19.3.2.8, ?memory size register 1 (memsiz1) ,? for a detailed functional description of the romhm bit. table 19-12. allocated off-chip memory options pag_sw1:pag_sw0 off-chip space on-chip space 00 876k bytes 128k bytes 01 768k bytes 256k bytes 10 512k bytes 512k bytes 11 0k byte 1m byte 76543210 r0 0 pix5 pix4 pix3 pix2 pix1 pix0 w reset 1 ???????? 1. the reset state of this register is cont rolled at chip integration. please refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? to determine the actual reset state of this register. = unimplemented or reserved figure 19-11. program page index register (ppage) chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 552 freescale semiconductor the hcs12 core architectur e limits the physical addr ess space available to 64k bytes. the program page index register allows for integrating up to 1m byte of flash or rom into the system by using the six page index bits to page 16k byte blocks into the program page window located from 0x8000 to 0xbfff as defined in table 19-14 . call and rtc instructions have special access to read and write this register without using the address bus. note normal writes to this register take one cycle to go into effect. writes to this register using the special access of th e call and rtc instructions will be complete before the end of the associated instruction. 19.4 functional description the mmc sub-block performs four ba sic functions of the core operati on: bus control, address decoding and select signal generation, memory expansion, and se curity decoding for the system. each aspect is described in the following subsections. 19.4.1 bus control the mmc controls the address bus and data buses that interface the core with the rest of the system. this includes the multiplexing of the input data buses to the core onto the ma in cpu read data bus and control table 19-13. ppage field descriptions field description 5:0 pix[5:0] program page index bits 5:0 ? these page index bits are used to select which of the 64 flash or rom array pages is to be accessed in the program page window as shown in ta b l e 1 9 - 1 4 . table 19-14. program page index register bits pix5 pix4 pix3 pix2 pix1 pix0 program space selected 000000 16k page 0 000001 16k page 1 000010 16k page 2 000011 16k page 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 0 0 16k page 60 1 1 1 1 0 1 16k page 61 1 1 1 1 1 0 16k page 62 1 1 1 1 1 1 16k page 63 chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 553 of data flow from the cpu to the output address and data buses of th e core. in additi on, the mmc manages all cpu read data bus swapping operations. 19.4.2 address decoding as data flows on the core address bus, the mmc decodes the address in formation, determines whether the internal core register or firmware space, the periphera l space or a memory register or array space is being addressed and generates the correct select signal. th is decoding operation also interprets the mode of operation of the system and the state of the mapping control re gisters in order to gene rate the proper select. the mmc also generates two external chip select signals, emulat ion chip select (ecs ) and external chip select (xcs ). 19.4.2.1 select priority and mode considerations although internal resources such as c ontrol registers and on-chip memory have default addresses, each can be relocated by changing the default values in control registers. norm ally, i/o addresses, control registers, vector spaces, expansion windows, and on-chip memo ry are mapped so that th eir address ranges do not overlap. the mmc wi ll make only one select signa l active at any given time. this activation is based upon the priority outlined in table 19-15 . if two or more blocks share the same address space, only the select signal for the block with the highest pr iority will become active. an example of this is if the registers and the ram are mapped to the same spac e, the registers will have priori ty over the ram and the portion of ram mapped in this shared space w ill not be accessible. the expansion windows have the lowest priority. this means that registers, vectors, and on-chip memory are always visible to a program regardless of the values in the page select registers. in expanded modes, all address spa ce not used by internal resources is by default external memory space. the data registers and data direct ion registers for ports a and b are removed from the on-chip memory map and become external acc esses. if the eme bit in the mode register (see chapter 18, ?multiplexed external bus interface (mebiv3)? ) is set, the data and data directi on registers for port e are also removed from the on-chip memory map and become external accesses. in special peripheral mode, the firs t 16 registers associated with bus expansion are removed from the on-chip memory map (porta, portb, ddra , ddrb, porte, ddre, pear, mode, pucr, rdriv, and the ebi reserved registers). table 19-15. select signal priority priority address space highest bdm (internal to core) firmware or register space ... internal register space ... ram memory block ... eeprom memory block ... on-chip flash or rom lowest remaining external space chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 554 freescale semiconductor in emulation modes, if the emk bit in the mode register (see chapter 18, ?multiplexed external bus interface (mebiv3)? ) is set, the data and data direction regi sters for port k are rem oved from the on-chip memory map and become external accesses. 19.4.2.2 emulation chip select signal when the emk bit in the mode register (see chapter 18, ?multiplexed external bus interface (mebiv3)? ) is set, port k bit 7 is used as an act ive-low emulation chip select signal, ecs . this signal is active when the system is in em ulation mode, the emk bit is set a nd the flash or rom space is being addressed subject to th e conditions outlined in section 19.4.3.2, ?extended addr ess (xab19:14) and ecs signal functionality .? when the emk bit is clear, this pin is used for general purpose i/o. 19.4.2.3 external chip select signal when the emk bit in the mode register (see chapter 18, ?multiplexed external bus interface (mebiv3)? ) is set, port k bit 6 is used as an ac tive-low external chip select signal, xcs . this signal is active only when the ecs signal described above is not active a nd when the system is addressing the external address space. accesses to unimplemented locations within the re gister space or to locations that are removed from the map (i.e., ports a and b in expa nded modes) will not cause this signal to become active. when the emk bit is clear, th is pin is used for general purpose i/o. 19.4.3 memory expansion the hcs12 core architectur e limits the physical addr ess space available to 64k bytes. the program page index register allows for integrating up to 1m byte of flash or rom into the system by using the six page index bits to page 16k byte blocks into the program page window located from 0x8000 to 0xbfff in the physical memory space. the paged memory space can consist of sole ly on-chip memory or a combination of on-chip and off-chip memory. this partitioni ng is configured at sy stem integration through the use of the paging c onfiguration switches ( pag_sw1:pag_sw0 ) at the core boundary. the options available to the integrator are as given in table 19-16 (this table matches table 19-12 but is repeated here for easy reference). based upon the system configuration, the program page window will cons ider its access to be either internal or external as defined in table 19-17 . table 19-16. allocated off-chip memory options pag_sw1:pag_sw0 off-chip space on-chip space 00 876k bytes 128k bytes 01 768k bytes 256k bytes 10 512k bytes 512k bytes 11 0k byte 1m byte chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 555 note the partitioning as defined in table 19-17 applies only to the allocated memory space and the actual on-chip memory sizes implemented in the system may differ. please refer to chapter 1, ?mc9s12e256 device overview (mc9s12e256dgv1)? for actual sizes. the ppage register holds the page select value fo r the program page window. the value of the ppage register can be manipulated by normal read and writ e (some devices don?t allow writes in some modes) instructions as well as the call and rtc instructions. control registers, vector spaces, and a portion of on- chip memory are located in unpaged portions of the 64k byte physical address space. the stack and i/o addresses should also be in unpaged memory to make them accessible from any page. the starting address of a service routine must be located in unpaged memory because the 16-bit exception vectors cannot point to addr esses in paged memory. however, a servi ce routine can call ot her routines that are in paged memory. the upper 16k byte block of memory space (0xc000?0xffff) is unpaged. it is recommended that all reset and interrupt v ectors point to locations in this area. 19.4.3.1 call and return from call instructions call and rtc are uninterruptable in structions that automa te page switching in the program expansion window. call is similar to a jsr instru ction, but the subroutine that is ca lled can be located anywhere in the normal 64k byte address space or on any page of program expansion memo ry. call calculates and stacks a return address, stacks the current ppage valu e, and writes a new instruction-supplied value to ppage. the ppage value controls which of the 64 possible pages is visible through the 16k byte expansion window in the 64k byte memory map. executi on then begins at the address of the called subroutine. table 19-17. external/internal page window access pag_sw1:pag_sw0 partitioning pix5:0 value page window access 00 876k off-chip, 128k on-chip 0x0000?0x0037 external 0x0038?0x003f internal 01 768k off-chip, 256k on-chip 0x0000?0x002f external 0x0030?0x003f internal 10 512k off-chip, 512k on-chip 0x0000?0x001f external 0x0020?0x003f internal 11 0k off-chip, 1m on-chip n/a external 0x0000?0x003f internal chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 556 freescale semiconductor during the execution of a call instruction, the cpu: ? writes the old ppage value into an intern al temporary register and writes the new instruction-supplied ppage valu e into the ppage register. ? calculates the address of the next instruction after the call instru ction (the return address), and pushes this 16-bit value onto the stack. ? pushes the old ppage value onto the stack. ? calculates the effective address of the subroutine, refills the queue , and begins execution at the new address on the selected page of the expansion window. this sequence is uninterruptable; there is no need to inhibit interrupts during call execution. a call can be performed from any address in memory to any other address. the ppage value supplied by the instruction is part of the effective address. for all addressing mode variations except indexed- indirect modes, the new pa ge value is provided by an immediate operand in the instruction. in indexed-indirect va riations of call, a pointer specif ies memory locations where the new page value and the address of the called subroutine ar e stored. using indirect addressing for both the new page value and the address within the page allows va lues calculated at run ti me rather than immediate values that must be known at the time of assembly. the rtc instruction terminates subroutines invoked by a call in struction. rtc unstacks the ppage value and the return address and re fills the queue. execution resumes with the next instruction after the call. during the execution of an rtc instruction, the cpu: ? pulls the old ppage value from the stack ? pulls the 16-bit return address from the stack and loads it into the pc ? writes the old ppage value into the ppage register ? refills the queue and resumes ex ecution at the return address this sequence is uninterruptable; an rtc can be executed from anyw here in memory, even from a different page of extended memory in the expansion window. the call and rtc instructions be have like jsr and rts, except they use more execution cycles. therefore, routinely substituting call/rtc for jsr/rts is not recomm ended. jsr and rts can be used to access subroutines that are on the same page in expanded memory. however, a subroutine in expanded memory that can be called from other pages must be terminated with an rtc. and the rtc unstacks a ppage value. so any access to the subroutine, even fr om the same page, must use a call instruction so that the correct ppage value is in the stack. 19.4.3.2 extended addres s (xab19:14) and ecs signal functionality if the emk bit in the mode register is set (see chapter 18, ?multiplexed external bus interface (mebiv3)? ) the pix5:0 values will be out put on xab19:14 respect ively (port k bits 5:0) when the system is addressing within the physi cal program page window address space (0x8000?0xbfff) and is in an expanded mode. when addressi ng anywhere else within the physical address space (outside of the paging space), the xab19:14 signals will be assigned a c onstant value based upon th e physical address space chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 557 selected. in addition, the active-low emulation chip select signal, ecs , will likewise function based upon the assigned memory allocation. in the cases of 48k byte and 64k byte allocated physical flash/rom space, the operation of the ecs signal will additionally depend upon the state of the romhm bit (see section 19.3.2.4, ?miscellaneous syst em control register (misc) ?) in the misc register. table 19-18 , table 19-19 , table 19-20 , and table 19-21 summarize the functionality of these signals based upon the allocated memory configuration. agai n, this signal information is only av ailable externally when the emk bit is set and the system is in an expanded mode. table 19-18. 0k byte physical flash/rom allocated address space page window access romhm ecs xab19:14 0x0000?0x3fff n/a n/a 1 0x3d 0x4000?0x7fff n/a n/a 1 0x3e 0x8000?0xbfff n/a n/a 0 pix[5:0] 0xc000?0xffff n/a n/a 0 0x3f table 19-19. 16k byte physical flash/rom allocated address space page window access romhm ecs xab19:14 0x0000?0x3fff n/a n/a 1 0x3d 0x4000?0x7fff n/a n/a 1 0x3e 0x8000?0xbfff n/a n/a 1 pix[5:0] 0xc000?0xffff n/a n/a 0 0x3f table 19-20. 48k byte physical flash/rom allocated address space page window access romhm ecs xab19:14 0x0000?0x3fff n/a n/a 1 0x3d 0x4000?0x7fff n/a 0 0 0x3e n/a 1 1 0x8000?0xbfff external n/a 1 pix[5:0] internal n/a 0 0xc000?0xffff n/a n/a 0 0x3f table 19-21. 64k byte physical flash/rom allocated address space page window access romhm ecs xab19:14 0x0000?0x3fff n/a 0 0 0x3d n/a 1 1 0x4000?0x7fff n/a 0 0 0x3e n/a 1 1 0x8000?0xbfff external n/a 1 pix[5:0] internal n/a 0 0xc000?0xffff n/a n/a 0 0x3f chapter 19 module mapping control (mmcv4) mc9s12e256 data sheet, rev. 1.08 558 freescale semiconductor a graphical example of a memory pa ging for a system configured as 1m byte on-chip flash/rom with 64k allocated physical space is given in figure 19-12 . figure 19-12. memory paging example: 1m byte on-chip flash/rom, 64k allocation these 16k flash/rom pages accessible from 0x0000 to 0x7fff if selected by the romhm bit in the misc register. normal single chip one 16k flash/rom page accessible at a time (selected by ppage = 0 to 63) 0x0000 0x8000 0xff00 0xffff 0x4000 0xc000 59 62 63 60 61 62 63 0123 61 16k flash (unpaged) 16k flash (unpaged) 16k flash (paged) 16k flash (unpaged) vectors mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 559 appendix a electrical characteristics a.1 general note the electrical characteris tics given in this sec tion are preliminary and should be used as a guide only. va lues cannot be guaranteed by freescale and are subject to change without notice. the part is specified and tested over the 5v and 3.3v ranges. for the intermediate range, generally the elect rical specifications for the 3.3v range apply, but the part is not tested in production test in the intermediate range. this supplement contains the most accurate electrical information for the mc9s12e-family microcontroller available at the time of publication. the info rmation should be considered preliminary and is subject to change. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate. note this classification will be added at a later release of the specification p: those parameters are guaranteed during pr oduction testing on each individual device. c: those parameters are achieved by the design char acterization by measuring a statistically relevant sample size across process vari ations. they are regularly ve rified by production monitors. t: those parameters are achieve d by design characterizati on on a small sample size from typical devices. all values shown in the typical column are within this category. d: those parameters are derive d mainly from simulations. appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 560 freescale semiconductor a.1.2 power supply the mc9s12e-family utilizes several pins to supply power to the i/o ports, a/d converter, oscillator, pll and internal logic. the vdda, vssa pair supplies the a/d converter and d/a converter. the vddx, vssx pair supplies the i/o pins the vddr, vssr pair supplies th e internal voltage regulator. vdd1, vss1, vdd2 and vss2 are the s upply pins for the internal logic. vddpll, vsspll supply the oscillator and the pll. vss1 and vss2 are internally connected by metal. vdd1 and vdd2 are internally connected by metal. vdda, vddx, vddr as well as vssa, vssx, v ssr are connected by anti-parallel diodes for esd protection. note in the following context vdd5 is used for either vdda, vddr and vddx; vss5 is used for either vs sa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the curren ts flowing into the vdda, vddx and vddr pins. vdd is used for vdd1, vdd2 and vddpll, vss is used for vss1, vss2 and vsspll. idd is used for the sum of the cu rrents flowing into vdd1 and vdd2. appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 561 a.1.3 pins there are four groups of functional pins. a.1.3.1 3.3v/5v i/o pins those i/o pins have a nominal le vel of 3.3v or 5v depending on the application operating point. this group of pins is comprised of all port i/o pins, th e analog inputs, bkgd pin and the reset inputs.the internal structure of all those pins is identical, however some of the functionality may be disabled. a.1.3.2 analog reference this group of pins is compri sed of the vrh and vrl pins. a.1.3.3 oscillator the pins xfc, extal, xtal dedica ted to the oscillator have a nominal 2.5v leve l. they are supplied by vddpll. a.1.3.4 test this pin is used for production testing only. a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd5 ) is greater than i dd5 , the injection current ma y flow out of v dd5 and could result in external power supply going out of regulation. insure external v dd5 load will shunt current greater than maxi mum injection current. this will be the greatest risk when the mcu is not consuming power; e.g. if no system cl ock is present, or if clock rate is very low which would reduce overall power consumption. appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 562 freescale semiconductor a.1.5 absolute maximum ratings absolute maximum ratings are stre ss ratings only. a functional operatio n under or outside those maxima is not guaranteed. stre ss beyond those limits may affe ct the reliability or caus e permanent damage of the device. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). table a-1. absolute maximum ratings num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 ?0.3 6.5 v 2 internal logic supply voltage 1 1 the device contains an internal voltage regulator to generat e the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd ?0.3 3.0 v 3 pll supply voltage 1 v ddpll ?0.3 3.0 v 4 voltage difference vddx to vddr and vdda ? vddx ?0.3 0.3 v 5 voltage difference vssx to vssr and vssa ? vssx ?0.3 0.3 v 6 digital i/o input voltage v in ?0.3 6.5 v 7 analog reference v rh, v rl ?0.3 6.5 v 8 xfc, extal, xtal inputs v ilv ?0.3 3.0 v 9 test input v test ?0.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins 2 2 all digital i/o pins are internally clamped to v ssx and v ddx , v ssr and v ddr or v ssa and v dda . i d ?25 +25 ma 11 instantaneous maximum current single pin limit for xfc, extal, xtal 3 3 these pins are internally clamped to v sspll and v ddpll i dl ?25 +25 ma 12 instantaneous maximum current single pin limit for test 4 4 this pin is clamped low to v ssr , but not clamped high. this pin must be tied low in applications. i dt ?0.25 0 ma 13 operating temperature range (packaged) t a ? 40 125 c 14 operating temperature range (junction) t j ? 40 140 c 15 storage temperature range t stg ? 65 155 c appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 563 a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qua lification for automotive grade integrated circuits. during the device qualification esd stresses we re performed for the human body model (hbm), the machine model ( mm) and the charge device model. a device will be defined as a fail ure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametr ic and functional testing is perf ormed per the applicable device specification at room temperature followed by hot te mperature, unless specified otherwise in the device specification. table a-2. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative ? ? 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative ? ? 3 3 latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v table a-3. esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 ? v 2 c machine model (mm) v mm 200 ? v 3 c charge device model (cdm) v cdm 500 ? v 4 c latch-up current at 125 c positive negative i lat +100 -100 ? ? ma 5 c latch-up current at 27 c positive negative i lat +200 -200 ? ? ma appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 564 freescale semiconductor a.1.7 operating conditions this chapter describes the opera ting conditions of the device. unle ss otherwise noted those conditions apply to all the following data. note instead of specifying ambient temperat ure all parameters are specified for the more meaningful silicon juncti on temperature. for power dissipation calculations refer to section a.1.8, ?power dissipation and thermal characteristics? . a.1.8 power dissipation an d thermal characteristics power dissipation and thermal character istics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j ) in c can be obtained from: the total power dissipation can be calculated from: table a-4. operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd5 2.97 3.3/5 5.5 v internal logic supply voltage 1 1 the device contains an internal voltage regulator to gener ate the logic and pll supply out of the i/o supply. the given operating range applies when this regulator is disabled and the device is powered from an external source. v dd 2.35 2.5 2.75 v pll supply voltage 1 v ddpll 2.35 2.5 2.75 v voltage difference vddx to vdda ? vddx ?0.1 0 0.1 v voltage difference vssx to vssr and vssa ? vssx ?0.1 0 0.1 v oscillator f osc 0.5 ? 16 mhz bus frequency 2 2 some blocks e.g. atd (conversion) and nvms (program/era se) require higher bus frequencies for proper operation. f bus 0.25 ? 25 mhz operating junction temperature range t j ?40 ? 140 c t j t a p d ja ? () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] = ja package thermal resistance, [ c/w] = p d p int p io + = p int chip internal power dissipation, [w] = appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 565 two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled which is the sum of all out put currents on i/o ports a ssociated with vddx and vddm. for r dson is valid: respectively 2. internal voltage regulator enabled i ddr is the current shown in table a-8 and not the overall current flowing into vddr, which additionally contains the current flowing into the external loads with output high. which is the sum of all out put currents on i/o ports a ssociated with vddx and vddr. table a-5. thermal package characteristics 1 1 the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit 1 t thermal resistance lqfp112, single sided pcb 2 2 pc board according to eia/jedec standard 51-3 ja ??54 o c/w 2 t thermal resistance lqfp112, double sided pcb with 2 internal planes 3 3 pc board according to eia/jedec standard 51-7 ja ??41 o c/w 3 t junction to board lqfp112 jb ??31 o c/w 4 t junction to case lqfp112 jc ??11 o c/w 5 t junction to package top lqfp112 jt ?? 2 o c/w 6 t thermal resistance qfp 80, single sided pcb ja ??51 o c/w 7 t thermal resistance qfp 80, double sided pcb with 2 internal planes ja ??41 o c/w 8 t junction to board qfp80 jb ??27 o c/w 9 t junction to case qfp80 jc ??14 o c/w 10 t junction to package top qfp80 jt ?? 3 o c/w p int i dd v dd ? i ddpll v ddpll ? i dda +v dda ? + = p io r dson i i io i 2 ? = r dson v ol i ol ------------ f o r o u t p u t s d r i v e n l o w ; = r dson v dd5 v oh ? i oh ------------------------------------ f o r o u t p u t s d r i v e n h i g h ; = p int i ddr v ddr ? i dda v dda ? + = p io r dson i i io i 2 ? = appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 566 freescale semiconductor a.1.9 i/o characteristics this section describes the characteristics of all 3.3v/5 v i/o pins. all parameters are not always applicable, e.g., not all pins featur e pull up/down resistances. table a-6. 5v i/o characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 ??v t input high voltage v ih ??v dd5 + 0.3 v 2 p input low voltage v il ? ? 0.35*v dd5 v t input low voltage v il v ss5 ? 0.3 ? ? v 3 c input hysteresis v hys ?250?mv 4 p input leakage current (pins in high ohmic input mode) 1 v in = v dd5 or v ss5 1 maximum leakage current occurs at maximum operating temperatur e. current decreases by approximately one-half for each 8c to 12c in the temperature range from 50c to 125c. i in ?1.0 ? 1.0 a 5 c output high voltage (pins in output mode) partial drive i oh = ?2ma v oh v dd5 ? 0.8 ? ? v 6 p output high voltage (pins in output mode) full drive ioh = ?10ma v oh v dd5 ? 0.8 ? ? v 7 c output low voltage (pins in output mode) partial drive iol = +2ma v ol ??0.8v 8 p output low voltage (pins in output mode) full drive i ol = +10ma v ol ??0.8v 9 p internal pull up device current, tested at v il max. i pul ? ? ?130 a 10 c internal pull up device current, tested at v ih min. i puh ?10 ? ? a 11 p internal pull down device current, tested at v ih min. i pdh ??130 a 12 c internal pull down device current, tested at v il max. i pdl 10 ? ? a 13 d input capacitance c in ?6?pf 14 t injection current 2 single pin limit total device limit. sum of all injected currents 2 refer to section a.1.4, ?current injection? for more details i ics i icp ?2.5 ?25 ? ? 2.5 25 ma 15 p port ad interrupt input pulse filtered 3 3 parameter only applies in stop or pseudo stop mode. t pign ?? 3 s 16 p port ad interrupt input pulse passed 3 t pval 10 ? ? s appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 567 a.1.10 supply currents this section describes the current consumption character istics of the device as well as the conditions for the measurements. table a-7. preliminary 3.3v i/o characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 ??v t input high voltage v ih ??v dd5 + 0.3 v 2 p input low voltage v il ? ? 0.35*v dd5 v t input low voltage v il v ss5 ? 0.3 ? ? v 3 c input hysteresis v hys 250 mv 4 p input leakage current (pins in high ohmic input mode) 1 v in = v dd5 or v ss5 1 maximum leakage current occurs at maximum operating temperatur e. current decreases by approximately one-half for each 8c to 12c in the temperature range from 50c to 125c. i in ?1.0 ? 1.0 a 5 c output high voltage (pins in output mode) partial drive i oh = ?0.75ma v oh v dd5 ? 0.4 ? ? v 6 p output high voltage (pins in output mode) full drive i oh = ?4ma v oh v dd5 ? 0.4 ? ? v 7 c output low voltage (pins in output mode) partial drive i ol = +0.9ma v ol ??0.4v 8 p output low voltage (pins in output mode) full drive i ol = +4.75ma v ol ??0.4v 9 p internal pull up device current, tested at v il max. i pul ? ? ?60 a 10 c internal pull up device current, tested at v ih min. i puh ?6 ? ? a 11 p internal pull down device current, tested at v ih min. i pdh ??60 a 12 c internal pull down device current, tested at v il max. i pdl 6?? a 13 d input capacitance c in ?6?pf 14 t injection current 2 single pin limit total device limit. sum of all injected currents 2 refer to section a.1.4, ?current injection? , for more details i ics i icp ?2.5 ?25 ? ? 2.5 25 ma 15 p port ad interrupt input pulse filtered 3 3 parameter only applies in stop or pseudo stop mode. t pign ?? 3 s 16 p port ad interrupt input pulse passed 3 t pval 10 ? ? s appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 568 freescale semiconductor a.1.10.1 measurement conditions all measurements are without output loads. unless ot herwise noted the currents are measured in single chip mode, internal volta ge regulator enabled and at 25mhz bus frequency using a 4mhz oscillator. a.1.10.2 additional remarks in expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. no generally applicable numbers can be given. a very good estimate is to take the single chip cu rrents and add the currents due to the external loads. table a-8. supply current characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 p run supply currents single chip, internal regulator enabled i dd5 ??65 ma 2 p p wait supply current all modules enabled only rti enabled i ddw ? ? ? ? 40 5 ma 3 c c c c c c c pseudo stop current (rti and cop enabled) 1, 2 ?40 c 27 c 70 c 85 c 105 c 125 c 140 c 1 pll off 2 at those low power dissipation levels t j = t a can be assumed i ddps ? ? ? ? ? ? ? 570 600 650 750 850 1200 1500 ? ? ? ? ? ? ? a 4 c p c c p c p c p pseudo stop current (rti and cop disabled) 1,2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i ddps ? ? ? ? ? ? ? ? ? 370 400 450 550 600 650 800 850 1200 ? 500 ? ? 1600 ? 2100 ? 5000 a 5 c p c c p c p c p stop current 2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i dds ? ? ? ? ? ? ? ? ? 12 30 100 130 160 200 350 400 600 ? 100 ? ? 1200 ? 1700 ? 5000 a appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 569 a.2 voltage regulator this section describes the characterist ics of the on chip voltage regulator. table a-9. voltage regulator electrical parameters num c characteristic symbol min typ max unit 1 p input voltages v vddr,a 2.97 ? 5.5 v 3 p output voltage core full performance mode v dd 2.35 2.5 2.75 v 4 p output voltage pll full performance mode v ddpll 2.35 2.5 2.75 v 5 p low voltage interrupt 1 assert level deassert level 1 monitors v dda , active only in full performance mode. indicates i/o & adc performance degradation due to low supply voltage. v lv i a v lv i d 4.0 4.15 4.37 4.52 4.66 4.77 v v 6 p low voltage reset 2 assert level deassert level 2 monitors v dd , active only in full performance mode. v lv r a and v pord must overlap v lv r a v lv r d 2.25 ? ? ? ? 2.55 v v 7 c power-on reset 3 assert level deassert level 3 monitors v dd . active in all modes. v pora v pord 0.97 ? --- --- ? 2.05 v v appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 570 freescale semiconductor a.2.1 chip power-up and lvi/lvr graphical explanation voltage regulator sub modules lvi (low voltage inte rrupt), por (power-on rese t) and lvr (low voltage reset) handle chip power-up or drops of the supply voltage. their func tion is described in figure a-1 . figure a-1. voltage regulator ? chip power-up and voltage drops (not scaled) v lvid v lvia v lvrd v lvra v pord lvi por lvr t v v dda v dd lvi enabled lvi disabled due to lvr appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 571 a.2.2 output loads a.2.2.1 resistive loads the on-chip voltage regulator is intended to supply th e internal logic and oscill ator circuits allows no external dc loads. a.2.2.2 capacitive loads the capacitive loads are specified in table a-10 . ceramic capacitors with x7 r dielectricum are required. a.3 startup, oscillator, and pll a.3.1 startup table a-11 summarizes several startup character istics explained in this section. table a-10. voltage regulator ? capacitive loads num characteristic symbol min typ max unit 1v dd external capacitive load c ddext 200 440 12000 nf 2v ddpll external capacitive load c ddpllext 90 220 5000 nf table a-11. startup characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 t por release level v porr ? ? 2.07 v 2 t por assert level v pora 0.97 ? ? v 3 d reset input pulse width, minimum input time pw rstl 2 ? ? t osc 4 d startup from reset n rst 192 ? 196 n osc 5 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ? ? ns 6 d wait recovery startup time t wrs ? 14 t cyc 7 p lvr release level v lv r r 2.25 ? ? v 8 p lvr assert level v lv r a ? ? 2.55 v appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 572 freescale semiconductor a.3.1.1 por the release level v porr and the assert level v pora are derived from the v dd supply. they are also valid if the device is powered ex ternally. after releasing the por reset th e oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is dete cted, the mcu will start using the internal self clock. the fastest startup ti me possible is given by n uposc . a.3.1.2 lvr the release level v lvrr and the assert level v lvra are derived from the v dd supply. they are also valid if the device is powered externally. after releasing th e lvr reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is dete cted, the mcu will start using the internal self clock. the fastest startup ti me possible is given by n uposc . a.3.1.3 sram data retention provided an appropriate external re set signal is applied to the mcu, preventing the cpu from executing code when vdd5 is out of specifica tion limits, the sram contents integr ity is guaranteed if after the reset the porf bit in the crg flags register has not been set. a.3.1.4 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock qualit y check, if there was an oscillation before reset. a.3.1.5 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasi ng the clocks to the system. a.3.1.6 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same sinc e the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 573 a.3.2 oscillator the device features an internal colpit ts and pierce oscillator. the selecti on of colpitts osci llator or pierce oscillator/external cloc k depends on the xclks signal which is sample d during reset. pierce oscillator/external clock m ode allows the input of a square wave. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start fr om either power-on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or stop if a proper oscillat ion is not detected. the quality ch eck also determines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a clock monitor failure is asserted if the frequency of the incoming cl ock signal is below the assert frequency f cmfa . table a-12. oscillator characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (colpitts) f osc 0.5 ? 16 mhz 1b c crystal oscillator range (pierce) 1 1 depending on the crystal a damping series resistor might be necessary f osc 0.5 ? 40 mhz 2 p startup current i osc 100 ? ? a 3 c oscillator start-up time (colpitts) t uposc ? 8 2 2 f osc = 4mhz, c = 22pf. 100 3 3 maximum value is for extreme cases using high q, low frequency crystals ms 4 d clock quality check time-out t cqout 0.45 2.5 s 5 p clock monitor failure assert frequency f cmfa 50 100 200 khz 6 p external square wave input frequency 4 4 only valid if pierce oscillator/external clock mode is selected f ext 0.5 ? 50 mhz 7 d external square wave pulse width low 4 t extl 9.5 ? ? ns 8 d external square wave pulse width high 4 t exth 9.5 ? ? ns 9 d external square wave rise time 4 t extr ? ? 1 ns 10 d external square wave fall time 4 t extf ? ? 1 ns 11 d input capacitance (extal, xtal pins) c in ? 7 pf 12 c dc operating bias in colpitts configuration on extal pin v dcbias ? 1.1 ? v 13 p extal pin input high voltage 4 v ih,extal 0.75*v ddpll ? ? v t extal pin input high voltage 4 v ih,extal ? ? v ddpll + 0.3 v 14 p extal pin input low voltage 4 v il,extal ? ? 0.25*v ddpll v t extal pin input low voltage 4 v il,extal v sspll ? 0.3 ? ? v 15 c extal pin input hysteresis 4 v hys,extal ? 250 ? mv appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 574 freescale semiconductor a.3.3 phase locked loop the oscillator provides the referenc e clock for the pll. the plls volt age controlled oscillator (vco) is also the system clock s ource in self clock mode. a.3.3.1 xfc component selection this section describes the selection of the xfc co mponents to achieve a good fi lter characteristics. figure a-2. basic pll functional diagram the following procedure can be used to calculate the resistan ce and capacitance values using typical values for k 1 , f 1 and i ch from table a-13 . the grey boxes show the calculation for f vco = 50mhz and f ref = 1mhz. e.g., these fr equencies are used for f osc = 4mhz and a 25mhz bus clock. the vco gain at the desired vc o frequency is approximated by: the phase detector re lationship is given by: i ch is the current in tracking mode. f osc 1 refdv+1 f ref phase detector vco k v 1 synr+1 f vco loop divider k 1 2 ? f cmp c s r c p vddpll xfc pin k v k 1 e f 1 f vco ? () k 1 1v ? --------------------------- - ? = 100 ? e 60 50 ? () 100 ? ----------------------- - ? = = -90.48mhz/v k i ch ? k v ? = = 316.7hz/ ? appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 575 the loop bandwidth f c should be chosen to fulfill the gar dner?s stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response. and finally the frequency relationship is defined as with the above values the resistance can be cal culated. the example is shown for a loop bandwidth f c =10khz: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: a.3.3.2 jitter information the basic functionality of the pll is shown in figure a-2 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature a nd other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects th e real minimum and maximum cloc k periods as illustrated in figure a-3 . f c 2 f ref ?? 1 2 + + ?? ?? ? ------------------------------------------ - 1 10 ------ f c f ref 410 ? -------------- 0.9 = () ; < ? < f c < 25khz n f vco f ref --------------- 2 s y n r 1 + () ? == = 50 r 2 nf c ??? k ----------------------------- = = 2* *50*10khz/(316.7hz/ ? ) =9.9k ? =~10k ? c s 2 2 ? f c r ?? ---------------------- 0.516 f c r ? -------------- - 0.9 = () ; = = 5.19nf =~ 4.7nf c s 20 ? c p c s 10 ? ? c p = 470pf appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 576 freescale semiconductor figure a-3. jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: for n < 100, the following equation is a good fit for the maximum jitter: this is very important to notice wi th respect to timers, serial modules where a prescaler will eliminate the effect of the jitter to a large extent. 23 n-1n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom ? ---------------------- - ? 1 t min n () nt nom ? ---------------------- - ? , ?? ?? ?? = jn () j 1 n -------- j 2 + = 1 5 10 20 n j(n) appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 577 table a-13. pll characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1?5.5mhz 2 d vco locking range f vco 8?50mhz 3 d lock detector transition from acquisition to tracking mode |? trk |3 ? 4% 1 1 % deviation from target frequency 4 d lock detection |? lock |0 ? 1.5% 1 5 d un-lock detection |? unl |0.5 ? 2.5% 1 6 d lock detector transition from tracking to acquisition mode |? unt |6 ? 8% 1 7 c pllon total stabilization delay (auto mode) 2 2 f osc = 4mhz, f bus = 25mhz equivalent f vco = 50mhz: refdv = #$03, synr = #$018, cs = 4.7nf, cp = 470pf, rs = 10k ? . t stab ?0.5 ?ms 8 d pllon acquisition mode stabilization delay 2 t acq ?0.3 ?ms 9 d pllon tracking mode stabilization delay 2 t al ?0.2 ?ms 10 d fitting parameter vco loop gain k 1 ? -100 ? mhz/v 11 d fitting parameter vco loop frequency f 1 ?60 ?mhz 12 d charge pump current acquisition mode | i ch |?38.5? a 13 d charge pump current tracking mode | i ch |?3.5 ? a 14 c jitter fit parameter 1 2 j 1 ??1.1% 15 c jitter fit parameter 2 2 j 2 ? ? 0.13 % appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 578 freescale semiconductor a.4 flash nvm a.4.1 nvm timing the time base for all nvm program or erase opera tions is derived from th e oscillator. a minimum oscillator frequency f nvmosc is required for performi ng program or erase operations. the nvm modules do not have any means to monitor the frequency an d will not prevent program or erase operation at frequencies above or belo w the specified minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash program and erase operati ons are timed using a clock derive d from the oscillator using the fclkdiv register. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in table a-14 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2mhz. a.4.1.1 single word programming the programming time for single word programming is dependent on the bus frequency as a well as on the frequency f nvmop and can be calculated accord ing to the following formula. a.4.1.2 row programming flash programming where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled. the time to program a consecutive word can be calculated as: the time to program a whole row is: row programming is more than 2 times faster than single word programming. a.4.1.3 sector erase erasing a 1024 byte flash sector takes: the setup times can be ignored for this operation. t swpgm 9 1 f nvmop ------------------------ - ? 25 1 f bus ----------- - ? + = t bwpgm 4 1 f nvmop ------------------------ - ? 9 1 f bus ----------- - ? + = t brpgm t swpgm 63 t bwpgm ? + = t era 4000 1 f nvmop ------------------------ - ? appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 579 a.4.1.4 mass erase erasing a nvm block takes: the setup times can be ignored for this operation. a.4.1.5 blank check the time it takes to perfor m a blank check on the flas h is dependant on the locat ion of the first non-blank word starting at relative address zero. it takes one bus cycle per word to verify plus a setup of the command. table a-14. nvm timing characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 ? 50 1 1 restrictions for oscillator in crystal mode apply! mhz 2 d bus frequency for programming or erase operations f nvmbus 1??mhz 3 d operating frequency f nvmop 150 ? 200 khz 4 p single word programming time t swpgm 46 2 2 minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . ?74.5 3 3 maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus. refer to formulae in section a.4.1.1, ?singl e word programming? through section a.4.1.4, ?mass erase? for guidance. s 5 d flash burst programming consecutive word t bwpgm 20.4 2 ?31 3 s 6 d flash burst programming time for 64 word row t brpgm 1331.2 2 ? 2027.5 3 s 7 p sector erase time t era 20 4 4 minimum erase times are achieved under maximum nvm operating frequency f nvmop . ?26.7 3 ms 8 p mass erase time t mass 100 4 ?133 3 ms 9 d blank check time flash per block t check 11 5 5 minimum time, if first word in the array is not blank ? 65546 6 6 maximum time to complete check on an erased block 7 t cyc 7 where t cyc is the system bus clock period. t mass 20000 1 f nvmop ------------------------ - ? t check location t cyc 10 t cyc ? + ? appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 580 freescale semiconductor a.4.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualific ation, constant process monitors and burn-in to screen early life failur es. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. figure a-4. typical endurance table a-15. nvm reliability characteristics 1 1 t javg will not exeed 85 c considering a typical temperature profile over the lifetime of a consumer, industrial or automotive application. conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit flash reliability characteristics 1 c data retention after 10,000 program/erase cycles at an average junction temperature of t javg 85 c t flret 15 100 2 2 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618. ? years 2 c data retention with <100 program/erase cycles at an average junction temperature t javg 85 c 20 100 2 ? 3 c number of program/erase cycles (?40 c t j 0 c) n fl 10,000 ? ? cycles 4 c number of program/erase cycles (0 c t j 140 c) 10,000 100,000 3 3 spec table quotes typical endurance evaluated at 25 c for this product family, typical endurance at various temperature can be estimated using the graph below. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619. ? typical endurance [103 cycles] operating temperature t j [ c] 0 50 100 150 200 250 300 350 400 450 500 ?40 ?20 0 20 40 60 80 100 120 140 ------ flash appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 581 a.5 spi characteristics this section provides electrical pa rametrics and ratings for the spi. in table a-16 the measurement conditions are listed. a.5.1 master mode in figure a-5 the timing diagram for master mode with transmission format cpha=0 is depicted. figure a-5. spi master timing (cpha = 0) table a-16. measurement conditions description value unit drive mode full drive mode ? load capacitance c load, on all outputs 50 pf thresholds for delay measurement points (20% / 80%) v ddx v sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1.if configured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 12 12 appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 582 freescale semiconductor in figure a-6 the timing diagram for master mode with transmission format cpha=1 is depicted. figure a-6. spi master timing (cpha=1) in table a-17 the timing characteristics for master mode are listed. table a-17. spi master mode timing characteristics num c characteristic symbol min typ max unit 1 p sck frequency f sck 1/2048 ? 1 / 2f bus 1 p sck period t sck 2 ? 2048 t bus 2 d enable lead time t lead ?1/2? t sck 3 d enable lag time t lag ?1/2? t sck 4 d clock (sck) high or low time t wsck ?1/2? t sck 5 d data setup time (inputs) t su 8??ns 6 d data hold time (inputs) t hi 8??ns 9 d data valid after sck edge t vsck ? ? 30 ns 10 d data valid after ss fall (cpha = 0) t vss ? ? 15 ns 11 d data hold time (outputs) t ho 20 ? ? ns 12 d rise and fall time inputs t rfi ?? 8 ns 13 d rise and fall time outputs t rfo ?? 8 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 2 12 13 3 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 583 a.5.2 slave mode in figure a-7 the timing diagram for slave mode with tr ansmission format cpha = 0 is depicted. figure a-7. spi slave timing (cpha = 0) in figure a-8 the timing diagram for slave mode with tr ansmission format cpha = 1 is depicted. figure a-8. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not defined! 12 12 11 see 13 note 8 10 see note sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not defined! slave 7 8 see note appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 584 freescale semiconductor in table a-18 the timing characteristics for slave mode are listed. table a-18. spi slave mode timing characteristics num c characteristic symbol min typ max unit 1 p sck frequency f sck dc ? 1 / 4f bus 1 p sck period t sck 4? t bus 2 d enable lead time t lead 4??t bus 3 d enable lag time t lag 4??t bus 4 d clock (sck) high or low time t wsck 4??t bus 5 d data setup time (inputs) t su 8??ns 6 d data hold time (inputs) t hi 8??ns 7 d slave access time (time to data active) t a ? ? 20 ns 8 d slave miso disable time t dis ? ? 22 ns 9 d data valid after sck edge t vsck ? ? 30 + t bus 1 1 t bus added due to internal synchronization delay ns 10 d data valid after ss fall t vss ? ? 30 + t bus 1 ns 11 d data hold time (outputs) t ho 20 ? ? ns 12 d rise and fall time inputs t rfi ?? 8 ns 13 d rise and fall time outputs t rfo ?? 8 ns appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 585 a.6 atd characteristics this section describes the characterist ics of the analog to digital converter. the atd is specified and tested for both the 3.3v and 5v range. for ranges between 3.3v and 5v the atd accuracy is generally the same as in the 3.3v range but is not tested in this range in production test. a.6.1 atd operating char acteristics ? 5v range the table a-19 shows conditions under which the atd operates. the following constraints exist to obt ain full-scale, full range results: vssa vrl vin vrh vdda . this constraint exists since th e sample buffer amplifier can not drive beyond the power supply levels th at it ties to. if the input level goes outside of this range it will effectively be clipped. a.6.2 atd operating characteristics ? 3.3v range the table a-20 shows conditions under which the atd operates. the following constraints exist to obt ain full-scale, full range results: vssa vrl vin vrh vdda . this constraint exists since th e sample buffer amplifier can not drive beyond the power supply levels th at it ties to. if the input level goes outside of this range it will effectively be clipped. table a-19. 5v atd operating characteristics conditions are shown in ta bl e a - 4 unless otherwise noted. supply voltage 5v-10% <= vdda <=5v+10% num c rating symbol min typ max unit 1 d reference potential low high v rl v rh v ssa v dda/2 ? ? v dda/2 v dda v v 2 c differential reference voltage 1 1 full accuracy is not guaranteed when differential voltage is less than 4.75v v rh ?v rl 4.75 5.0 5.25 v 3 d atd clock frequency f at d c l k 0.5 ? 2.0 mhz 4d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f at d c l k conv, time at 4.0mhz 3 atd clock f at d c l k 2 the minimum time assumes a final sample period of 2 atd clocks cycl es while the maximum time assumes a final sample period of 16 atd clocks. 3 reduced accuracy see ta b l e a - 2 2 and ta b l e a - 2 3 . n conv10 t conv10 t conv10 14 7 3.5 ? ? ? 28 14 7 cycles s s 5 d atd 8-bit conversion period clock cycles 1 conv, time at 2.0mhz atd clock f at d c l k n conv8 t conv8 12 6 ? ? 26 13 cycles s 6 d stop recovery time (v dda = 5.0 volts) t sr ??20 s 7 p reference supply current i ref ? ? 0.375 ma appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 586 freescale semiconductor a.6.3 factors influencing accuracy three factors ? source resistance, source capacitance and current inj ection ? have an influence on the accuracy of the atd. a.6.3.1 source resistance due to the input pin leakage current as specified in table a-6 and table a-7 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s specifies results in an error of less than 1/2 lsb (2.5mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced e rror is acceptable, larger values of source resistance are allowed. a.6.3.2 source capacitance when sampling an additional internal capacitor is switched to the input . this can cause a voltage drop due to charge sharing with the external and the pin ca pacitance. for a maximum sa mpling error of the input voltage 1lsb, then the external filter capacitor, c f 1024 * (c ins - c inn ). a.6.3.3 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel bei ng stressed has conversion values of 0x3ff (0xff in 8-bit mode) for anal og inputs greater than vrh and 0x000 for values less than vrl unless the current is higher than specified as disruptive conditions. table a-20. 3.3v atd operating characteristics conditions are shown in ta b l e a - 4 unless otherwise noted; supply voltage 3.3v-10% <= v dda <= 3.3v+10% num c rating symbol min typ max unit 1 d reference potential low high v rl v rh v ssa v dda /2 ? ? v dda /2 v dda v v 2 c differential reference voltage v rh -v rl 3.0 3.3 3.6 v 3 d atd clock frequency f at d c l k 0.5 ? 2.0 mhz 4 d atd 10-bit conversion period clock cycles 1 conv, time at 2.0mhz atd clock f at d c l k conv, time at 4.0mhz 2 atd clock f at d c l k 1 the minimum time assumes a fi nal sample period of 2 atd clocks cycles whil e the maximum time as sumes a final sample period of 16 atd clocks. 2 reduced accuracy see ta bl e a - 2 2 and ta bl e a - 2 3 . n conv10 t conv10 t conv10 14 7 3.5 ? ? ? 28 14 7 cycles s s 5 d atd 8-bit conversion period clock cycles 1 conv, time at 2.0mhz atd clock f at d c l k n conv8 t conv8 12 6 ? ? 26 13 cycles s 6 d recovery time (v dda =3.3 volts) t rec ??20 s 7 p reference supply current i ref ? ? 0.250 ma appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 587 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channe l (coupling ratio k), this additiona l current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err = k * r s * i inj , with i inj being the sum of the currents inj ected into the two pins adjacent to the converted channel. a.6.4 atd accuracy ? 5v range table a-22 specifies the atd conversion performance excludi ng any errors due to current injection, input capacitance and s ource resistance. table a-21. atd electrical characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance r s ?? 1 k ? 2 t total input capacitance non sampling sampling c inn c ins ? ? ? ? 10 15 pf 3 c disruptive analog input current i na ?2.5 ? 2.5 ma 4 c coupling ratio positive current injection k p ??10 -4 a/a 5 c coupling ratio negative current injection k n ??10 -2 a/a table a-22. 5v atd conversion performance conditions are shown in ta bl e a - 4 unless otherwise noted v ref = v rh - v rl = 5.12v. resulting to one 8 bit count = 20mv and one 10 bit count = 5mv f at d c l k = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb ? 5 ? mv 2 p 10-bit differential nonlinearity dnl ?1 ? 1 counts 3 p 10-bit integral nonlinearity inl ?2.0 ? 2.0 counts 4 p 10-bit absolute error 1 1 these values include quantization error which is inherently 1/2 count for any a/d converter. ae ?2.5 ? 2.5 counts 5 c 10-bit absolute error at f atdclk = 4mhz ae ? 7.0 ? counts 6 p 8-bit resolution lsb ? 20 ? mv 7 p 8-bit differential nonlinearity dnl ?0.5 ? 0.5 counts 8 p 8-bit integral nonlinearity inl ?1.0 0.5 1.0 counts 9 p 8-bit absolute error 1 ae ?1.5 1.0 1.5 counts appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 588 freescale semiconductor a.6.5 atd accuracy ? 3.3v range table a-23 specifies the atd conversion performance excludi ng any errors due to current injection, input capacitance and s ource resistance. for the following definitions see also figure a-9 . differential non-linearity (dnl) is defined as the differ ence between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: table a-23. 3.3v atd conversion performance conditions are shown in ta b l e a - 4 unless otherwise noted v ref = v rh - v rl = 3.328v. resulting to one 8 bit count = 13mv and one 10 bit count = 3.25mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb ? 3.25 ? mv 2 p 10-bit differential nonlinearity dnl ?1.5 1.5 counts 3 p 10-bit integral nonlinearity inl ?3.5 1.5 3.5 counts 4 p 10-bit absolute error 1 1 these values include the quantization error which is inherently 1/2 count for any a/d converter. ae ?5 2.5 5 counts 5 c 10-bit absolute error at f atdclk = 4mhz ae ? 7.0 ? counts 6 p 8-bit resolution lsb ? 13 ? mv 7 p 8-bit differential nonlinearity dnl ?0.5 ? 0.5 counts 8 p 8-bit integral nonlinearity inl ?1.5 1.0 1.5 counts 9 p 8-bit absolute error 1 ae ?2.0 1.5 2.0 counts dnl i () v i v i1 ? ? 1lsb --------------------------- 1 ? = inl n () dnl i () i1 = n v n v 0 ? 1lsb -------------------- - n ? == appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 589 figure a-9. atd accuracy definitions note figure a-9 shows only definitions, for sp ecification values refer to table a-22 and table a-23 . 1 5 vin mv 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 50 0x3f7 0x3f9 0x3f8 0x3fb 0x3fa 0x3fd 0x3fc 0x3fe 0x3ff 0x3f4 0x3f6 0x3f5 8 9 1 2 0xff 0xfe 0xfd 0x3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 5055 10-bit absolute error boundary 8-bit absolute error boundary lsb vi-1 vi dnl appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 590 freescale semiconductor a.7 dac characteristics this section describes the characterist ics of the digital to analog converter. a.7.1 dac operating characteristics a.8 external bus timing a timing diagram of the external mu ltiplexed-bus is illustrated in figure a-10 with the actual timing values shown on table table a-26 and table a-27 . all major bus signals are included in the diagram. while both a data write and data read cycle are show n, only one or the other would occur on a particular bus cycle. the expanded bus timings are highl y dependent on the load conditions . the timing parameters shown assume a balanced load across all outputs. table a-24. dac electrical characteristics (operating) num c characteristic condition symbol min typ max unit 1 d dac supply v dda 2.97 ? 5.5 v 2 d dac supply current running i ddarun ??3.5ma dstop (low power) i ddstop ??1.0ma 3 d reference potential low v ssa v ssa ?v ssa v d high v ref v dda /2 ? v dda v 4 d reference supply current v ref to v ssa i ref ??400ma 5 d input current, channel off 1 i off ?200 ? 1 a 6 d operating temperature range t ?40 ? 125 c table a-25. dac timing/perf ormance characteristics num c parameters symbol min typ max unit 1 d dac operating frequency f bus ??25mhz 2 d integral non-linearity inl ? 0.25 ? count 3 d differential non-linearity dnl ? 0.10 ? count 4 d resolution res ? ? 8 bit 5 d settling time t s 5?10 s 6 p absolute accuracy abs acc ?1 ? 1 count 7 d offset error err ? +/-2.5 ? mv appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 591 figure a-10. general external bus timing addr/data (read) addr/data (write) addr data data 5 10 11 8 16 6 eclk 1, 2 3 4 addr data data 12 15 9 7 14 13 ecs 21 20 22 23 non-multiplexed 17 19 lstrb 29 noacc 32 ipipo0 ipipo1, pe6,5 35 18 27 28 30 33 36 31 34 r/w 24 26 25 addresses pe4 pa, pb pa, pb pk5:0 pk7 pe2 pe3 pe7 appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 592 freescale semiconductor table a-26. expanded bus timing characteristics (5v range) conditions are 4.75v < vddx < 5.25v, junction temperature -40c to +140c, c load = 50pf num c rating symbol min typ max unit 1 p frequency of operation (e-clock) f o 0?25.0mhz 2 p cycle time t cyc 40 ? ? ns 3 d pulse width, e low pw el 19 ? ? ns 4 d pulse width, e high 1 1 affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. pw eh 19 ? ? ns 5 d address delay time t ad ?? 8ns 6 d address valid time to e rise (pw el ?t ad )t av 11 ? ? ns 7 d muxed address hold time t mah 2??ns 8 d address hold to data valid t ahds 7??ns 9 d data hold to address t dha 2??ns 10 d read data setup time t dsr 13 ? ? ns 11 d read data hold time t dhr 0??ns 12 d write data delay time t ddw ?? 7ns 13 d write data hold time t dhw 2??ns 14 d write data setup time 1 (pw eh ?t ddw )t dsw 12 ? ? ns 15 d address access time 1 (t cyc ?t ad ?t dsr )t acca 19 ? ? ns 16 d e high access time 1 (pw eh ?t dsr )t acce 6??ns 17 d non-multiplexed address delay time t nad ?? 6ns 18 d non-muxed address valid to e rise (pw el ?t nad )t nav 14 ? ? ns 19 d non-multiplexed address hold time t nah 2??ns 20 d chip select delay time t csd ? ? 16 ns 21 d chip select access time 1 (t cyc ?t csd ?t dsr )t accs 11 ? ? ns 22 d chip select hold time t csh 2??ns 23 d chip select negated time t csn 8??ns 24 d read/write delay time t rwd ?? 7ns 25 d read/write valid time to e rise (pw el ?t rwd )t rwv 14 ? ? ns 26 d read/write hold time t rwh 2??ns 27 d low strobe delay time t lsd ?? 7ns 28 d low strobe valid time to e rise (pw el ?t lsd )t lsv 14 ? ? ns 29 d low strobe hold time t lsh 2??ns 30 d noacc strobe delay time t nod ?? 7ns 31 d noacc valid time to e rise (pw el ?t nod )t nov 14 ? ? ns 32 d noacc hold time t noh 2 ?? ns 33 d ipipo[1:0] delay time t p0d 2 ? 7ns 34 d ipipo[1:0] valid time to e rise (pw el ?t p0d ) t p0v 11 ?? ns 35 d ipipo[1:0] delay time 1 (pw eh -t p1v ) t p1d 2 ? 25 ns 36 d ipipo[1:0] valid time to e fall t p1v 11 ?? ns appendix a electrical characteristics mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 593 table a-27. expanded bus timing characteristics (3.3v range) conditions are vddx=3.3v+/-10%, junction temperature -40c to +140c, c load = 50pf num c rating symbol min typ max unit 1 p frequency of operation (e-clock) f o 0 ? 16.0 mhz 2 p cycle time t cyc 62.5 ? ? ns 3 d pulse width, e low pw el 30 ? ? ns 4 d pulse width, e high 1 1 affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. pw eh 30 ? ? ns 5 d address delay time t ad ? ? 16 ns 6 d address valid time to e rise (pw el ?t ad )t av 16 ? ? ns 7 d muxed address hold time t mah 2??ns 8 d address hold to data valid t ahds 7??ns 9 d data hold to address t dha 2??ns 10 d read data setup time t dsr 15 ? ? ns 11 d read data hold time t dhr 0??ns 12 d write data delay time t ddw ? ? 15 ns 13 d write data hold time t dhw 2??ns 14 d write data setup time 1 (pw eh ?t ddw )t dsw 15 ? ? ns 15 d address access time 1 (t cyc ?t ad ?t dsr )t acca 29 ? ? ns 16 d e high access time 1 (pw eh ?t dsr )t acce 15 ? ? ns 17 d non-multiplexed address delay time t nad ? ? 14 ns 18 d non-muxed address valid to e rise (pw el ?t nad )t nav 16 ? ? ns 19 d non-multiplexed address hold time t nah 2??ns 20 d chip select delay time t csd ? ? 25 ns 21 d chip select access time 1 (t cyc ?t csd ?t dsr )t accs 22.5 ? ? ns 22 d chip select hold time t csh 2??ns 23 d chip select negated time t csn 8??ns 24 d read/write delay time t rwd ? ? 14 ns 25 d read/write valid time to e rise (pw el ?t rwd )t rwv 16 ? ? ns 26 d read/write hold time t rwh 2??ns 27 d low strobe delay time t lsd ? ? 14 ns 28 d low strobe valid time to e rise (pw el ?t lsd )t lsv 16 ? ? ns 29 d low strobe hold time t lsh 2??ns 30 d noacc strobe delay time t nod ? ? 14 ns 31 d noacc valid time to e rise (pw el ?t nod )t nov 16 ? ? ns 32 d noacc hold time t noh 2??ns 33 d ipipo[1:0] delay time t p0d 2 ? 14 ns 34 d ipipo[1:0] valid time to e rise (pw el ?t p0d )t p0v 16 ? ? ns 35 d ipipo[1:0] delay time 1 (pw eh -t p1v )t p1d 2?25 ns 36 d ipipo[1:0] valid time to e fall t p1v 11 ? ? ns mc9s12e256 data sheet, rev. 1.08 freescale semiconductor 594 appendix b ordering information and mechanical drawings figure b-1. order part number coding table b-1 lists the part number coding base d on the package and temperature. table b-2 summarizes the package opti on and size configuration. table b-1. part number coding part number temperature package mc9s12e256cfu -40c, 85c 80 qfp mc9s12e256cpv -40c, 85c 112 lqfp MC9S12E256MFU -40c, 125c 80 qfp mc9s12e256mpv -40c, 125c 112 lqfp table b-2. package option summary part number package temp. 1 options 1 c: t a = 85c, f = 25mhz. m: t a = 125c, f = 25mhz flash ram mebi tim sci spi iic a/d d/a pwm pmf kwu i/o 2 2 i/o is the sum of ports capable to act as digital input or output. tim is the number of channels. a/d is the number of a/d channels. d/a is the number of d/a channels. pwm is the number of channels. pmf is the number of channels. kwu is the number of key wake up interrupt pins. i/o is the sum of ports capable to act as digital input or output. mc9s12e256 112lqfp m, c 256k 16k 1 12 3 1 1 16 2 6 6 16 92 80qfp 0 60 mc9s12 e256 c fu package option temperature option device title controller family temperature options package options fu = 80 qfp pv = 112 lqfp c = ?40c to 85c v = ?40c to 105c m = ?40c to 125c how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006. all rights reserved. mc9s12e256 rev. 1.08, 01/2006 |
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